JPH03248611A - Temperature compensation gain setting controller - Google Patents
Temperature compensation gain setting controllerInfo
- Publication number
- JPH03248611A JPH03248611A JP4654690A JP4654690A JPH03248611A JP H03248611 A JPH03248611 A JP H03248611A JP 4654690 A JP4654690 A JP 4654690A JP 4654690 A JP4654690 A JP 4654690A JP H03248611 A JPH03248611 A JP H03248611A
- Authority
- JP
- Japan
- Prior art keywords
- converter
- output
- gain
- rom
- telecommand
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000005070 sampling Methods 0.000 abstract description 4
- 230000007257 malfunction Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、マイクロ波回路から構成される衛星搭載用
中継器（以下中継器）の持つ利得を外部コマンドにより
一定ステップで可変させ、かつ温度変動による利得変位
を補償した利得割前装置に関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention allows the gain of a satellite-mounted repeater (hereinafter referred to as a repeater) consisting of a microwave circuit to be varied in fixed steps by an external command, and The present invention relates to a gain dividing device that compensates for gain displacement due to fluctuations.
従来、この種の装置として第２図に示されるものがあっ
た。（１）はテレコマンド入力端子、（２）はゲインス
テータスデコーダ、 （３１はＲＯＭ、（４１は〕ｆワ
ーオンリセット回路、（５）は利得増加を指示する第１
のテレコマンド信号、（６）は利得減少を指示する第２
のテレコマンド１＝号、（７）はＡ／Ｄコンノ（−夕。Conventionally, there has been a device of this type as shown in FIG. (1) is a telecommand input terminal, (2) is a gain status decoder, (31 is a ROM, (41 is a) f-war-on reset circuit, (5) is a first input terminal that instructs a gain increase.
(6) is the second telecommand signal commanding gain reduction.
Telecommand number 1, (7) is the A/D controller (-evening).
（８）は抵抗器、（９）はサーミスタ、α０）は第１の
ラッチ。(8) is a resistor, (9) is a thermistor, and α0) is the first latch.
（ｌυは第１のＡＮＤゲート、面はＮＯＲゲーグーｆｌ
りは発振器、 （１４１は第１のＯＲゲグー−、Ｑ５１
は第２のＯＲゲート、０６１は第３のＯＲゲート、（１
７１はスイッチングトランジスタ、［Ｂは第２のラッチ
、 （１９１は第２のＡＮＤゲーグー（２ｆｉ）はＤ／
Ａコンバータ、（２１１は可変アッテネータバイアス端
子である。第３図は中継語における利得制御装置の位置
付けを示す。（至）は温度補償利得設定制御装置、閣は
第１のＲＦ帯増輻器、 （ｓｏ）は第２のＲＦ帯増幅蕾
、 （６０）は可変アッテネータを示す。(lυ is the first AND gate, face is NOR game fl
ri is an oscillator, (141 is the first OR game, Q51
is the second OR gate, 061 is the third OR gate, (1
71 is a switching transistor, [B is a second latch, (191 is a second AND gate (2fi) is a D/
A converter, (211 is a variable attenuator bias terminal. Figure 3 shows the positioning of the gain control device in the relay word. (To) is the temperature compensation gain setting control device, and 211 is the first RF band amplifier, (so) indicates the second RF band amplification bud, and (60) indicates a variable attenuator.
次に動作について説明する。外部より送信されろテレコ
マンド信号が入力端子（１）に印加されると。Next, the operation will be explained. When a telecommand signal transmitted from the outside is applied to the input terminal (1).
ゲインステータスデコーダ（２）の内容が更新され。The contents of the gain status decoder (2) are updated.
その出力がＲＯＭ （３’ｌのアドレスとして出力され
る。The output is output as the address of ROM (3'l).
ゲインステータスデコーダ（２）は電源投入時にパワー
オンリセット回路（４）によって発生するパルスにより
−Ｈリセットされた後、利得増加のテレコマンド信号（
５）、利＃！減少のテレコマンド（６）を受は設定利得
を解読する。ＲＯＭ ［３１にはゲインステータスデコ
ーダ（２）の出力とは全く独立な Ａ／Ｄコンバータ（
７）の出力が印加されろ。Ａ／Ｄコンバータ（７）の入
力は抵抗器（８）とサーミスタ（９）の接続点の電位で
ある。温度変動に伴いサーミスタ（９）の抵抗値が変り
、接続点電位の変動量がＡ／Ｄコンバータ（７）の持つ
しきい値を越えると、Ａ／Ｄコンバータ（７）の出力も
変化する。Ａ／Ｄコンバータの出力はＲＯＭアドレスの
他にラッチ（１０１，ＡＮＤゲーグーＤとＮＯＲゲート
叩にもそのＬＳＢだけ印加される。ラッチα０）では発
振器０３）の発生するクロック周期毎に。After the gain status decoder (2) is reset to -H by a pulse generated by the power-on reset circuit (4) when the power is turned on, the gain increase telecommand signal (
5), profit #! The receiver of the decrease telecommand (6) decodes the set gain. ROM [31 has an A/D converter (
7) is applied. The input of the A/D converter (7) is the potential at the connection point between the resistor (8) and thermistor (9). When the resistance value of the thermistor (9) changes with temperature fluctuation and the amount of change in the connection point potential exceeds the threshold value of the A/D converter (7), the output of the A/D converter (7) also changes. The output of the A/D converter is applied not only to the ROM address but also to the latch (101, AND game D and NOR gate).In the latch α0), every clock cycle generated by the oscillator 03).
Ａ／Ｄコンバータ（７）のＬＳＢを取込み、ＡＮＤゲー
ト（社）、ＮＯＲゲート叩へ出力する。ＡＮＤゲート０
１）及びＮＯＲゲート叩ではクロックにて温度状況をサ
ンプリングし、１サンプリング周期の間でＬＳＢの変化
が認められた時、ＯＲゲグー圓を通じて温度変化のステ
ータスを出す。一方、パルスコマンド信号においても２
ケある内の一方のコマンドが送られてきｔこ時、ＯＲゲ
グー■を通じて利得変化のステータスを知らせる。加え
て電源投入時発生するパワーオンリセットパルスとの論
理和がイネーブルになった時のみ１周囲温度状況下の設
定利得を可変アッテネータのバイアス値が書き込まれた
Ｒ ＯＭ ［３１に電圧が印加する様、ＯＲゲグー圓の
出力をスイッチングトランジスタ面のベースへ接続しト
ランジスタ面を導通状態としてＲＯＭ（３）へ電流を流
す。なお、この状態は１クロック周期のみ持続するため
ＲＯＭ ＋３１の出力が消滅しない様ラッチ（至）にて
次の利得変更時まで保持される。It takes in the LSB of the A/D converter (7) and outputs it to the AND gate (Inc.) and NOR gate. AND gate 0
1) In the case of hitting the NOR gate, the temperature situation is sampled by the clock, and when a change in LSB is recognized within one sampling period, the status of the temperature change is output through the OR gate. On the other hand, the pulse command signal also has 2
When one of the commands is sent, the status of the gain change is notified through ORG. In addition, only when the logical sum with the power-on reset pulse generated when the power is turned on is enabled, the voltage is applied to the ROM [31] in which the bias value of the variable attenuator is written to set the gain under the ambient temperature condition. , the output of the OR gate is connected to the base of the switching transistor surface, the transistor surface is made conductive, and a current flows to the ROM (3). Note that this state lasts for only one clock period, so it is held by a latch until the next gain change so that the output of ROM +31 does not disappear.
次の利得変更時はＡＮＤゲート（２）より得られるパル
スでＲＯＭ （３１の出力を再び取込む。ラッチ（至）
で保持される設定利得データは、Ｄ／Ａコンバータ（至
）によりアナログ電圧へ変換され、可変アッテネータバ
イアスとして可変アッテネータパスアス端子四より出力
される。At the next gain change, the output of ROM (31) is taken in again using the pulse obtained from the AND gate (2). Latch (to)
The setting gain data held in is converted into an analog voltage by the D/A converter (to), and outputted from the variable attenuator pass terminal 4 as a variable attenuator bias.
従来の温度補償利得設定制御装置は以上のように構成さ
れているので２本装置中のＲＯＭの出力をラッチするフ
リップフロップが放射線の影響によレビット反転を起こ
し、誤動作を起こすという課題があった。Since the conventional temperature compensation gain setting control device is configured as described above, there was a problem in that the flip-flops that latched the output of the ROM in the two devices caused Levitt inversion due to the influence of radiation, causing malfunction. .
この発明は上記のような課題を解消するためになされた
もので、放射線の影響を受けない信頼性の高い温度補償
利得設定制御装置を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a highly reliable temperature compensation gain setting control device that is not affected by radiation.
この発明に係る温度補償利得設定制御装置は。 A temperature compensation gain setting control device according to the present invention.
ＲＯＭの出力をラッチせず、Ｄ／Ａ変換後のアナログ値
をホールドするため、ＲＯＭへの通電時間を電源投入時
、パルスコマンド受信時及び温度状況変更時に限定した
まま放射線の影響を無視てきる様サンプルホールド回路
を用いたものである。Since the ROM output is not latched and the analog value after D/A conversion is held, the influence of radiation can be ignored while energizing the ROM is limited to when the power is turned on, when receiving pulse commands, and when changing temperature conditions. It uses a similar sample-and-hold circuit.
この発明は、サンプリングにてＲＯＭを動作させ、 Ｄ
／Ａコンバータの出力をホールドすることによりディ
ジタルのラッチ回路を削減し、低消費電力でより小型な
回路規模の信頼性の高い装置が実現できる。This invention operates the ROM by sampling, and D
By holding the output of the /A converter, the number of digital latch circuits can be reduced, and a highly reliable device with low power consumption and smaller circuit scale can be realized.
以下、この発明の一実施例を図について説明する。第１
図において、 ＋１１ 、［２） 、（３１、（４］
、（５１、（６１、（７１、（８） 。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, +11, [2), (31, (4]
, (51, (61, (71, (8)).
（９１、（１０１、（Ｉｌｌ 、 （１２） 、 （１
３１、（１４１、Ｑ５１ 、 ［６１、（Ｉ７１． （
２ｍ 、 （２１１ハ従来装置と全く同一のものである
。―ばＦＥＴ、Ｇ！３１はオペアンプ、 Ｇ！４１はコ
ンデンサを示す。(91, (101, (Ill), (12), (1
31, (141, Q51, [61, (I71.
2m, (211C is exactly the same as the conventional device. - is a FET, G!31 is an operational amplifier, and G!41 is a capacitor.
次に動作について説明する。外部より送信されろテレコ
マンド信号が入力端子（１）に印加されるとゲインステ
ータスデコーダ（２）の内容が更新され。Next, the operation will be explained. When a telecommand signal transmitted from the outside is applied to the input terminal (1), the contents of the gain status decoder (2) are updated.
その出力がＲＯＭ ＋３１のアドレスとして出力される
。The output is output as the address of ROM +31.
ゲインステータスデコーダ（２）は電源投入時にパワー
オンリセット回路（４）によって発生するパルスにより
一旦リセットされた後、利得増加のテレコマンド信号（
５）、利得減少のテレコマンド信号（６）を受け、設定
利得を解読する。ＲＯＭ ＋３１にはゲインステータス
デコーダ（２）の出力とは全く独立な Ａ／Ｄコンバー
タ（７）の出力が印加されろ。Ａ／Ｄコンバータ（７）
の入力は抵抗器（８）とサーミスタ（９）の接続点の電
位である。温度変動に伴いサーミスタ（９）の抵抗値が
変り、接続点電位の変動量がＡ／Ｄコンバータ（７）の
持つしきい値を超えると、Ａ／Ｄコンバータ（７）の出
力も変化する。Ａ／Ｄコンバータ（７）の出力はＲＯＭ
アドレスの他にラッチＱＱ）、ＡＮＤゲート（Ｉｌｌと
ＮＯＲゲート口にもそのＬＳＢだけ印加される。ラッチ
α０）では発振器α３）が発生するクロック周期毎に、
Ａ／Ｄコンバータ（７）のＬＳＢを取込み、ＡＮＤゲー
グーｌ、ＮＯＲゲート口へ出力する。ＡＮＤゲーグーＤ
及びＮＯＲゲート口てはクロックにて温度状況をサンプ
リングし、１サンプリング周期の間でＬＳＢの変化が認
められた時、ＯＲゲグーＱ４］を通して温度変化のステ
ータスを出す。一方。The gain status decoder (2) is reset by a pulse generated by the power-on reset circuit (4) when the power is turned on, and then receives a gain increase telecommand signal (
5) Receive the gain reduction telecommand signal (6) and decipher the set gain. The output of the A/D converter (7), which is completely independent of the output of the gain status decoder (2), is applied to ROM +31. A/D converter (7)
The input is the potential at the connection point between the resistor (8) and thermistor (9). When the resistance value of the thermistor (9) changes with temperature fluctuation and the amount of change in the connection point potential exceeds the threshold value of the A/D converter (7), the output of the A/D converter (7) also changes. The output of A/D converter (7) is ROM
In addition to the address, only the LSB is applied to the latch QQ), the AND gate (Ill, and the NOR gate port.In the latch α0), every clock period generated by the oscillator α3),
It takes in the LSB of the A/D converter (7) and outputs it to the AND gate and NOR gate. AND game goo D
The temperature status is sampled by the clock at the NOR gate, and when a change in LSB is recognized within one sampling period, the status of the temperature change is output through the OR gate Q4. on the other hand.
パルスコマンド信号においても２ケある内の一方のコマ
ンドが送られてきた時、ＯＲゲグー印を通じて利得変化
のステータスを知らせる。加えて電源投入時発生するパ
ワーオンリセットパルスの論理和がイネーブルになった
時のみ２周囲温度状況下の設定利得を可変アッテネータ
のバイアス値が書き込まれたＲ ＯＭ （３）に電圧が
印加する様、ＯＲゲグー圓の出力をスイッチングトラン
ジスターのベースへ接続し、トランジスタＵ）を導通状
態としてＲＯＭ （３１へ電流を流す。ＲＯＭ （３１
より出力される可変アッテネータバイアスは、 Ｄ ／
Ａコンバータ（至）にてアナログ量へ変換される。Ｄ／
ＡコンバータＧ！ｍにより変換された可変アッテネータ
バイアスはＦＥＴ（２２１のドレインに印加され、その
ゲートへ接続されているＯＲゲグー印がイネーブルにな
った時ソースへその値をホールドする。ホールド時間は
オペアンプ囚の入力インピーダンス及びコンデンサ（２
匂の容量により決まる。Also in the pulse command signal, when one of the two commands is sent, the status of the gain change is notified through the OR signal. In addition, only when the logical sum of the power-on reset pulses that occur when the power is turned on is enabled, a voltage is applied to the ROM (3) in which the bias value of the variable attenuator is written, and the gain is variable under two ambient temperature conditions. , connect the output of the OR gate to the base of the switching transistor, turn on the transistor U), and flow current to ROM (31).ROM (31
The variable attenuator bias output from D/
It is converted into an analog quantity by the A converter (to). D/
A converter G! The variable attenuator bias converted by m is applied to the drain of the FET (221) and holds its value to the source when the OR gate connected to its gate is enabled.The hold time is determined by the input impedance of the op amp. and capacitor (2
Determined by scent capacity.
今、可変アッテネータの設定精度をｎｚとすると。Now, let nz be the setting accuracy of the variable attenuator.
１００− ｎ ＝ ｅ −”’ となり。100-n=e-”’ Next door.
で、オペアンプの入力インピーダンスをＲＭΩ。So, the input impedance of the operational amplifier is RMΩ.
コンデンサの容量をＣｕＦとした時。When the capacitor capacity is CuF.
となる。この場合２発振器のクロック周期は。becomes. In this case, the clock period of the two oscillators is.
以下とすればよい。オペアンプの出力はトランジスタ固
を介して可変アッテネータバイアス端子（２１１へ供給
される。The following may be used. The output of the operational amplifier is supplied to a variable attenuator bias terminal (211) via a transistor.
以上のようにこの発明によれば、サンプリングにてＲＯ
Ｍを動作させ、可変アッテネータバイアス値をホールド
しているので、低消費電力でｆｉ射線による誤動作のな
い信頼性の高い温度補償利得設定制御装置が得られる効
果がある。As described above, according to the present invention, RO
Since M is operated and the variable attenuator bias value is held, a highly reliable temperature compensation gain setting control device with low power consumption and no malfunction due to fi rays can be obtained.
第１図はこの発明の一実施例による温度補償利得設定制
御装置を示すブロック図、第２図は従来の温度補償利得
設定制御装置を示す図、第３図は中継器の一実施例を示
す図である。（１）はテレコマンド入力端子、（２）は
ゲインステータスデコーダ。
（３）はＲＯＭ、［４１はパワーオンリセット、（５）
は利得増加のテレコマンド信号、（６）は利得減少のテ
レコマンド信号、（７）はＡ／Ｄコンバータ、（８）は
抵抗器。
（９）はサーミスタ、ａωはラッチ、ｆｉｌ）はＡＮＤ
ゲート。
回はＮＯＲゲート、０３）は発振器、圓は第１のＯＲゲ
ート、Ｑ５１は第２のＯＲゲート、（ト）は第３のＯＲ
ゲート、（１７１はスイッチングトランジスタ、（２）
はＤ／Ａコンバータ、＋２１１は可変アッテネータバイ
アス端子。
（至）はＦＥＴ、（！＋１はオペアンプ、 （２４１は
コンデンサ。
固はトランジスタを示す。
なお２図中、同一符号は同一または相当部分を示す。FIG. 1 is a block diagram showing a temperature compensation gain setting control device according to an embodiment of the present invention, FIG. 2 is a diagram showing a conventional temperature compensation gain setting control device, and FIG. 3 is a block diagram showing an embodiment of a repeater. It is a diagram. (1) is a telecommand input terminal, and (2) is a gain status decoder. (3) is ROM, [41 is power-on reset, (5)
is a telecommand signal with increased gain, (6) is a telecommand signal with decreased gain, (7) is an A/D converter, and (8) is a resistor. (9) is a thermistor, aω is a latch, fil) is AND
Gate. times is a NOR gate, 03) is an oscillator, 圓 is the first OR gate, Q51 is the second OR gate, (g) is the third OR gate
Gate, (171 is a switching transistor, (2)
is a D/A converter, and +211 is a variable attenuator bias terminal. (to) is a FET, (!+1 is an operational amplifier, (241 is a capacitor, and solid is a transistor. In Figure 2, the same reference numerals indicate the same or equivalent parts.
Claims (1)
コマンド信号から設定利得状態を解読するゲインステー
タスデコーダと、電源とアース間に直列に接続された抵
抗器とサーミスタと、上記抵抗器とサーミスタとの接続
点の電位を取込むＡ／Ｄコンバータと２パワーオンリセ
ット回路の出力、２ケのテレコマンドパルスの論理和ま
たは上記Ａ／Ｄコンバータの最下位ビットと、上記最下
位ビットをラッチ回路に介した出力の論理演算結果との
論理和が、ベースへ接続されているトランジスタを介し
て電圧が印加され、上記ゲインステータスデコーダ、Ａ
／Ｄコンバータの並列出力信号をアドレスとし、周囲温
度状況下に適合した利得設定値に対応した減衰量を得る
ために必要な電圧値を読み出すＲＯＭと、このＲＯＭ出
力をアナログ量へ変換するＤ／Ａコンバータと、このＤ
／Ａコンバータ出力をドレインに取込み、クロック及び
上記パワーオンリセットと、テレコマンドパルスと、上
記Ａ／Ｄコンバータ最下位ビットのラッチ前後の論理演
算結果との論理和がゲートに印加されることによりＤ／
Ａコンバータの出力値をソースにホールドするＦＥＴと
、このＦＥＴのソースとアース間に直列に接続されたコ
ンデンサと、上記ＦＥＴのソースに非反転入力端子が接
続されたオペアンプ及びこのオペアンプ出力に直列に接
続されたトランジスタ、このトランジスタのエミッタよ
り可変アッテネータへそのバイアスを供給する出力端子
とを備えたことを特徴とする温度補償利得設定制御装置
。a gain status decoder having an input terminal into which a telecommand pulse is input and decoding a set gain state from the input command signal; a resistor and thermistor connected in series between a power supply and ground; and the resistor and thermistor. The output of the A/D converter and the two power-on reset circuits that take the potential at the connection point, the OR of the two telecommand pulses, or the least significant bit of the A/D converter and the least significant bit of the above to the latch circuit. A voltage is applied through the transistor connected to the base of the gain status decoder, A.
A ROM that uses the parallel output signal of the /D converter as an address and reads out the voltage value necessary to obtain the attenuation amount corresponding to the gain setting value suitable for the ambient temperature condition, and a D/D converter that converts this ROM output into an analog value. A converter and this D
/A converter output is taken into the drain, and the logical sum of the clock, the power-on reset, the telecommand pulse, and the logical operation results before and after the latch of the lowest bit of the A/D converter is applied to the gate. /
A FET that holds the output value of the A converter in its source, a capacitor connected in series between the source of this FET and the ground, an operational amplifier whose non-inverting input terminal is connected to the source of the FET, and an operational amplifier connected in series to the output of this operational amplifier. A temperature compensated gain setting control device comprising a transistor connected to the transistor and an output terminal for supplying a bias from the emitter of the transistor to a variable attenuator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4654690A JPH03248611A (en) | 1990-02-27 | 1990-02-27 | Temperature compensation gain setting controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4654690A JPH03248611A (en) | 1990-02-27 | 1990-02-27 | Temperature compensation gain setting controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03248611A true JPH03248611A (en) | 1991-11-06 |
Family
ID=12750310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4654690A Pending JPH03248611A (en) | 1990-02-27 | 1990-02-27 | Temperature compensation gain setting controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03248611A (en) |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011513706A (en) * | 2008-02-26 | 2011-04-28 | アレグロ・マイクロシステムズ・インコーポレーテッド | Magnetic field sensor with automatic sensitivity adjustment |
| US8680846B2 (en) | 2011-04-27 | 2014-03-25 | Allegro Microsystems, Llc | Circuits and methods for self-calibrating or self-testing a magnetic field sensor |
| US8692546B2 (en) | 2009-07-22 | 2014-04-08 | Allegro Microsystems, Llc | Circuits and methods for generating a diagnostic mode of operation in a magnetic field sensor |
| US8818749B2 (en) | 2009-02-17 | 2014-08-26 | Allegro Microsystems, Llc | Circuits and methods for generating a self-test of a magnetic field sensor |
| US9201122B2 (en) | 2012-02-16 | 2015-12-01 | Allegro Microsystems, Llc | Circuits and methods using adjustable feedback for self-calibrating or self-testing a magnetic field sensor with an adjustable time constant |
| JP2015215177A (en) * | 2014-05-08 | 2015-12-03 | セイコーエプソン株式会社 | Circuit device, temperature detector, electronic apparatus and temperature detection method |
| US9638764B2 (en) | 2015-04-08 | 2017-05-02 | Allegro Microsystems, Llc | Electronic circuit for driving a hall effect element with a current compensated for substrate stress |
| US9645220B2 (en) | 2014-04-17 | 2017-05-09 | Allegro Microsystems, Llc | Circuits and methods for self-calibrating or self-testing a magnetic field sensor using phase discrimination |
| US9735773B2 (en) | 2014-04-29 | 2017-08-15 | Allegro Microsystems, Llc | Systems and methods for sensing current through a low-side field effect transistor |
| US9804249B2 (en) | 2014-11-14 | 2017-10-31 | Allegro Microsystems, Llc | Dual-path analog to digital converter |
| US9841485B2 (en) | 2014-11-14 | 2017-12-12 | Allegro Microsystems, Llc | Magnetic field sensor having calibration circuitry and techniques |
| US9851417B2 (en) | 2015-07-28 | 2017-12-26 | Allegro Microsystems, Llc | Structure and system for simultaneous sensing a magnetic field and mechanical stress |
| US10107873B2 (en) | 2016-03-10 | 2018-10-23 | Allegro Microsystems, Llc | Electronic circuit for compensating a sensitivity drift of a hall effect element due to stress |
| US10132879B2 (en) | 2016-05-23 | 2018-11-20 | Allegro Microsystems, Llc | Gain equalization for multiple axis magnetic field sensing |
| US10162017B2 (en) | 2016-07-12 | 2018-12-25 | Allegro Microsystems, Llc | Systems and methods for reducing high order hall plate sensitivity temperature coefficients |
| US10466298B2 (en) | 2014-11-14 | 2019-11-05 | Allegro Microsystems, Llc | Magnetic field sensor with shared path amplifier and analog-to-digital-converter |
| US10520559B2 (en) | 2017-08-14 | 2019-12-31 | Allegro Microsystems, Llc | Arrangements for Hall effect elements and vertical epi resistors upon a substrate |
| US11169223B2 (en) | 2020-03-23 | 2021-11-09 | Allegro Microsystems, Llc | Hall element signal calibrating in angle sensor |
| US11630130B2 (en) | 2021-03-31 | 2023-04-18 | Allegro Microsystems, Llc | Channel sensitivity matching |
| US11994541B2 (en) | 2022-04-15 | 2024-05-28 | Allegro Microsystems, Llc | Current sensor assemblies for low currents |
-
1990
- 1990-02-27 JP JP4654690A patent/JPH03248611A/en active Pending
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013224958A (en) * | 2008-02-26 | 2013-10-31 | Allegro Microsystems Llc | Magnetic field sensor with automatic sensitivity adjustment |
| JP2011513706A (en) * | 2008-02-26 | 2011-04-28 | アレグロ・マイクロシステムズ・インコーポレーテッド | Magnetic field sensor with automatic sensitivity adjustment |
| US8818749B2 (en) | 2009-02-17 | 2014-08-26 | Allegro Microsystems, Llc | Circuits and methods for generating a self-test of a magnetic field sensor |
| US9151807B2 (en) | 2009-02-17 | 2015-10-06 | Allegro Microsystems, Llc | Circuits and methods for generating a self-test of a magnetic field sensor |
| US8692546B2 (en) | 2009-07-22 | 2014-04-08 | Allegro Microsystems, Llc | Circuits and methods for generating a diagnostic mode of operation in a magnetic field sensor |
| US8680846B2 (en) | 2011-04-27 | 2014-03-25 | Allegro Microsystems, Llc | Circuits and methods for self-calibrating or self-testing a magnetic field sensor |
| US9201122B2 (en) | 2012-02-16 | 2015-12-01 | Allegro Microsystems, Llc | Circuits and methods using adjustable feedback for self-calibrating or self-testing a magnetic field sensor with an adjustable time constant |
| US9645220B2 (en) | 2014-04-17 | 2017-05-09 | Allegro Microsystems, Llc | Circuits and methods for self-calibrating or self-testing a magnetic field sensor using phase discrimination |
| US9735773B2 (en) | 2014-04-29 | 2017-08-15 | Allegro Microsystems, Llc | Systems and methods for sensing current through a low-side field effect transistor |
| JP2015215177A (en) * | 2014-05-08 | 2015-12-03 | セイコーエプソン株式会社 | Circuit device, temperature detector, electronic apparatus and temperature detection method |
| US9841485B2 (en) | 2014-11-14 | 2017-12-12 | Allegro Microsystems, Llc | Magnetic field sensor having calibration circuitry and techniques |
| US10466298B2 (en) | 2014-11-14 | 2019-11-05 | Allegro Microsystems, Llc | Magnetic field sensor with shared path amplifier and analog-to-digital-converter |
| US9804249B2 (en) | 2014-11-14 | 2017-10-31 | Allegro Microsystems, Llc | Dual-path analog to digital converter |
| US9638764B2 (en) | 2015-04-08 | 2017-05-02 | Allegro Microsystems, Llc | Electronic circuit for driving a hall effect element with a current compensated for substrate stress |
| US9851417B2 (en) | 2015-07-28 | 2017-12-26 | Allegro Microsystems, Llc | Structure and system for simultaneous sensing a magnetic field and mechanical stress |
| US10746817B2 (en) | 2015-07-28 | 2020-08-18 | Allegro Microsystems, Llc | Structure and system for simultaneous sensing a magnetic field and mechanical stress |
| US10107873B2 (en) | 2016-03-10 | 2018-10-23 | Allegro Microsystems, Llc | Electronic circuit for compensating a sensitivity drift of a hall effect element due to stress |
| US10254354B2 (en) | 2016-03-10 | 2019-04-09 | Allegro Microsystems, Llc | Electronic circuit for compensating a sensitivity drift of a hall effect element due to stress |
| US10132879B2 (en) | 2016-05-23 | 2018-11-20 | Allegro Microsystems, Llc | Gain equalization for multiple axis magnetic field sensing |
| US10908232B2 (en) | 2016-05-23 | 2021-02-02 | Allegro Microsystems, Llc | Gain equalization for multiple axis magnetic field sensing |
| US10162017B2 (en) | 2016-07-12 | 2018-12-25 | Allegro Microsystems, Llc | Systems and methods for reducing high order hall plate sensitivity temperature coefficients |
| US10746818B2 (en) | 2016-07-12 | 2020-08-18 | Allegro Microsystems, Llc | Systems and methods for reducing high order hall plate sensitivity temperature coefficients |
| US10520559B2 (en) | 2017-08-14 | 2019-12-31 | Allegro Microsystems, Llc | Arrangements for Hall effect elements and vertical epi resistors upon a substrate |
| US11169223B2 (en) | 2020-03-23 | 2021-11-09 | Allegro Microsystems, Llc | Hall element signal calibrating in angle sensor |
| US11630130B2 (en) | 2021-03-31 | 2023-04-18 | Allegro Microsystems, Llc | Channel sensitivity matching |
| US11994541B2 (en) | 2022-04-15 | 2024-05-28 | Allegro Microsystems, Llc | Current sensor assemblies for low currents |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH03248611A (en) | Temperature compensation gain setting controller | |
| CA1213948A (en) | Gain amplifier | |
| US7567103B2 (en) | Apparatus for detecting and preventing a lock failure in a delay-locked loop | |
| EP1794882A2 (en) | Programmable low noise amplifier and method | |
| US7679417B2 (en) | Attenuator with bias control circuit | |
| US9087567B2 (en) | Method and apparatus for amplifier offset calibration | |
| CN106877943B (en) | Communication transceiver using loopback calibration and calibration method of transmitting power thereof | |
| JP2003142991A (en) | Comparing circuit, comparator, level judging circuit and method for setting threshold voltage in level judging circuit | |
| US10914805B2 (en) | Signal error calibrating method | |
| CN109067371B (en) | Resistance-network-free programmable gain amplifier circuit | |
| US8294487B2 (en) | Configuration setting device of integrated circuit and the configuration setting method thereof | |
| JPH03179906A (en) | Temperature compensation type gain setting controller | |
| US4992756A (en) | Low offset transconductance amplifier in an analog electronic cochlea | |
| CN114204939A (en) | Offset voltage correction circuit and offset voltage correction method | |
| JPH0423606A (en) | Temperature compensation gain setting controller | |
| US20150244391A1 (en) | Ramp signal generator using programmable gain amplifier | |
| JPH05342380A (en) | Operation mode control circuit for microcomputer | |
| JPH10256488A (en) | Operation mode setting circuit | |
| JP2013025772A (en) | Two-wire transmitter | |
| KR890002314B1 (en) | Analog-digital converting circuit | |
| US7936620B2 (en) | Receiver of semiconductor memory apparatus | |
| JPH04351071A (en) | Gamma correction circuit for liquid crystal display device | |
| JPS61252707A (en) | Latch circuit | |
| KR200187772Y1 (en) | Control apparatus for delay time | |
| JPS54122946A (en) | Self diagnosis unit |