JPH0324788U - - Google Patents
Info
- Publication number
- JPH0324788U JPH0324788U JP8533789U JP8533789U JPH0324788U JP H0324788 U JPH0324788 U JP H0324788U JP 8533789 U JP8533789 U JP 8533789U JP 8533789 U JP8533789 U JP 8533789U JP H0324788 U JPH0324788 U JP H0324788U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- interpolation
- output
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 4
- 230000003111 delayed effect Effects 0.000 claims 2
- 238000010561 standard procedure Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 7
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Television Systems (AREA)
Description
第１図はこの考案の一実施例を示す回路図、第
２図は第１図のライン補間回路の具体例を示す回
路図、第３図はこの考案の他の実施例を示す回路
図、第４図はテレビジヨン信号のインターレース
原理を説明するために示した図、第５図は動画処
理の問題点を説明するために示した説明図、第６
図は補間信号作成例を説明するために示した説明
図である。
１２……１ライン遅延回路、１３……ライン補
間回路、１４……補間信号選択回路、１５……方
式判定回路、１６，１７……フイールドメモリ、
１８……フレーム間判定回路、１９……フイール
ド間判定回路。
FIG. 1 is a circuit diagram showing one embodiment of this invention, FIG. 2 is a circuit diagram showing a specific example of the line interpolation circuit of FIG. 1, and FIG. 3 is a circuit diagram showing another embodiment of this invention. Fig. 4 is a diagram shown to explain the interlacing principle of television signals, Fig. 5 is an explanatory diagram shown to explain problems in video processing, and Fig. 6 is an explanatory diagram shown to explain the problems of video processing.
The figure is an explanatory diagram shown to explain an example of interpolation signal generation. 12...1 line delay circuit, 13...line interpolation circuit, 14...interpolation signal selection circuit, 15...method determination circuit, 16, 17...field memory,
18... Inter-frame determination circuit, 19... Inter-field determination circuit.
Claims (1)
入力信号と１ライン遅延信号とによる上下のライ
ンの垂直方向画素間および斜め方向の画素間の相
関判定を行い、相関性が最も強い画素を用いて前
記ライン補間信号を得るライン補間回路と、 前記入力信号と１フレーム遅延信号とにより、
静止画と動画との判定出力を得るフレーム間判定
回路と、 このフレーム間判定回路から、静止画判定出力
と動画判定出力とに応じて、前記入力信号の１フ
イールド遅延出力と、前記ライン補間回路からの
ライン補間信号の混合比が制御され、その出力を
補間信号とする補間信号選択回路と、 前記入力信号が標準方式であるか否かの判定出
力を得る方式判定手段と、 この方式判定手段から前記入力信号が非標準方
式であるとの判定出力が得られたときに前記補間
信号選択回路の選択状態を強制的に前記ライン補
間回路の出力信号選択状態に切換える手段とを具
備したことを特徴とする補間信号処理回路。[Claims for Utility Model Registration] In order to obtain a line interpolation signal between scanning lines,
a line interpolation circuit that determines the correlation between vertical pixels and diagonal pixels of the upper and lower lines based on the input signal and the one-line delayed signal, and obtains the line interpolation signal using the pixel with the strongest correlation; With the input signal and 1 frame delayed signal,
an inter-frame determination circuit that obtains a determination output between a still image and a moving image; and a 1-field delay output of the input signal from the inter-frame determination circuit according to the still image determination output and the video determination output, and the line interpolation circuit. an interpolation signal selection circuit in which the mixing ratio of the line interpolation signal from the input signal is controlled and whose output is used as an interpolation signal; a method determining means for obtaining a determination output as to whether the input signal is a standard method; and the method determining means. means for forcibly switching the selection state of the interpolation signal selection circuit to the output signal selection state of the line interpolation circuit when a determination output that the input signal is of a non-standard method is obtained from the method. Features an interpolation signal processing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8533789U JPH0324788U (en) | 1989-07-20 | 1989-07-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8533789U JPH0324788U (en) | 1989-07-20 | 1989-07-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0324788U true JPH0324788U (en) | 1991-03-14 |
Family
ID=31634427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8533789U Pending JPH0324788U (en) | 1989-07-20 | 1989-07-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0324788U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08303095A (en) * | 1995-05-11 | 1996-11-19 | Kyowa Steel Kk | Door stop tool for biparting door |
| JP2002354430A (en) * | 2001-05-30 | 2002-12-06 | Mitsubishi Electric Corp | Scanning line converting apparatus |
-
1989
- 1989-07-20 JP JP8533789U patent/JPH0324788U/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08303095A (en) * | 1995-05-11 | 1996-11-19 | Kyowa Steel Kk | Door stop tool for biparting door |
| JP2764380B2 (en) * | 1995-05-11 | 1998-06-11 | 協和スチール有限会社 | Tilt stopper for double door |
| JP2002354430A (en) * | 2001-05-30 | 2002-12-06 | Mitsubishi Electric Corp | Scanning line converting apparatus |
| JP4656759B2 (en) * | 2001-05-30 | 2011-03-23 | 三菱電機株式会社 | Scanning line converter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2732650B2 (en) | Vertical edge detection circuit | |
| US4745458A (en) | Television signal processing system | |
| US5065243A (en) | Multi-screen high-definition television receiver | |
| CA2018880A1 (en) | Scanning line number converting device for video signal, and down-converter and picture-in-picture tv receiver using the same | |
| JPH0320115B2 (en) | ||
| JPH0324788U (en) | ||
| EP0766457A3 (en) | Improved scanning circuit structure of a television receiver | |
| JPS6132681A (en) | Signal processing circuit | |
| JP2748496B2 (en) | High Definition Television Display | |
| KR950002387A (en) | High definition video format conversion device and method | |
| JP2514221B2 (en) | Television receiver | |
| JPH0330586A (en) | Motion detection circuit | |
| JP2784806B2 (en) | Motion area detection circuit | |
| JP2924199B2 (en) | Television receiver | |
| JPH03179890A (en) | Television receiver | |
| CA1165864A (en) | Variable aspect ratio televison receiver | |
| JP2574296B2 (en) | Television signal processor | |
| JPS6185965U (en) | ||
| JPH07135620A (en) | Second generation edtv signal decoder | |
| JPH0298574U (en) | ||
| JPH0328886U (en) | ||
| JPH04270581A (en) | Muse/ntsc converter and ntsc receiver | |
| JPH04227195A (en) | Television receiver | |
| JPH0822056B2 (en) | MUSE decoder | |
| JPH04326885A (en) | Television receiver |