JPH0324704B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic diagram processing device for inputting logic diagrams into a computer.

Conventionally, this type of equipment uses a digitizer.
Or a tablet was used.
Figure 1 is a block diagram showing a conventional device using a tablet. In the figure, 1 is an input device such as a keyboard, and 2 is a central processing unit (hereinafter referred to as
3 is the main memory (hereinafter referred to as MMU)
4 is an auxiliary memory. The auxiliary memory is, for example, a nonvolatile storage device such as a magnetic disk, and all necessary programs and data are stored in the auxiliary memory 4, and are input from the auxiliary memory 4 to the MMU 3 when necessary. 5 is an output device, such as a printer or an X-Y plotter. A display device 6 uses a graphic display or the like to display figures resulting from the processing. Reference numeral 7 denotes an operation unit that provides positional information on the input screen using a stylus, a cursor, or the like. 8 is a control section, 9 is a coding section, and 10 is a tablet section.

In order to input information regarding a desired logic diagram using the device shown in FIG. 1 and store it in the MMU 3 or the auxiliary memory 4 via the MMU 3, the desired logic diagram is drawn in a predetermined format on a predetermined lined sheet of paper. An original drawing (not shown in Figure 1) is prepared, and basic logic circuits that are the same as the basic logic circuits drawn at those positions are prepared in the order of the positions on the drawing indicated by the borders of the original drawing. The position on the tablet section 10 where is drawn is specified using the stylus of the operation section 7. Then, MMU3 representing the position on the drawing of the original drawing
The symbol code representing the basic logic circuit of that part is sent to the address position of the control unit 8, the coding unit 9, and the CPU 2.
stored via. The symbol code of the basic logic circuit drawn at each position on the tablet unit 10 is configured to be read out when the stylus of the operation unit 7 specifies the position. is relatively simple.

In addition, in order to reproduce and output the logic diagram of the original drawing from the array of symbol codes stored in the MMU 3 to the output device 5, display device 6, etc., drawing information corresponding to each symbol code must be stored. No. The drawing information is stored in advance in the auxiliary memory 4 as a drawing information table, and a correspondence table indicating at which address in the drawing information table the drawing information corresponding to each symbol code is stored is also stored in the auxiliary memory 4. is stored in

By inputting predetermined signals from the keyboard of the input device 1 to the CPU 2, the symbol code array temporarily stored in the MMU 3 can be transferred to the auxiliary memory 4, or read from the auxiliary memory 4 to correspond to the original drawing. The logical diagram is displayed on the X-Y plotter of the output device 5 or the display device 6.

Next, when using a digitizer instead of a tablet, place the original drawing in a position corresponding to the tablet section 10 in FIG. trace. Then, a video signal representing the logic diagram is input to the encoding section 9. The encoding unit 9 performs pattern recognition processing on the input video signal according to a predetermined program, and through this processing determines the symbol code corresponding to the basic logic circuit of each part constituting the logic diagram of the original drawing. The symbol code representing the basic logic circuit of that part is stored in the address position of the MMU 3 representing the upper position, and the subsequent operation is the same as when using a tablet.

As explained above, with conventional devices, whether using a tablet or a digitizer, the operator must manually specify the position or trace the position, and this manual work is complicated and However, the disadvantages are that errors are easy to occur and the equipment is expensive.

In order to eliminate such drawbacks, the
Publication No. 105566 describes an example in which an image of a capacitor and a number indicating its value are input using an ITV imaging device, and the image is recognized. At this time, the figure and numbers are coded into a pattern that is normalized by a computer, so that the image can be displayed superimposed on the input image (corresponding to the original image). However, even with this, processing efficiency could not be greatly improved.

The present invention was made to eliminate the above-mentioned drawbacks of conventional devices, and an object of the present invention is to provide a logic diagram processing device that can automatically perform logic diagram input operations.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention, in which the same symbols as in FIG. 1 indicate the same or corresponding parts, 20 is a drawing setting device, 21 is a television camera (hereinafter abbreviated as TV camera), 22 is a video signal amplifier, 23 is an analog-to-digital converter (hereinafter abbreviated as ADC), 24 is a basic logic diagram table, 25 is a data buffer memory, and 26 is a
A program for pattern recognition is stored in ROM (read-only memory).

FIG. 3 shows an example of an original drawing of a logic diagram to be input into the apparatus of the present invention, in which connections of an AND gate 31, an OR gate 32, a NOT gate 33 are drawn, and connection node numbers N ₁ , N ₂ , N ₃ indicating connection information thereof. etc. are added as shown in the figure.

The original drawing shown in FIG. 3 is set in the drawing setting device 20, the screen is horizontally scanned and vertically scanned by the TV camera 21, the optical information shown by the pixels of the screen is converted into an electrical signal, and the ADC 23 converts the optical information into a digital code (for example, In this case, 1 pixel represents black and white.
(represented by a binary signal of bits), and convert it into
After performing pattern recognition processing using the program stored in the ROM 26, the data buffer memory 25
Temporarily stored in .

FIG. 4 is a format diagram showing an example of the contents of the data buffer memory 25, where 40 is an address column;
41 is a symbol code field, 42 is a terminal number field, and 43 is a connection node number field. Figure 3 is TV camera 21
If the contents of the _buffer memory ₂₅ become as shown in FIG _. 4 after being converted into a video signal by This is the address where location information data is stored. Similarly, Y ₂ Y ₂ Y ₂ is an address for storing position information of the AND gate 31 on the original drawing. Also, symbol code b ₂₁ b ₂₂ …b _2o
is the symbol code representing OR gate 32, a ₂₁ a ₂₂ ...
a _2o is a symbol code representing the AND gate 31.

FIG. 5 is a format diagram showing an example of the contents of the basic logic diagram table 24, where 50 is the address of this table, 51 is the symbol code stored at the corresponding address, and 52 is the number of terminals corresponding to the symbol code. Terminal column 53 is a drawing information table address column that stores the address where drawing information of the basic logic diagram corresponding to the symbol code is stored. For example, the information on the OR gate corresponding to the OR gate 32 shown in FIG.
You can see that it is stored at the address location X ₁₀ X ₁₀ X ₁₀ .

As shown in FIG. 5, the basic logic diagram table 24 has a symbol code 51 arbitrarily determined for each basic logic diagram within the conditions that can specify the basic logic diagram, and a drawing information table for drawing the basic logic diagram. An address 50 for storing the stored drawing information table address 53 together with the symbol code 51 can be determined and created. To test the operation of the pattern recognition process, it is sufficient to set a basic logic diagram in the drawing setting device 20, perform the pattern recognition process, and check whether a symbol code for the basic logic diagram can be obtained. The fact that the drawing information corresponding to the symbol code is stored in the drawing information table address is the same as that explained with reference to FIG.

Data buffer memory 25 as shown in Fig. 4
To store the contents in the auxiliary memory 4, data processing is further performed, and instead of the symbol code field 41, the drawing information table address where drawing information for drawing the basic logic diagram represented by the symbol code is stored is stored. All you have to do is configure the column to do so. This data processing also follows the program stored in the ROM26.
Executed by CPU2. In other words, using the example of Figures 4 and 5, the Figure 4 address
When the basic logic diagram table 24 is searched using the symbol code b ₂₁ b ₂₂ ...b _2o of Y ₁ Y ₁ Y ₁ , it is found that the corresponding drawing information table address is Z ₁₀ Z ₁₀ Z ₁₀ , and the symbol code b in FIG. ₂₁ b ₂₂ …replace b _2o with Z ₁₀ Z ₁₀ Z ₁₀ ,
The symbol code a ₂₁ a ₂₂ ...a _2o of Y ₂ Y ₂ Y ₂ is replaced with the corresponding drawing information table address Z ₂ Z ₂ Z ₂ , and the table after such replacement processing is stored in the auxiliary memory 4. .

In order to display the logic diagram information stored in the auxiliary memory 4 in the form of a logic diagram on the output device 5 or display device 6, a signal instructing the output of the diagram from the input device 1 is input to the CPU 2, and the information is stored in the ROM 26. Start the program that has been installed and save the auxiliary memory 4
Read out the information stored in and draw a diagram. For example, at the position on the display screen of the display device 6 indicated by _the address Y _{1 Y 1} Y ₁ , the OR gate ₃₂ is
is drawn, but at that time, as shown in Figure 4, the connected node numbers are I ₁ and N ₁ for input, and N ₂ for output.
Next, the AND gate 31 is drawn at the position indicated by the address Y ₂ Y ₂ Y ₂ according to the drawing information stored in the drawing information table address Z ₂ Z ₂ Z ₂ , but its connection node number has an output of N ₁ and the input of or gate 32
Since it is the same as _N1 , wiring is drawn so that both terminals are connected, and the logic diagram shown in FIG. 3 is displayed on the display device 6 through similar processing.

The following describes a case where a desired logic diagram is stored in the auxiliary memory 4 in the form of a code and displayed on the display device 6 or the like at a necessary time in the form of the original logic diagram. It is also easy to simulate the operation of the corresponding logic circuit by using the memory as shown. That is, since the operation of the basic logic circuit corresponding to each symbol code 41 in FIG. 4 is fixed, for example, if the logic of connection node numbers 43I ₁ , I ₂ , I ₃ is determined, the logic of N ₃ is determined. That is, the logic and symbolic code of I ₂ , I ₃ a ₂₁ a ₂₂ ...
The logic of N ₁ is determined by a _2o , and the logic of N 2 is determined by the logic of I ₁ , N ₁ and the symbol code b ₂₁ b ₂₂ ... _{b 2o} ,
The logic of N ₃ is determined by the logic of N ₂ and the symbol code c ₁₁ c ₁₂ ...c _1o .

Furthermore, in the basic logic diagram table 24 with the contents shown in FIG. 5, each symbol code may be established arbitrarily as long as it does not cause confusion with other symbol codes, but the relationship with the pattern recognition program is maintained. ,
Regarding various drawings representing various basic logic circuits,
The signal obtained by scanning the drawing with an imaging device must be subjected to pattern recognition processing using a predetermined program, and the result must be established so that a symbol code representing the basic logic circuit can be determined. Therefore, the standard part of the basic logic diagram table 24 is stored in advance in the auxiliary memory 4 together with the corresponding pattern recognition program, and only changed or added data can be input from the input device 1 via the CPU 2. can.

In the above explanation, the basic logic diagram table 24, data buffer memory 25, and ROM 26 have been explained as separate memories, but different address areas in a single memory are 24, 25, 25,
It may be used as 26 areas.

As described above, since the basic logic diagram table and data buffer memory, which are unique to the processing configuration of the present invention, are used, the present invention inputs a logic diagram and clearly expresses each node connection and input/output relationship. In addition to simply processing logic circuit diagrams, it is possible to generate a format directly connected to a logic simulator in the data buffer memory (Figure 4 of the specification) using a method different from conventional methods, greatly increasing processing efficiency. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional device, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is an original drawing showing an example of a logic diagram to be input, and FIG. 4 is a block diagram showing an example of a logic diagram to be input. FIG. 5 is a format diagram showing an example of the contents of the basic logic diagram table of FIG. 2. FIG. 1... Input device, 2... CPU, 4... Auxiliary memory, 5... Output device, 6... Display device, 20...
...Drawing setting device, 21...TV camera, 24...
...Basic logic diagram table, 25...Data buffer memory, 26...ROM. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1 Basics registered in a storage means by associating symbol codes representing various basic logic circuits with drawing information table addresses storing drawing information for drawing the basic logic circuits. A logic diagram is configured using a logic diagram table and at least one type of basic logic circuit of the various basic logic circuits described above, and a logic diagram in which connection information written in text information is attached to this configuration is scanned with an imaging device. means for performing pattern recognition processing on the obtained signal using a predetermined program to determine the position of each basic logic circuit on the logic diagram, the symbol code representing the basic logic circuit, and the connection relationship; A data buffer memory that temporarily stores the symbol code, information representing the corresponding position on the logic diagram, and related connection information, and the above basic logic diagram table is created using each symbol code stored in this data buffer memory. means for searching and determining the correspondence between the information representing the position on the logic diagram corresponding to each symbol code and each drawing information table address, and outputting the logic diagram based on the information representing the position, the connection information, and the drawing information. A logic diagram processing device comprising means for directly outputting connection information and symbol codes stored in a data buffer memory to a logic simulator.