JPH03246781A - Feature vectoring circuit - Google Patents

Abstract

PURPOSE:To increase the processing speed by performing the arithmetic processing for generation of a feature vector by a specific circuit constitution. CONSTITUTION:At least line element information with one dot as the unit of a character pattern is applied to and stored in a first storage means 1, and a second address generating means 4 generates the address to read out line element information stored in the first data storage means 1 and the address to read out weight data corresponding to this line element information from a second storage means 2. Outputted weight data is applied to accumulating means 5-1 to 5-n, and they are provided correspondingly to line element directions, and a decoding means 6 decodes line element information and enables accumulating means 5-1 to 5-n by the output result to accumulate weight information of directions. Thus, a feature vector is quickly obtained when line element data is obtained correspondingly to dots.

Description

[Detailed Description of the Invention] [Summary] Regarding a feature vectorization circuit in a recognition device that recognizes patterns using feature vectors, the present invention relates to a feature vectorization circuit that quickly obtains feature vectors even when obtaining line element data corresponding to dots, for example. A first data storage means for adding line element information in at least a dot unit of a character pattern and storing the line element information; and a first data storage means for storing the line element information in the first data storage means. a first address generation means for generating an address indicating a position; a second data storage means for storing weight data of the line element information; and an address for reading out the line element information stored in the first data storage means. and an address for reading out the weight data corresponding to the line element information read at the address from the second data storage means, and a weight output from the second data storage means. Data is added to decode the line element information stored in the number accumulating means provided corresponding to the direction of the line element and the first data storage means, and enable the accumulating means with the decoding result. and decoding means for accumulating weight information for each direction.

[Industrial application field]

The present invention relates to a recognition device for character patterns, and more particularly to a feature vectorization circuit in a recognition device that recognizes patterns using feature vectors.

[Background Art] With the development of computer systems, reading devices have been put into practical use that capture image data, cut out characters from the captured image data, and recognize each character of the read document. This reading device divides the dot data read by an image scanner or the like into predetermined area units, and compares the characters within the divisions (the characters in the squares) with the predetermined character data to find the first image. The distorted characters are output as a result. This predetermined character data is generally stored in a dictionary memory, and the dictionary memory stores, for example, data characterizing each prescribed character. When a character to be recognized is input, the input character is characterized in the same way, and the distance from the previously determined characteristic data stored in the dictionary memory is determined. The smallest character from this determined distance is output as the recognition result.

In the recognition of characters, etc. in the conventional computer system described above, feature vectors are used to characterize the characterized data stored in the dictionary memory and also to characterize the input characters (image data). This feature vector, for example, determines the direction of line elements that make up a character in units of dots,
Furthermore, it is divided into character area units and the vector directions within each divided area are totaled. This feature vector increases the recognition rate of input characters.

[Problem to be solved by the invention]

The recognition rate is increased using the feature vector described above, but in order to aggregate the directions for each specific area from the obtained line element data, we read out the individual line element data for each area and set a register in advance for each same direction. The number of directions was calculated by incrementing the value of . Furthermore, when weighting is performed depending on the position within the area, processing such as adding the weighted value to a register corresponding to the direction read out in units of one dot is performed. All of these processes involve processing individual data representing line elements, for example, when line elements are determined in units of dots, the data is processed in units of dots.

Therefore, there is a problem in that it takes a lot of time to obtain this feature vector.

Furthermore, in order to increase the recognition rate, the resolution when reading characters is increased and recognition is now performed from a larger number of dots than before.

For this reason, when one character is read out, there is a large amount of dot information, which causes a problem in that it takes even more time to obtain the aforementioned feature vectors.

SUMMARY OF THE INVENTION An object of the present invention is to provide a feature vectorization circuit that quickly obtains feature vectors even when line element data is obtained in correspondence with dots, for example.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

The first storage means 1 stores the line element information in addition to at least dot unit line element information of the character pattern. This line element information is, for example, information indicating in which direction the line element is connected to the dot.

The first address generation means 2 generates an address indicating the storage position of the line element information in the first data storage means 1.

The second data storage means 3 stores weight data of the line element information. For example, this weight data is a weight based on the position of the dot of each line element.

A second address generating means 4 generates an address for reading line element information stored in the first data storage means 1 and the weight data corresponding to the line element information read at this address from the second storage means 2. Generates the read address.

The accumulating means 5-1 to 5-n add the weight data output from the second data storage 3, and are provided corresponding to the direction of the line element.

The decoding means 6 decodes the line element information stored in the first storage means 1, and uses the output result to enable the accumulation means 5-1 to 5-n to accumulate weight information for the direction. Calculate.

[For production]

For example, the line segmentation information within the area of one character is stored in the first storage means 1 at an address position designated by the first generation means 2 in units of dots or in a plurality of dots.

In order to obtain a feature vector within the specific area from the stored data, the second address generating means 4 first adds an address that indicates a dot existing within the specific area to the data storage means 1, and then generates the first data. The storage means 1 adds the data specified at the address, that is, the line element data, to the decoding means 6.

Corresponding to the address position added to the first data storage means 1, the second address means 4 adds the address of the corresponding position to the second weight data storage means 3 which stores weight information in that area. The weight data output from the second data storage means 3 is applied to the accumulating means 5-1 to 5-n. The accumulating means 5-1 to 5-n are provided corresponding to the direction of the line elements, and the decoding means 6 decodes the value corresponding to the storage direction, and the values in the accumulating means 5-1 to 5-n are Indicate one item. According to this instruction, the weighting is accumulated for each direction, and the accumulated values for each direction are obtained in the accumulating means 5-1 to 5-n.

Since each dot is stored in a specific address position so that the address generated by the first address means 2 can be accumulated for each area within each character, the second address generation means 4
When reading out the data, each weighting stored in the second data storage means 3 can be read out in correspondence, thereby speeding up the processing.

〔Example〕

The present invention will be described in detail below using the drawings.

FIG. 2 is a system configuration diagram of an embodiment of the present invention.

Information read by an image scanner or the like is stored in the image memory 10 as image data.

This image memory 10 has a storage capacity for one page read by an image scanner, and stores each dot of read information as binary data of white or black, that is, 0 and 1 data.

The image data stored in the image memory 10 is applied to a noise removal module 11 to remove noise generated during reading. For example, the noise removed by this noise removal module 11 is noise unrelated to character information, etc. For example, a 3 x 3 mask with a black center and 8 dots surrounding the center dot.
The dots are noises such as white, and the noise removal module 11 makes the dots in the center white. Although this noise removal module is provided in the character recognition pre-processing section 12, it is not limited thereto, and may be performed when storing each character in the normalization module 16, which will be described later. It may be performed at the time of line element formation.

The image information from which noise has been removed by the noise removal module 11 is sent to the row histogram module 13, the column histogram module 14, and further to the readout control module 1.
Join 5. The row histogram module 13 is a module that projects the read information, for example, the content of the paper read by the above-mentioned image scanner, in the column direction in units of dots, and calculates the number of dots in the row for each dot unit.

That is, this is a process of determining how many black dots are present in each one-dot row (horizontal direction) for each one-dot row. Also, the column histogram 14 is a process of projecting in the column direction in the same way as the row histogram described above, and calculating the number of projected black dots.

The row histogram module 13 sequentially counts the dots in the field from the data that is sequentially read out from the image memory IO in the row direction in units of dots and added via the noise removal module 11 (dot readout similar to raster scanning). (1 dot line). Then, the number of black dots is sequentially calculated for each line. The number of black dots becomes the row histogram corresponding to each row. Also, the column histogram 14 is 1
Each dot has a counter corresponding to the number of dots in the dot row, and each time the dots in one row are different, the counter corresponding to the black dot is incremented. By performing the above-described operations for one page, the row histogram module 16 and the column histogram module 14 produce so-called row histograms representing the number of dots for each row position and column position.

A column histogram is required. The result is then applied to the read control module 15.

The readout control module 15 sequentially obtains row positions and column positions from these row histograms and column histograms. For example, this position can be obtained by the period of the row histogram or the period of the column histogram.

The read control module 15 determines the row and column positions, but also performs the following processing. Image data, for example, information read from an image scanner, may have a tilt depending on the position of the paper and the like.

For this reason, the readout control module 15 sequentially changes the angle at which the histogram is obtained so that the column histogram and the row histogram take the maximum value, and obtains a correction angle.

Then, input the image information added from the above-mentioned noise removal module 11 again to obtain the final histogram,
From the point where the row histogram obtained by the corrected slope (the histogram takes the maximum value) changes from 0 to positive (possibly positive to 0), one line of data corresponding to the slope is read out for one period. The data is stored in a row buffer provided within the control module 15.

The read control module 15 further obtains the column histogram within the row of one row of data stored in the row buffer, cuts out the data from the position where the column histogram changes from 0 to positive, and outputs it to the normalization module 16. It is also output to the conversion table creation module 17.

This extracted data is data of the I character area.

The conversion table creation module 17 is a module that obtains conversion data for normalizing one character by the normalization module 16. It projects the conversion data in the column direction and the row direction on the one character area cut out by the readout control module 15, and The counters in the column and row directions are incremented dot by dot (row and column) from the column and row where the dot exists, and the values up to the final value '' in the area of one character are determined.

In the normalization module 16, the final value of the dot cut out by this one character in the row direction and column direction and the cut out 1
Based on the size of the character, the character is expanded to cover the entire area within the extraction area. For example, an enlargement process is performed to make an area of 64×64 dots into one character area. If the value of the character in the column direction and row direction is 48 dots (both column and row) in the conversion table creation module 17,
Processing is performed to convert 48-dot characters to 64-dot characters.

In this process, data in a row or column at a specific position is repeated to make the same data and enlarge the characters. Furthermore, in the case of reduction, rows and columns at specific positions are repeatedly read out and ORed together to reduce them as the same row or example.

Normalization module I6 allows one character area, e.g. 64X
After one character has been enlarged within 64 dots, the thinning module 18 performs a process of thinning the character. In this thinning module 18, one dot above, below, left and right of the center dot is
Thinning processing is performed using a mask of 11 dots (3×3), one dot to the left, and two dots above from the center.

By controlling the center dot to be O when the pattern is predetermined by the mask described above, thinning of the area around one dot forming a character can be achieved in one process. By sequentially repeating thinning of this mask, it is possible to achieve a one-dot line.

For example, 64×6 obtained by the thinning module 18
The 4-dot thinned character is added to the line segmentation module 19 and converted into line segments. This line segmentation module calculates the sum of black dots that exist in the vertical direction from the target dot, that is, the center dot, when they exist in the horizontal direction, when they exist in the upper right and lower left, and when they exist in the upper left and lower right. Each dot is represented by four types of line elements. If the line element belongs to more than one of the above four types, priority is given in the order of, for example, the vertical direction, then the horizontal direction, etc., and in which direction the line element exists is determined for each dot.

Note that if the center is 0 dot, that is, white, it is assumed that no line exists.

In the line segmentation module 19, there are four directions: up and down, left and right, diagonally upward to the right, diagonally upward to the left, and five types, including the case where there is no line element, so the state is expressed as a 3-bit value for each dot. , a total of 3×64×64 information and added to the feature vector module 20.

In the feature vector module 20, the line segmentation information obtained by the line segmentation module 19 described above is divided into 8-dot units in the left, right, top, and bottom, respectively, and the divided areas are divided into one area each in the downward and right directions (2× 2 areas) with a total of 16 dots as one vector module area, and count how many line elements exist in four directions: up and down, left and right, upper right, and upper left. do. A feature vector is calculated using a 16x16 dot area as one vector module area, but since this one vector module area is moved in units of 8 dots, there are 7 areas in each of the row and column directions, resulting in a total of 7 x 7 feature vectors. This is the area of

In the feature vectorization module 20, the number of directions is calculated for each area type as described above, but when calculating this number, weighting is applied to each area, with the center being higher and the surrounding areas being lower as they go outward. ing. For example, each dot in the 4 x 4 area centered on the center is given a weight of 4, each of the two dots around it is given a weight of 3, each of the two dots around it is given a weight of 2, and then the two dots around it are given a weight of 4. Each dot is set to 1, weighting is performed, and a feature vector is determined.

This feature vector has specific characters to be recognized all made the same size by the normalization module 16, so
If they are the same character, they have almost the same feature vector,
The feature vectors differ for each character. However, since there are very similar modules, in the embodiment of the present invention, in order to speed up the calculation process and improve the recognition rate, a standard pattern of feature vectors is used for each feature vectorization region, i.e. Classification is performed within each square, and L class (for example, L = 20) is divided within each square.
) and the unknown input. That is, the distance between the feature vector in each square of the standard pattern and the feature vector in the square obtained by the special notice vector module 20 is determined for each square. Each of the squares is divided into classes (class 1 to class 2), and the distance ranking of the classes within each square is determined in descending order of distance to the fifth class.

The distance calculation module 21 stores this distance in the class dictionary 23-
1 (standard patterns are stored in class units). Note that when searching for individual candidate characters, the candidate dictionary 23-2 is used (at this time, the switch SW selects the candidate dictionary 23-2).

The top selection and score allocation module 22 determines the top five classes mentioned above and determines the score corresponding to each class for each square. That is, the top selection and score assignment module 22 determines the score to be given to each of the first to fifth ranking classes in class units based on the distance obtained from the distance calculation module 21, and calculates the score of each character. For example, if it is the first distance (short distance), 5 points are given, then 4 points, 3, 2.1 points, etc. are given to the class. These are provided corresponding to squares 1 to 49, respectively. The processing results of the top selection score module 22 are added to the comprehensive evaluation module 24.

The comprehensive evaluation module 24 is a module that calculates the degree of matching between an input object, that is, an input character and its candidate, and has three types of operation: an associative matching mode, an exhaustive matching mode, and an individual matching mode.

The associative matching mode is a mode in which the score of a candidate is calculated from the mask corresponding to the candidate stored in the associative dictionary 23-3 and the class to which the candidate belongs.

As shown in Figure 2(b), the associative dictionary has candidates ■D for each mask.
The class ID of the class to which the candidate belongs in the mask is stored, using the address as the address.

This data is obtained by clustering a set of D-dimensional partial vectors corresponding to the mask ID of each candidate according to their (weighted) distances, and only the results are stored in the associative dictionary. At the same time, a class dictionary 23-1 in the distance calculation module is also created correspondingly.

Note that the associative dictionary 23-3 and the class dictionary 23-1 correspond to each other and have the same type. When storing two or more types of dictionaries in one memory, the specification of the dictionary to be used becomes the dictionary reference start position. (Divide this dictionary into candidate IDs,
Comprehensive evaluation can be performed for each in parallel, and if higher speed is required, it can be easily achieved).

The associative dictionary 23-3 is a table in which the class ID: K of the class to which candidate a belongs with mask m is written.
)=, for candidate a (=1 to C), the following is obtained (M=49), where P (m, k) represents the score. The overall evaluation value V (a) for candidate a is obtained using this formula.

The total matching mode and individual matching mode of the comprehensive evaluation module are modes in which calculations are made for each candidate.

Total matching mode is a=1 to C1 Individual matching mode is J=1
~ck, a=b(j), and find the distance expressed by d(m, a). This value V (a) is the (weighted) distance of the feature vector between candidate a and the input object.

The top candidate selection module 25 selects and outputs a plurality of characters, for example, five characters determined from the top in each character correspondence.

The top five characters become the recognition result in the read image data.

All of the operations described above are performed by pipeline processing. That is, data for one page, for example, in the image memory 10 that stores image data is read out by pipeline processing, divided into lines by the control module 15, and outputted to the normalization module 16 in units of characters.

The character wheel is subjected to the aforementioned thinning, line segmentation, feature vectorization, and recognition processing.

The top selection module 25 is a module that ranks candidates based on the overall evaluation value and selects the top five candidates.
If the input is in associative exhaustive matching mode ((a', V
(a) l a', a = 1~c modified) If it is in the individual integer unit mode ((j, v(a) lj = 1~ck, a =
b (j)) (Comprehensive evaluation output of individual matching) Descending/ascending order: (Character association dyad order, Others: Smallest order). Further, the output is the candidate IDs (or input order) arranged in the order of the manually sorted results and their comprehensive evaluation values.

In the embodiments of the present invention described above, a pattern recognition device using the feature vectorization circuit in the embodiments of the present invention has been described. Below, the feature vectorization circuit in the pattern recognition device will be explained in more detail.

3 is a detailed circuit configuration diagram of an embodiment of the present invention.

One character pattern cut out is processed by the thinning module 18
The character is converted into a character with a thickness of one dot, and the line segmentation module 19 determines in which direction (line element) the thin line continues for each dot. The data (line elementization data) obtained by this line elementization module 19 is added to the data buffer 31. For example, the data buffer 31 is a FIFO capable of storing line segmentation data in units of one character. The data stored in the data buffer 31 is then read out in units of 16 bits and added to the data exchange memory 32.

On the other hand, in response to reading from a CPU (not shown) or the like, clock pulses are sequentially applied to the sequence counter 33, and the sequence counter 33 sequentially counts the pulses. This clock pulse generates one pulse for one reading from the data buffer 31. That is, the sequence counter sequentially increments its count value in response to data reading.

The count value of the sequence counter 10 is the address generation R.
Join OM. The address generation ROM 34 stores the location to be stored in the data exchange memory 32. The count value of the sequence counter 33 has a one-to-one correspondence with the address position read from the data buffer 31. For example, when the sequence counter 33 is "1", the data ■, ■, ■, ■ as shown in FIG. instruct.

In the embodiment of the present invention shown in FIG. 3, data (line element data) is read out with a width of 16 bits. The line segmentation data includes information such as 4 directions for 1 dot and the fact that line elements do not exist or even cross each other, and the direction of 1 dot is
It is expressed in bits. In order to improve readout efficiency, one dot is made up of 4 bits, and the line segmentation information of 4 dots is added to the data exchange memory 32 by one readout.

The data buffer 31 has a FIFO structure, and the first input data FIFO-DATAI (■ to ■) is added to the data exchange memory 32.

At this time, the address generation ROM 34 outputs "0000", that is, "0", and the exchange memory 32 outputs the address "0".
The data FIFO-DATAI is stored in "000". Next, FIFO-DATA2 is added, but although the sequence counter 33 is 0001, the address generation RO
0001 in M34 stores 64 (decimal), and this value is added to the input address of the data exchange memory 32, so FIFO-DATA2 (data ■, ■, ■,
) is stored at address 64. The address generation ROM 34 adds addresses to the data exchange memory 32 so as to sequentially store data in units of 64 addresses. And the 17th data, data F I FO
-DATA1,7 is added, at this time the address becomes "1" and the data conversion memory 32 stores data FIFO-DATA17 at address 1. Next, FI FO-DATA 8 is stored at address 65, following the 16 pieces of data stored in the optical system in sequence.

In the embodiment of the present invention, the area for one character is 64 dots×
It is an area of 64 dots and is added to the data buffer 31 in parallel, so it is a unit of 4 dots.

In other words, the data buffer 31 is a 1024-stage FIFO.
A total of 4096 dots (64 dots x 64 dots) are stored in units of 4 dots. The data FIFO-DATA1 to 1024 stored in this data buffer 31
(Each data is 16 bits) is sequentially stored in units of 64 addresses by the operation described above, as shown in FIG. As is clear from the relationship between converted image data and memory addresses shown in FIG. 6, four dots are simultaneously added to the line element data in units of four dots in the vertical direction. Therefore, if four dots of line element data in the vertical direction are added as shown in FIG. 6, addresses 0 to 63 will be in the horizontal direction. That is, in the horizontal direction, there are addresses for a total of 64 dots from O to 63, and in the vertical direction, 4 dots are read out in common, resulting in 16 addresses.

By the above-described operation, data of, for example, four dots in the vertical direction are sequentially stored in the data exchange memory 32 at 64 addresses apart, as shown in FIG.

After this storage operation is completed, the sequence counter 35 starts counting, and the weighting is sequentially added to the table 38 via the address generation R0M 36 and the Hanwha 37. Although not shown, the sequence counter is a circuit that starts a counting operation in response to an instruction from the CPU. By adding the incrementing data of the sequence counter 35 to the address of the address generation ROM 36, the address generation ROM 36 counts in units of squares (16 x 16). Generates the address to be accessed. FIG. 7 is a diagram of generated addresses for square 1. In this case, the square I is 0-15.61-79.
12B-143, 192207, and when the sequence count is 00, "OII" is 1, "1"...15
At 0:00, it is "64". At 17, it is "65". At 32, it is "128". At 33, it is "129"...4
8, "192°, 49", etc. are generated respectively. The data generated in the address generation ROM 36 is added to the output address of the data exchange memory 32, and after the change in FIG. From 0 in the image data and memory address relationship diagram, 0-16 in the horizontal direction, 0, 64, 128.1 in the vertical direction
A total of 64 addresses, 92, are output by the data exchange memory 32. The data output to this data exchange memory is temporarily captured in a flip-flop (latch) 39 for timing adjustment, and then sent to decoders 40-1 to 40-4.
0-4. is added in units of 4 bits, that is, in units of dots.

Decoders 40-1 to 40-4 decode data in vector directions (0°, 90', 45° and 135°) for each dot, and output an H level signal when components in each direction are present. Each decoder 40-1~
The output of decode 0@ of 40-4 is AND gate 41-1
~Join 43-1. Similarly, 90°, 45°, and 135@ are added to the corresponding AND gates.

In the embodiment of the present invention, vectors are weighted for each square within one character area, and the AND gate whose gate is turned on by the decoded value described above is weighted by timing adjustment from the table RAM 38. 4 through flip-flops (latches) 45 for each
Bit data is added. In the embodiment of the present invention, 1
Since weighting is set in units of 2 dots out of the 16 dots in a square, the weighting RAM table is 8 bits, and the data of each 2 dot is corresponded to the values of the adjacent corresponding dots. In addition to the and gate. For example, corresponding to Oo, the AND gate 44-1 and the AND gate 43-1 are adjacent dots in dot units, and the AND gate 42-1
Since the dots 41-1 and 41-1 are adjacent dots, the upper 4 bits and the lower 4 bits are used to create a combination of AND gates. anime game) 41-
The outputs of 1 to 44-1 are applied to accumulation circuits 46-1 to 49-1.

In the embodiment of the present invention, weighted feature vectors are obtained corresponding to 90°, 45°, and 135°, so AND gates are similarly set up in the accumulator circuits (46-2 to 49-49). 2゜46-3~49-3.46-
4 to 49-4) respectively.

Below, Oo will be explained in detail since it is the same for Oo, 90°, 45°, and 135° as described above. When the decoders 40-1 to 40-4 determine that it is 0°, the corresponding AND gate is turned on.
For weighting, 4-bit data output from the table RAM is output to the accumulator circuit. By adding this data, the accumulation circuits 46-1 to 49-1 accumulate the values.

When all operations of mask 1 are completed, the CPU (not shown)
Accumulator circuits 46-1 to 48-1 sequentially add data to accumulator circuit 49-1 according to the instructions in between. Thereby, the accumulation circuit 49-1 obtains a weighted feature vector for the zero degree direction.

The above-mentioned weighting is stored in the table RAM 38 in units of 4 dots (2×2). For example, if this data is vertical dot data, it will be common in units of dots, and as mentioned above, the 4-bit value will be is the AND gate 44-1.43-1, and the other data is 42
-1.41-1. On the other hand, since the two dots arranged horizontally are common, the data output from the table RAM 38 is weighted by the sequence counter 35 and has the same address for the two dots in the horizontal direction as shown in FIG. Therefore, the values are the same. To express this in more detail, the sequence counter sequentially increments and generates an address R.
For the 12-bit data added to OM, the lower 6 bits excluding ILSB are output. As a result, when the sequence counter is O to 1, address 0 is added to the weighting table RAM 38 for 2 dots, and then addresses 1, 2, 3, and the same address are specified for the 2 dots. The same weight data is output. This results in 2
Each time a dot is read out, it is decoded by a decoder and the gate of the accumulator circuit is controlled, but the weight for two dots does not change, and weighting can be done in units of squares of 2 × 2 dots for a total of 16 dots. Also, weighted accumulation can be performed.

By operating as described above, 16
The data of X16 dots can be called up, and the corresponding weighting table is also sequentially (see FIG. 8), so that the data changes every two dots in correspondence with the dots. Note that the address generation ROM 36 has a 12-bit address and a 10-bit output, so it can generate an address for each square, and this address generation ROM 36 and weighting correspond to the table RAM 38. By doing this, it is possible to obtain the feature vector for each square.

FIG. 9 is a diagram of generated addresses in square 2, and FIG. 10 is a table address diagram with weighting corresponding to square 2, and the weighting can be sequentially changed for the squares.

In the embodiment of the present invention, the output of the data buffer 31 is connected to the buffer 51 connected to the CPU bus, so that it is possible to monitor the stored data. For example, this buffer 51 may also be used in the sequence counter 35.
Since these are connected, the sequence counter can be initialized under the control of the CPU.

On the other hand, for weighting, buffers 52 and 53 are provided at the address input and data terminals of the table RAM 38, respectively. For example, if dictionary data for feature vectors has different weightings, it is necessary to weight the dictionaries accordingly. The weighted data is stored through the CPU
This can be done by That is, the contents of the table RAM 38 can be arbitrarily changed depending on the purpose.

On the other hand, data buffer 5 is provided in the accumulation circuits 49-1 to 49-4.
5 and a buffer 54 are connected. This buffer allows the data of each cumulative result (0° to 135°) to be transferred to CP.
For example, when performing character-by-character recognition again (confirmation recognition), the buffer 5
The data of the accumulation circuits 49-1 to 49-4 can be read through the accumulation circuits 49-1 to 49-4.

On the other hand, when recognition is performed by each circuit as shown in FIG. can be found.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to prevent the complexity of calculation processing when generating feature vectors, and to perform similar calculations with a simple circuit configuration. Furthermore, even if the amount of processing information in the feature vector generation circuit used in the character recognition algorithm is large as described above, the feature vector generation algorithm can be realized by a simple circuit, making it possible to reduce the size and increase the speed. Further, as described above, it is possible to miniaturize and speed up the recognition apparatus using the character recognition algorithm.

[Brief Description of the Drawings] Figure 1 is a principle block diagram of the present invention, Figure 2 is a system configuration diagram of an embodiment of the invention, and Figure 3 is a detailed circuit diagram of an embodiment of the invention. , FIG. 4 is an explanatory diagram of input data, FIG. 5 is a diagram of data storage arrangement in memory, FIG. 6 is a diagram of the relationship between image data after conversion and memory addresses, and FIG. 7 is a diagram of <Mask No., l > Occurrence address chart,
- FIG. 8 is a corresponding weight table address diagram, FIG. 9 is a generation address diagram of <Mask No., 2>, and FIG. 10 is a corresponding weight table address diagram. DESCRIPTION OF SYMBOLS 1... First data storage means, 2... First address generation means, 3... Second data storage means, 4... Second address generation means, 5... Accumulation Means, ・Decoding means.

Claims (1)

[Scope of Claims] 1) A first data storage means for adding line element information in at least a dot unit of a character pattern and storing the line element information (
1), a first address generating means (2) for generating an address indicating a storage position of the line element information in the first data storage means (1), and storing weight data of the line element information. a second data storage means (3), an address for reading the line element information stored in the first data storage means (1), and a second data storage means for storing the weight data corresponding to the line element information read at the address; Data storage means (
2) a second address generation means (4) which generates an address to be read from the second data storage means; and an accumulation of a number provided corresponding to the direction of the line element by adding the weight data output from the second data storage means. means (5-1 to 5-n); decoding the line element information stored in the first data storage means (1), and using the decoding result to the accumulating means (5-1 to 5-n); A feature vectorization circuit characterized in that it comprises a decoding means (6) for enabling weight information for a direction and accumulating weight information for the direction. 2) The feature vectorization circuit according to claim 1, wherein m sets of the accumulating means (5-1 to 5-n) are provided, and the line element information added in units of m bits is processed in parallel.