JPH0324623A - Loop processing controller - Google Patents

Abstract

PURPOSE:To rapidly process a loop by adding a counter value indicating the number of addresses of executed instructions to the value of a 3rd register for holding the addresses of loop control instructions when a previously set loop condition is formed, and using the added value as the address of an instruction to be successively read out from a control storage circuit. CONSTITUTION:A firmware instruction from the control storage circuit 1 is temporarily stored in a 1st register 2, recoded by a decoder 3 and stored in a 2nd register 4. The formation of a loop condition in an instruction is detected by a detector 5. The counter 8 counts up the number of instructions to be repeatedly executed and inputs an address updating value to an adder 7 and the added value is held in the 3rd register 6. Then, the loop condition, the number of repeats to be executed and operation to be executed are stored in a 4th register 9, and when one of these contents is switched by a selector 11 and applied to the adder 7, the instruction to be read out next in the circuit 1 can be read out even when it is stored in an address other than continuous addresses, so that rapid loop processing can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is utilized for the execution of firmware instructions in a processor controlled by the firmware instructions. The present invention relates to control of firmware instructions in loop processing.

〔overview〕

The present invention provides a loop processing control device for a processor that executes loop processing under the control of firmware instructions, when a preset loop condition is established.
Hold the address of the C loop control instruction (add the value of the counter indicating the number of addresses of executed instructions to the value of the third register and use this as the address of the next instruction to be read from the control storage circuit) This enables high-speed loop processing, allows multiple consecutive firmware instructions to be executed repeatedly, and improves the execution performance of loop processing consisting of conditional branches and multiple arithmetic instructions.

[Conventional technology]

Conventionally, this type of loop processing has been performed by combining at least two firmware instructions.

That is, loop processing is constructed using conditional branch instructions and normal arithmetic or memory access instructions.

[Problem that the invention seeks to solve]

The conventional loop processing described above consists of at least two firmware instructions, and the conditional branch instruction and operation or memory access instruction are separated, so if the number of loops is n, at least 2 x n steps are executed. I needed time.

Amidst the strong desire to improve the processing speed of processors, improving the performance of loop processing is one of the most important themes, and in conventional technology, multiple arithmetic instructions are written for the number of loops, and condition judgment is improved even slightly. Programming techniques existed to eliminate overhead.

However, this method cannot be used when the number of loops is not fixed, and has disadvantages such as poor memory usage efficiency. In most cases, loop processing is achieved by a combination of conditional branch instructions and arithmetic instructions. Ta. In such a case, the execution time required for the original calculation is more than twice as long, which has the disadvantage of hindering performance improvement.

The present invention aims to eliminate such drawbacks and provides an apparatus that can perform loop processing at high speed.

[Means for solving problems]

The present invention includes a control storage circuit that stores firmware instructions, a first register that temporarily holds the firmware instructions output from the control storage circuit, and a decoder that decodes the firmware instructions held in the first register. , a second register that holds the decoding result, a condition detector that detects whether a loop condition in the loop control instruction is satisfied, and a third register that holds the address of the control storage circuit. A loop processing control device comprising: an adder that calculates the address of the control storage circuit and supplies it to the third register; The present invention is characterized by comprising a counter that sequentially outputs an update value of the address to the adder.

A fourth register is provided in the adder via a selector, and this fourth register describes the loop conditions used to control loop processing, the number of instructions to be repeatedly executed, and the operations to be executed when the conditions are met. The address of the loop control instruction can be held according to the number of executed loop instructions.

[Effect]

While the loop condition is satisfied, the address of the control memory circuit is generated by adding the value of the counter representing the number of executed instructions to the value of the register that holds the address of the control memory circuit where the loop control instruction is written. Repeatedly executes multiple consecutive firmware instructions.

By providing a fourth register and switching it with a selector to feed it to the input of the adder, even if the next instruction to be read is stored at an address other than consecutive addresses in the control storage circuit, I can handle it.

This allows high-speed loop processing and allows multiple consecutive firmware instructions to be repeatedly executed. In particular, in the case of a one-step loop instruction, two
Processing can be performed with twice the performance, and similar processing can be performed with fewer steps.

〔Example〕 Next, embodiments of the present invention will be described based on the drawings.

The figure is a block diagram showing the structure of an embodiment of the present invention.

The embodiment of the present invention includes a control memory circuit l for storing firmware instructions, a first register 2 for holding firmware instructions read from the control memory circuit l, and a decoder 3 for decoding the firmware instructions. A second register 4 that holds the decoder result, a condition detector 5 that detects whether the loop condition is satisfied, and a third register 6 that holds the address of the firmware instruction to be read next. an adder 7 for calculating the address of the control storage circuit l; a counter 8 for generating an offset value input to the adder 7; a fourth register 9 for storing the address of the loop control instruction; selector 10,
11.

Next, the operation of the embodiment of the present invention constructed in this manner will be explained.

Normal instructions that are not loop control instructions are read from the control storage circuit 1 and stored in the first register 2. Next, the firmware instruction in the first register 2 is input to the decoder 3, the instruction is decoded, and then input to the second register 4 for execution.

The address of the firmware instruction is read by an adder 7. The third register 6 stores the address of the firmware instruction to be read next. If the loop is not in progress, the output of the third register 6 is selected by the selector 1l and inputted to the adder 7.

The counter 8 always outputs "1", and the adder 7 adds it to generate the address of the firmware instruction to be read out from the control storage circuit 1 next.

When executing a one-step loop using only a loop control instruction, zero is stored in the loop control instruction as the number of instructions to be looped. Loop control instruction is decoder 3
When the loop condition is input, the condition detector 5 checks whether the loop condition is satisfied.

If the conditions are met, the first selector lO selects the output of the decoder 3. While the loop condition is satisfied, the firmware command input to the decoder 3 is input to the decoder 3 again, and at the same time, the firmware command is not read from the control storage circuit 1. With this operation, l
A loop of steps can be realized.

Next, a case will be described in which a step loop is executed after a loop control instruction. In this case, the number n of instructions to be looped is stored in the loop control instruction. When a loop control command is manually input to the decoder 3, the number n of commands to be repeatedly executed is set in the counter 8 as the maximum value of the count. The address of the loop control instruction is held in the fourth register 9. When the condition detector 5 confirms that the loop condition is satisfied, the counter 8 counts up by 1 with l as the initial value.

The adder 7 generates the address of the firmware instruction to be read from the control storage circuit 1 by adding the count value of the counter 8 and the address of the loop control instruction. When the count value exceeds the maximum value n, the count value is reset to zero and the adder 7 generates the address of the loop control command again.

This address generation function sequentially reads n firmware instructions after the loop control instruction from the control storage circuit 1, stores them in the second register 4 via the first register 2 and decoder 3, and executes them. . When the count value is reset to zero, the loop control command is read again from the control storage circuit 1, and the same repeated operation is performed while the loop condition is satisfied.

If the loop condition is not satisfied, the counter 8 outputs a value obtained by adding 1 to the number n of instructions to be repeatedly executed set in the counter 8. Adder 7 generates an address for exiting from loop processing by adding the output of counter 8 and the address of the loop control command.

〔Effect of the invention〕

As explained above, according to the present invention, the number of instructions to be repeatedly executed is written in the loop control instruction, and when the number of repeats is zero, instruction reading from the control storage area is stopped and the instructions are input to the decoder. By inputting the firmware instructions to the decoder again, high-speed loop processing can be performed.

In addition, if the number of repetitions is not zero, add the count value of the counter whose maximum value is the number of repetitions and the address of the loop control instruction, and sequentially execute the instructions that should be repeatedly executed after the loop control instruction. The firmware instructions can be executed repeatedly.

In particular, a one-step loop instruction can perform processing with twice the performance of conventional loop processing of a pair of conditional branch instruction and arithmetic instruction, and it is also possible to perform the same processing with fewer steps than conventional loop processing. There are effects such as being able to.

[Brief explanation of drawings]

The figure is a block diagram showing the structure of an embodiment of the present invention. ■... Control storage circuit, 2, 4, 6, 9... Register, 3... Decoder, 5... Condition detector, 7... Adder, 8... Counter, 10, 1l ···selector.

Claims (1)

[Claims] 1. A control storage circuit that stores firmware instructions; a first register that temporarily holds firmware instructions output from the control storage circuit; a decoder for decoding, a second register for holding the decoding result, a condition detector for detecting whether a loop condition in a loop control instruction is satisfied, and a second register for holding an address of the control storage circuit. a loop processing control device comprising three registers, an adder that calculates the address of the control storage circuit and supplies it to the third register; and an adder that stores the number of instructions to be repeatedly executed and calculates the number of instructions from 1 to the number of this instruction. A loop processing control device comprising: a counter that sequentially outputs numerical values up to and inputs an updated value of an address to the adder.