JPH0324489A - Sonar receiver - Google Patents

Abstract

PURPOSE:To stabilize action of the apparatus by generating a high frequency signal at a specified level with a multiplying D/A converter and further performing a templing at a center frequency of the high frequency signal. CONSTITUTION:A high frequency signal S10 is inputted into a multiplying D/A converter 22 via a BPF 20 to be multiplied by a digital set value. After con trolled in level by a data signal S12 from an ROM 24, the results are amplified to a specified level with an amplification circuit 26 and inputted into a sampling and holding circuit 32 as signal S15. The signal S15 from a clock signal generator 34 from the circuit 32 and then, holding signal S17 is sent out as output signal S25 as cleared of a overlapped high-order component of the signal S17 and unde sired noise components outside an information band with an LPF 38. Therefore, effect of glitch as caused with a gain switching of the converter 22 is blocked and a signal processing of the signal S25 free from restriction by time base thereby assuring a stable action state with a lowering of erroneous recognition of a signal attributed to the reflection of a target.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a sonar receiving device that receives an ultrasonic signal reflected by a target object after transmission and detects an information signal related to detection of the target object. Regarding.

[Conventional technology] An ultrasonic signal is transmitted, an echo signal of the ultrasonic wave reflected from a target object is received by a delivery device, and then signal processing is performed to detect the target object, that is, to generate an information signal related to the target object. In a sonar receiving device that derives the distance, the distance to the target object is determined from the time it takes for the echo signal to return, and the size of the target object is estimated from the level of the echo signal.

In this case, even if the echo signals are related to the same target object, an echo signal from a nearby site has a high level, and an echo signal from a long distance site has a low level. For this reason, it is common practice to correct the level based on distance. Such correction is done by TVG (Time Varied Gain).
) is generally used to control the final signal output to be approximately constant using a gain control circuit or the like.

In this gain control circuit, multiplication (multiplication type) D is used so that the gain can be set accurately with digital values.
A circuit using a /A converter is adopted.

Such a sonar receiving device is shown in FIG.

In FIG. 3, reference numeral 2 is a BPF, and this sonar receiving device further includes a multiplying D/A converter 4, an amplifier circuit 6, a frequency mixer 8, a local oscillator 10, and an LPF.
12, a clock signal generator 14, an address signal generation circuit 16, and a ROM (memory table) 18.

Then, the echo signal is received, and the high frequency signal derived from the receiver etc. is band-limited by the BPF 2, and then input to the multiplication D/A converter 4, where it is multiplied by the analog signal and the digital setting value. A signal for setting a digital value is input from the ROM 18 so that the derived signal has a predetermined level.

The signal is input to a frequency mixer 8 via an amplifier circuit 6 and mixed with a carrier frequency signal generated by a local oscillator 10. Next, the LPF 12 derives an output signal in which only low frequency signal components are extracted.

Here, the memory table 18 for setting the gain of the multiplication D/A converter 4 stores the value of the TVG curve, and is driven by the address signal generation circuit 16.

FIG. 4(a) shows the input waveform of the frequency mixer 8.
The output waveform of L P F 12 is shown in the figure.

The address signal generation circuit 16 updates the address at a period T, and signals of gain setting values are sequentially generated from the ROM 18. As a result, as shown in FIG. 4(b), a glitch occurs immediately after the gain switching, as indicated by the occurrence time t. The generation time t is represented by the settling time of the multiplying D/A converter 4, and is, for example, within Iμsec.

After being frequency converted here, the output waveform derived from L P F 12 is shown in FIG.
．． ), causing undershoot and overshoot waveform distortion (ablation phenomenon).

[Problems to be Solved by the Invention] In the sonar receiving device according to the above-mentioned conventional technology, the glitch that occurs in the multiplying D/A converter is caused by narrowing of the band and time expansion ( ringing effect), and the output waveform is accompanied by long-term distortion. For this reason, it is difficult to perform signal processing that distinguishes between the distorted waveform caused by the glitch and the reflected signal from the target object, resulting in a drawback that misidentification is likely to occur when detecting the target object.

The present invention has been made in view of the above points, and it is possible to effectively prevent the influence of glitches caused by gain switching of a multiplying D/A converter, and to subject the output signal to time axis limitations. It is an object of the present invention to provide a sonar receiving device that can perform processing without problems, reduce misidentification of signals related to reflection from a target object, and obtain a stable operating state.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the sonar receiving device of the present invention has the following features: A sonar receiving device that derives a signal related to target detection includes a multiplier D/A converter that is supplied with a high frequency signal and derives the signal at a predetermined level; a sample hold circuit that samples the output signal of the multiplying D/A converter; and a memory that sends out a control signal for changing a digital setting value related to the gain of the multiplying D/A converter and includes a memory table. and an address generation circuit that sends out an address signal that causes the switching timing of the memory table to be immediately after the sampling.

[Operation] In the sonar receiving device of the present invention configured as described above, the digital setting value related to the gain is set so that the high frequency signal is generated and derived at a predetermined level by the multiplying D/A converter. A control signal for changing the signal is supplied, and the output signal of the multiplication D/A converter is sampled at the center frequency of the high frequency signal.

In this case, the control signal is supplied to the multiplication D/A converter based on an address signal for timing the memory table switching immediately after the sampling.

This prevents glitches that occur based on the gain settings from being introduced into the output signal.

[Embodiment] Next, an embodiment of the sonar receiving device according to the present invention will be described in detail with reference to the accompanying drawings.

Figure 1 shows the overall structure of the embodiment, and Figures 2 (a) to (
b) shows the signal processing waveform.

In FIG. 1, a high frequency signal S1 is derived from an echo signal received by a delivery device or the like. is supplied and BPF performs band limitation.
20, and further derives the product of the supplied analog signal and the digital setting value.
2, and a ROM (memory table) 24 that stores digital values of the TVG curve that controls the signal derived from the multiplying D/A converter 22 to a predetermined level.
and an amplifier circuit 26. Further, a sample hold circuit 32 to which the human input signal SIS derived from the amplifier circuit 26 is supplied, and a sample hold circuit 32 having the same center frequency f as the human input signal SIS. It has a clock signal generator 34 for sending out a clock signal Sl6, an LPF 38, a frequency divider 40, and an address signal generation circuit 42 composed of a digital counter.

Next, the operation of the embodiment configured as described above will be explained.

The high frequency signal SIO is band-limited by the BPF 20 and then inputted to the multiplication D/A converter 22 . The multiplying D/A converter 22 converts the supplied analog signal and digital signal. A value of the product of places is created.

Here, the product value is the TVG curve (
A data signal Sl■ of a data table> is supplied, and the level of the supplied signal is controlled and created based on the data. Subsequently, after being amplified to a predetermined level by the amplifier circuit 26, the input signal 5 is sent to the sample hold circuit 32.
15.

In the sample hold circuit 32, the clock signal generator 3
A hold signal Sat obtained by sampling the input signal 315 is sent out based on the center frequency fo of the clock signal srs determined at step 4. Subsequently, the LPF 38 removes high-order components superimposed on the hold signal Sl'l, unnecessary noise components outside the information band, etc., and creates an output signal 32S.

On the other hand, in the frequency divider 40, the center frequency f supplied from the clock signal generator 34. The clock signal Sll+ is frequency-divided to generate a clock signal 32g which becomes a basic clock with a period T of the address signal generation circuit 42.

The address signal generation circuit 42 is composed of a digital counter, and the R O which stores the digital value of the TVG curve.
Specify the address of M24 to control it. and,
From R O M24, data signal Sl2 is sent every cycle T.
('rvc, data) is supplied to the multiplication D/A converter 22, and control is performed so that the level of the output signal is shaped to a predetermined value.

Such signal processing waveforms are shown in FIGS. 2(a) to 2(d).

The figure (a) shows a clock signal S+s which is sent out from the clock signal generator 34 and serves as a reference clock.

(b) The figure shows the input signal SIS supplied to the sample hold circuit 32. (C) The diagram shows sample hold circuit 3
2 shows a hold signal Stt derived from 2.

(a) The figure shows the output signal Sas sent out from the LPF 38.

The input signal S+s (Figure b) of the sample and hold circuit 32 has a center frequency f. The human input signal Sls is sampled and held at the rising edge of the clock signal S's (Figure a), and as a result, a stepped hold signal Sl7 ( The waveform is as shown in Figure C. At this time, the timing of gain switching is set so that the gain is switched immediately after the sample and hold ends and at a period T.

When gain switching is performed, a glitch occurs as shown in Fig. 3), but the glitch occurrence time t is represented by the settling time of the multiplying D/A converter 22, and for example, within 1 μsec. be. On the other hand,
The period tex of the clock signal Sl6 is, for example, a high frequency signal S. When the center frequency fo is 100 KHz, it is 10 μsec, which is a sufficiently large value compared to the glitch occurrence time t. Therefore, as a result of the sample hold, the influence of glitches does not appear.

In this way, as shown in the (ω diagram), the sampled and held hold signal SI7 has a stepped waveform.Here, the hold signal SI7 is filtered by the LPF 38, and the output signal S2S is the final output signal. The hold signal SIT (Figure C) is derived from the human input signal SI.
It is converted into a signal of the frequency difference between the clock signal Sl8 (Figure S Cb) and the clock signal Sl8 (Figure a).Signal processing for such frequency conversion is the same as a so-called "sampling scope", which is often used to observe ultra-high frequency continuous signals. On the other hand, from the so-called sampling theorem, which states that ``if sampling is performed at twice the bandwidth of the input signal or more, the original waveform can be completely determined,'' the high-frequency signal SIO including the input carrier wave is cannot be reproduced, but for signals within the bandwidth of the high-frequency signal SIO, it is sufficient to perform sampling at twice the bandwidth or more.In this embodiment, the ratio of the center frequency to the bandwidth is several dozen. The sampling conditions are fully satisfied.

[Effects of the Invention] As described above, according to the sonar receiving device of the present invention, a signal related to detection of a target object is obtained from a high frequency signal derived by receiving an ultrasonic signal reflected by a target object after transmission. A sonar receiving device that derives a high frequency signal includes a multiplying D/A converter that is supplied with a high frequency signal, generates it at a predetermined level and derives the high frequency signal, and further comprises a multiplying D/A converter at a center frequency of the high frequency signal. a sample hold circuit for sampling an output signal of the multiplier, a memory for sending out a control signal for changing a digital setting value related to the gain of the multiplying D/A converter, and having a memory table; and an address generation circuit that sends out an address signal that causes the memory table switching timing to be immediately after the sampling, thereby reducing the influence of glitches that occur when switching the gain of the multiplying D/A converter. or effectively prevented;
Signal processing can be performed without the output signal being limited by the time axis, and erroneous recognition of signals related to reflection from a target object is reduced, resulting in the effect that a stable operating state can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall structure of the sonar receiving device according to the present invention, and FIGS. 2(a) to 2(d) are signal processing waveform diagrams used to explain the operation of the embodiment shown in FIG. , FIG. 3 is a block diagram showing the overall structure of a conventional sonar receiving device, and FIG. be. 20...BPF 22...Multiple D/A converter 24...R
OM 26...Amplifier 32...Sample hold circuit 34...Clock signal generator 38...LPF4
0... Frequency divider 42... Address signal generation circuit

Claims (2)

[Claims] (1) After transmission, the high-frequency signal is supplied to a sonar receiving device that derives a signal related to target object detection from the high-frequency signal derived by receiving the ultrasonic signal reflected by the target object, and the high-frequency signal is Multiplying D generated and derived from
/A converter, a sample hold circuit that samples the output signal of the multiplying D/A converter at the center frequency of the high-frequency signal, and a digital setting value related to the gain of the multiplying D/A converter. A sonar receiver comprising: a memory that sends out a control signal for changing the memory table and includes a memory table; and an address generation circuit that sends out an address signal that causes the switching timing of the memory table to be immediately after the sampling. Device. (2) The sonar receiving device according to claim 1, further comprising: a BPF to which a high-frequency signal is supplied and sends a signal in a predetermined band to a multiplying D/A converter; What is claimed is: 1. A sonar receiving device comprising: an amplifier disposed to amplify a sampled signal and send it to a sample-and-hold circuit; and an LPF that removes frequency components in a predetermined band from the sample-and-held signal.