JPH0324483A - Fault diagnostic circuit - Google Patents

Abstract

PURPOSE:To achieve a labor saving in fault diagnostics by a method wherein a test signal generated outside an electronic device is inputted into the electronic device to judge the propriety of electronic circuits and a fault part is specified automatically based on the results of judgment. CONSTITUTION:Various patterns of test signals 11 necessary for inspecting actions of electronic circuits 3A-3N are generated from a test signal generator 4 independent of an electronic device 2. The signals 11 are inputted into the electronic circuits 3A-3N of the device 2 through signal switch 1 and outputs signals 12A-12N from the circuits 3A-3N are compared with expected value signals for the signals 12A-12N with a propriety judging device 5 to judge the propriety of actions of the circuits 3A-3N. Then, the results of the judgment are outputted sequentially to a specifying device 6 for troubled parts to specify the troubled parts automatically thereby achieving a significant labor saving in fault diagnostics.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a failure diagnosis circuit. (Prior Art) As is well known, in order to facilitate maintenance of electronic devices, electronic circuits with minimum replacement units are used. It is constructed by interconnecting multiple electronic circuits, and enables fault diagnosis and maintenance for each electronic circuit.In other words, for example, each electronic circuit has a built-in test signal generator that generates a predetermined pattern of test signals. , the person in charge places the electronic circuit in test mode, inputs a test signal, compares the output signal at the output stage with the expected value signal using a measuring instrument, and determines the quality of the electronic circuit. This is performed for all electronic circuits in sequence. (Problem to be solved by the invention) However, the conventional fault diagnosis method described above has the following problems. Namely, when using a test signal built into the electronic circuit. Since the types of test signal patterns are limited, it is difficult to check the entire operation of the circuit using this limited pattern of test signals.

Therefore, in order to completely check the operation of each electronic circuit, make a correct pass/fail judgment, and correctly identify the failure location, a specialized fault diagnostician must carefully examine each electronic circuit using a dedicated measuring instrument. First, the fault diagnosis process takes a lot of time. The present invention was made in view of these conventional problems, and its purpose is to provide a fault diagnosis circuit that can automatically identify a faulty part. (Means for Solving the Problems) In order to achieve the above object, a fault diagnosis circuit of the present invention has the following configuration.

That is, the fault diagnosis circuit of the present invention is a fault diagnosis circuit that diagnoses the fault of each electronic circuit in an electronic device constituted by a plurality of interconnected electronic circuits; a test signal generator that generates;
a signal switcher that switches between the device input signal and the test signal and applies it to the input stage of the device; and a signal switch that compares the output signal for the input test signal with the expected value signal for this output signal at the output stage of each electronic circuit; The present invention is characterized by comprising: a pass/fail determiner that determines the quality of an electronic circuit; and a failure part locator that identifies a faulty electronic circuit based on the output of the determination result of the pass/fail determiner. (Operation) Next, the operation of the fault diagnosis circuit of the present invention, which is designed as described above, will be explained. In the present invention, the test signal generator is provided as an independent circuit, so that it is possible to generate a test signal of an arbitrary pattern. This test signal is switched with the device input signal and input to the device. The arrangement of each electronic circuit in the device is usually determined based on the flow of signals, etc., and the quality of each electronic circuit is judged in the order according to this rule. Then, based on the successive judgment results, if the previous judgment result was ``good'' and the current judgment result was ``fail,'' it would be possible to identify that the electronic circuit corresponding to J is the faulty part. The above fault diagnosis operation is
Everything is done automatically, eliminating the need for specialized measuring instruments and specialized troubleshooters, which were required in the past, resulting in significant labor savings.

(Example) Examples of the present invention will be described below with reference to the attached drawings. FIG. 1 shows a fault diagnosis circuit according to a first embodiment of the present invention. In FIG. 1, the electronic device 2 is interconnected with a plurality of electronic circuits (3A to 3N) having the minimum exchange rate.
The arrangement of these plurality of electronic circuits (3A to 3N) is determined based on the flow of signals and the like. The test signal generator 4 arbitrarily generates test signals 11 of various patterns necessary to sufficiently check the operation of each electronic circuit (3A to 3N).This is possible even though it is an independent circuit.Signal The switch 1 is installed in front of the electronic device 2 and switches between the device input signal 10 and the test signal 11 and sends it to the electronic device 2.
output as an input signal. There are various control modes for this signal switch, the details of which will be described later. The pass/fail determiner 5 receives the output signal (12A to 12N) of each electronic circuit (3A to 3N) to which the test signal 11 is input, compares it with the expected value signal, and determines the output signal of each electronic circuit (3A to 3N).
A to 3N) are performed in a predetermined order, for example, starting with the electronic circuit 3A, and the results of the determination are sequentially output to the failure part locator 6. The failure part specifier 6 has a built-in failure diagnosis algorithm as shown in Table 1, for example, and sequentially monitors the input of the quality judgment results for the output signals of each electronic circuit (3A to 3N), and performs judgment up to, for example, electronic circuit 3D. Pass/fail judgment result ○・・・・・・
... Good, ×... Song not good. The result in Table 1 is "Good", and the next judgment result of electronic circuit 3E is "
If not, the electronic circuit 3E is identified as the faulty part. Next, FIG. 2 shows a fault diagnosis circuit according to a second embodiment.
This second embodiment circuit has a mode selector 7 added. This mode selector 7 has the following functions for the signal switch 1:
A switching control signal 13 is output so that the device input signal 10 is selected when the electronic device 2 is in an operating state, and the test signal 11 is selected when the electronic device 2 is in an inactive state. That is, according to the circuit of the second embodiment, the mode selector 7 is controlled from the outside to select the operation mode of the electronic device 2, and the failure diagnosis is performed when the electronic device 2 is in a non-operational state. Can be done. In addition, as shown in FIG. 3, a timing controller 8 is interposed between the signal switch 1 and the mode selector 7 to detect failures when the electronic device 2 is in operation, and to identify failure parts when the electronic device 2 is not in operation. It can also be configured to do so. That is, when the mode selection signal 14 output from the mode selector 7 indicates the operating state, the timing controller 8 causes the signal switch 1 to select the test signal 11 only within a predetermined time based on a predetermined timing schedule. A switching control signal 13 is output to the switch. At this time, the failure part specifier 6 detects the electronic circuit 3N at the last stage.
monitors the pass/fail judgment result of the output signal, and the judgment result is “
If the answer is "No", it is determined that a failure has occurred in one of the electronic circuits 3A to 3N. Based on this determination result, the mode selector 7 is caused to select the non-operating state, and the timing controller 8 is caused to output a switching rtirm signal 13 so that the signal switch 1 always selects the test signal 11. As a result, the failure part specifier 6 detects each electronic circuit (3A to 3N).
) can be sequentially monitored as described above to determine the failure location. Note that, as shown in FIG. 4, a common bus 9 is provided within the electronic device 2.
Each electronic circuit (3A to 3N) sequentially outputs an output signal (12A to 12N) corresponding to the test signal 11 to the common bus 9 based on a predetermined timing schedule, and each output signal (12A to 12N) is The data may be input to the pass/fail determiner 5 serially from the bus 9. In this way, the number of input signal lines to the pass/fail determiner 5 can be significantly reduced. Note that this procedure is the first
It goes without saying that this method can be similarly applied to those shown in Figures 2 and 2. (Effects of the Invention) As detailed above, according to the fault diagnosis circuit of the present invention,
We have made it possible to input a test signal arbitrarily generated outside the electronic device into the electronic device, thoroughly judge whether each electronic circuit is good or bad, and automatically identify the faulty part based on the judgment results. This eliminates the need for dedicated measuring instruments and specialized troubleshooting TIR personnel, which were previously required, resulting in significant labor savings.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a fault diagnosis circuit according to a first embodiment of the present invention, FIG. 2 is a block diagram of a fault diagnosis circuit according to a second embodiment, and FIG. 3 is a block diagram of a fault diagnosis circuit according to a third embodiment of the present invention. 4 is an elliptical block diagram of the fault diagnosis circuit according to the fourth embodiment. 1...Signal switcher, ~3N...Electronic circuit, 5...Good/failure judge, 7...Mode selector, 9...・Common bus. 2...Electronic device, 3A 4...Test signal generator, 6...Failure part locator, 8...Timing control 6L device,

Claims (1)

[Claims] A fault diagnosis circuit for diagnosing the failure of each electronic circuit in an electronic device composed of a plurality of interconnected electronic circuits; the fault diagnosis circuit includes a test signal generator for generating a test signal; and a device input. a signal switcher that switches between a signal and a test signal and applies it to the input stage of the device; a signal switch that compares the output signal for the input test signal and the expected value signal for this output signal at the output stage of each electronic circuit; A fault diagnosis circuit comprising: a pass/fail decider for making a pass/fail decision; and a failure part specifyer for specifying a faulty electronic circuit based on the judgment result output of the pass/fail decider.