JPH03243925A - Liquid-crystal display and manufacture - Google Patents

Abstract

PURPOSE: To lower the resistance of a data bus line, to lower the possibility of the opening of the data bus line and to improve image contrast by forming a data line in a single step on a substrate by N<+> polysilicon and turning the data line to a hybrid conductor provided with two layers in contact further. CONSTITUTION: Data buses 28 are made to run parallelly to respective columns, gate lines 30 are made to run parallelly to respective rows and respective pixel electrodes 26 are connected to one data bus 28 and one gate line 30 by the thin film transistor 24 of a stagger structure near an intersection among the data and gate lines. A transistor source 34 is connected to the data bus line 28, input data are sent from there through a transistor channel to a transistor drain 36 connected to the pixel electrode 26 and a transistor gate 38 is connected to a scanning line 30. At the time of manufacture, the data line is formed on the substrate by the N<+> polysilicon by one operation and a metal overlay is executed on the data bus 28 and a pixel electrode area surface. Thus, disconnection or an open signal line during the manufacture are reduced, reliability is improved and the image contrast is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field 1] The present invention generally relates to flat liquid crystal matrix displays (
Regarding thin film transistors (LCD), more specifically thin film transistors (
(TFT) in which each pixel is directly addressed.

[Prior Art 1] Flat electronic displays that are not as large and do not consume as much power as cathode ray tubes have been the goal of display manufacturers and display users since the invention of thin film transistors around 1970. However, manufacturing flat panel electronic displays addressed by thin film transistor arrays is the most exciting design task. Nevertheless, by 1986 only a few companies had been able to establish production lines for TPT address liquid crystal displays.

The advantage of a multi-address liquid crystal display is that it has the same number of human-powered bus lines as for conventional multiple address techniques used in matrix displays.

Furthermore, thin film transistors have a directed address (direct address).
There are no adverse effects caused by the duty ratio in the ted addressing method.

Based on the advantages of TPT addressing, the number of pixels that can be included in a liquid crystal display is unlimited and desired gray levels can be easily generated.

In the next decade, active addressed matrix displays using thin film transistor arrays appear to be the dominant display technology.

One of the most important thin film transistor manufacturing processes is chemical vapor deposition (CVD). Because the CVD method is very flexible, the structure of thin film transistors varies significantly from manufacturer to manufacturer. Generally, there are two types of thin film 1~lancisister structure,?
In other words, it is a stagger type or Brenna type TPT.

Staggered structures are conventionally used for amorphous silicon in thin film transistors because different films can be deposited sequentially by chemical vapor deposition techniques. This has the advantage of reducing pollution from the environment and lowering manufacturing costs.

On the other hand, polysilicon thin film transistors usually have a coplanar structure. The contemplated process sequences and thermal cycles are similar to conventional integrated circuit manufacturing methods. However, in a 1986 paper by Seiko Epson Corporation of Japan, ``Low-temperature-treated polySTFT and its application to large-area LCD'', 17th Band Display, 1986, No. 196,
199) shows that a hybrid W4 design using a staggered structure of poly5rss+- transistors as a switch in a liquid crystal display pixel has been quite successful.

Yield is the primary issue in constructing thin film transistor liquid crystal matrix displays.

Low yields in manufacturing thin film transistor liquid crystal displays result from two main factors. One is a disconnection or open state of the path line that cannot transmit the picture signal. The other is particles or pinholes within the deposited film. The number of these defects increases as the size of the liquid crystal display increases.

For example, research has been conducted to improve the performance of large-sized liquid crystal displays, such as improving the quality of the liquid crystal material itself and color filters, driving methods, and multi-gap design of RGB color and black matrices. Nevertheless, large screen liquid crystal display images already appear to be as good as cathode ray tubes.

What is desired is a large liquid crystal matrix display that overcomes manufacturing problems that reduce manufacturing yields.

Accordingly, it is an object of the present invention to provide an improved active liquid crystal display panel whose reliability is improved by reducing disconnections or open signal lines during construction.

Another object of the present invention is to provide an improved active liquid crystal display panel having a staggered polysilicon thin film transistor array structure.

Yet another object of the present invention is to provide an improved active LCD panel with improved image contrast quality.

Yet another object of the present invention is to provide an improved active LCD panel that can be manufactured economically in any size and that provides images comparable to cathode ray tubes.

In accordance with embodiments of the present invention, staggered polysilicon TFTs
The array provides an active liquid crystal display panel. The vixel electrodes are arranged on the substrate in a matrix of rows and columns. A data bus runs parallel to each column, and a scanning or gate line runs parallel to each row. Near the intersection between the data and gate lines, each pixel electrode is connected to one data bus and one gate line by a staggered thin film transistor. The transistor source is connected to the data bus line, from which input data is sent through the transistor channel to the transistor drain, which is connected to the pixel electrode. The transistor gate is connected to the scan line.

During manufacturing, transistor sources, drains, and data bus lines are formed in a single step on a substrate in a single operation. An undoped polysilicon film is formed as a gate channel between the source and drain, and is covered by an insulating layer that includes the connection to the transistor source and overlaps the source, drain, and data bus. A metal overlay is applied over the data bus and over the surface of the pixel electrode region through an opening provided in the insulating layer in alignment with the data bus and a portion of the pixel electrode contact region.

During the same operation, a metal gate electrode is formed on the opposite side of the gate channel between the transistor source and drain. The data bus lines and gate lines are insulated from each other at intersections.

The advantage of this structure is that the data lines or buses and the sources and drains of transistors 1 to 1 are formed in a single step on the substrate in a single procedure. Manufacturing costs are lower than conventional integrated circuit processing techniques that use high current implanters to form transistor sources and drains within the substrate. Additionally, the data line is a hybrid conductor with two layers in contact: a metal layer and a single layer. This structure reduces the electrical resistance of the data bus line and reduces the possibility that the data bus line will become open. In fact, the data bus line is only opened if there is a defect at the same location in both layers. Furthermore, whenever gold am is deposited on the gate electrodes and gate scan lines and hybrid data bus, the transmission of light through the liquid crystal display panel is reduced. Image contrast is improved for the entire display.

[Example] FIG. 2 is a cross-sectional view of the prior art staggered thin film transistor 10 of FIG. 1. A single step source 12 on a substrate 16, which can be a glass, quartz, or silicon wafer.
and a drain 14 are formed. A gate channel 18 of an undoped polysilicon film is formed between the source 12 and drain 14. A gate insulator 20 is grown or deposited over the gate channel 18 . Gate insulator 2
0 is a thermal oxide or oxide and nitride formed by low pressure chemical vapor deposition. A gate electrode 22 located on the opposite side of the gate channel 18 is formed of any metal, and the on/off state of the gate channel 18 is controlled by a voltage applied to the gate electrode 22 in a known manner.

FIG. 2 shows a fragment of a liquid crystal matrix display in which a thin film transistor 24 is used to control a single pixel element 26 in accordance with the present invention. As is known, a liquid crystal display is a pixel matrix arranged in horizontal rows and vertical columns. In accordance with the present invention, each vixel 26 is similarly addressed by an associated thin film transistor 24.

The following description regarding the illustrated LCD fragment applies to any display element.

Display signals are available to the pixels 26 via a vertical data bus 28. A data bus 28 is routed along each pixel 26 within a given column of the matrix display, ie, running in the y direction in FIG. This signal on data bus 28-[ is received by pixel 26 only when switching transistor 24 is on. The gate scanning line 30 is horizontal,
ie, in the X direction, each row of pixels 26 is associated with one tree of scanning lines 30. Scan [930 is [-
Connected to the gate of transistor 24, an associated data bus 28 is connected to the source of transistor 24, and pixel 26 is connected to the drain of transistor 24.

It is believed that transistor 24 is turned on only when the associated G1-Scan line 30 is high and a signal is simultaneously applied to the associated data bus 28.

A gate channel 38, shown in phantom in FIG. 2, extends between source 34 and drain 36 and faces gate electrode 32. At any given time, only one gate scan line 30 is high and a signal is present on only one data bus 28. Thus, at any given time, only one pixel 26 is driven, although other vixels generally retain previously received signals.

Switching transistor 24 is a thin film transistor having the structure described below with respect to FIGS. 3a-3d.

As a first manufacturing step, the source 34 and drain 3
6 and data bus 28 are formed as a single step film or layer on a glass substrate 40 (FIG. 3a). The drain 36 includes a portion that acts as a pixel electrode contact region 42, and the source 34 extends toward the data bus 28 so that the one-step film or layer provided in the first step is connected to the source 34. data bus 2
8 within an integral structure. Further, the drain 36 and the vixel electrode contact i-¥142 are also integrated with each other. The source 34 and drain 36 are separated by a space, and the gate channel 38 is formed by an undoped polysilicon film overlying the substrate and overlapping the source and drain (Figure 3b).

A gate insulator 44 is then formed over the gate channel 38 by thermal oxide or low pressure chemical vapor monolayer oxide and nitride (Figure 3C). The insulator film 44 is the drain 36
and extends to substantially cover not only pixel electrode contact area 42 but also data bus 28 and source 34 .

However, due to masking, a portion 43 of the data bus 28 and a portion 45 of the vixel electrode contact region VJ, 42 are not covered with the gate insulator film 44. Regions [43, 45] of the structure that are not covered by the insulating film 44 are indicated by diagonal lines in FIG.

Thereafter, the gate electrode 32 is superimposed on the gate channel 38.
A gate metal pattern is formed (3d
figure). At the same time, a metal layer 46 is formed in the shaded area 43.45 in FIG. 2 where the insulator 44 is not present. Therefore, most of the data bus 28 except for the intersection with the gate scanning line 30 has a two-layer hybrid structure. On top of the N+ polysilicon layer 28 adjacent to the substrate 40 is a metal layer 46. Pixel electrode contact region 42 is also a hybrid structure consisting of one step layer adjacent to substrate 40;
The second step layer is covered with a metal layer 46. In this way, a staggered thin film transistor according to the present invention is formed.

In the same process of forming the metal gate electrode 32 and the hybrid layer 46, the gate scanning line 30 is formed on the substrate 40 using the same metal. Therefore, the gate electrode 32 and the scanning line 30 become an integral part of the same layer.

In summary, on a substrate 40, which can be a glass, quartz or silicon wafer, sources, drains, associated data buses and associated pixel electrode contact regions are formed in one operation. A gate channel 38 is formed over and between source 34 and drain 36.

Next, the data bus 28, the source 34, the drain 36, the vixel electrode contact region 1i! ! An insulating layer 44 is formed that extends to cover the entire single step layer including 42 and gate channel 38 . Known masking (and/or
The data bus 28 and portions of the pixel electrode contact areas 42 are stripped of the insulator coating by a technique (or etching). Finally, the gate electrode 32 of the transistor and the connected gate scan line 30 are deposited in the same manufacturing step. The exposed portions 43.45 of the data bus 28 and pixel electrode contact area 42 are also coated with the same metal in the same operation as the gate electrode and gate scan line formation.

According to the size of the display, dozens of pixels in the LCD panel can be manufactured at the same time.

In a transmission type liquid crystal display matrix, the pixel electrodes 26 may be indium tin oxide (100). In a reflective liquid crystal display matrix, the vixel electrode Iti26 can be metal.

A metal layer 46, which is a shunt conductor overlapping a portion of the data bus 28, is in direct and continuous contact with a single step layer of the data bus 28. Therefore, when data bus 28 is open in the region shunted by metal heavy WIi 46, signals are still passed to transistor source 34.

In fact, an infinite number of signal paths can be used to compensate for a break in the continuity of the data bus polysilicon film 28 or metal overlay layer 46, as long as the break does not occur at the exact same location in both layers. Therefore, compared to the conventional structure in which the data bus has a single layer, the data signal is transferred to the transistor 24.
The probability that the data will not be input is significantly reduced.

The metal layer forming the shunt conductor 46, which overlaps a portion of the gate electrode, gate scan line, data bus, and pixel electrode contact area, is opaque, and the L between adjacent pixels 26 is
Unwanted light transmission through the CD panel is prevented. Therefore, image contrast and quality are improved. Using the staggered structure, the thin film transistor 24 acts as a gate switch for the liquid crystal display matrix.
provides image quality comparable to cathode ray tubes.

Since glass substrates can be used in staggered structures, larger displays can be manufactured at lower cost than cobrasted structures which require more expensive substrates.

The double layer structure of the data bus reduces the resistance of long data bus lines in large flat panel displays.

Furthermore, since the metal layer covers a large area of the flat panel display, this structure prevents light transmission and improves the image contrast quality of the liquid crystal display. Furthermore, the photoelectric response is reduced in the region covered with the metal layer.

Those skilled in the art will understand that what has been described so far is the structure and manufacturing method of an element associated with one liquid crystal matrix display substrate. In a complete display, a second substrate with at least one electrode faces the first substrate, with a space between the substrates containing the liquid crystal material.

Therefore, it will be seen that the said objective is efficiently achieved from what has become clear from the foregoing description. All matter contained in the foregoing description and accompanying drawings is intended to be illustrative only and in a restrictive sense, as certain changes may be made to the structure without departing from the spirit and scope of the invention. shall not be. The claims are intended to include all general and specific features of the invention as described herein and all statements of the scope of the invention.

FIG. 2 is a partial schematic diagram of a liquid crystal display with pixels driven via thin film transistors according to the invention; FIGS. 3a to 3d show the manufacturing steps of the liquid crystal display; FIG. 4 is a sectional view taken along line 3--3 in FIG. 2, and FIG. 4 is a sectional view taken along line 4--4 in FIG.

Explanation of reference symbols 10...Stagger WI film transistor 12.34...
・Source 14.36...Drain 16...Substrate 18.38...Gate channel 20.44...Group 1~Insulator 22.32...Gate electrode 24...1ill transistor 26... - Pixel element 28...Data bus 30...Gate scanning line 40...Glass substrate 42...Pixel electrode contour 46...Metal layer contact area

Claims (15)

[Claims] (1) A liquid crystal display having a plurality of pixels arranged in a matrix of rows and columns, the display comprising a substrate, several parallel spaced data buses on said substrate, and each substantially orthogonal thereto. gate scan lines insulated from each other at the intersection, each pixel including a pixel electrode having a pixel electrode contact area, the pixel electrode at the intersection of the one data bus and the one scan line; adjacently arranged, the display further includes: pixel contact regions formed of the same material as sources connected to the one data bus, connected to the data bus, the sources and drains of the transistors, and the pixel electrode contact regions; a thin film transistor having: a gate channel contacting and extending between a source and a drain of the transistor; an insulating layer overlapping the gate channel, the source and the drain; and an insulating layer overlapping the insulating layer. a gate electrode disposed opposite to the gate channel and connected to the one gate scan line. (2) In the liquid crystal display according to claim (1),
The liquid crystal display further comprises a conductive layer overlapping at least a portion of the one data bus and the pixel electrode contact area and made of the same material as the gate electrode. (3) In the liquid crystal display according to claim (1),
The data bus, the source, the drain, and the pixel electrode contact regions are made of N+ polysilicon, and the gate channel is made of undoped polysilicon. (4) In the liquid crystal display according to claim (2),
The one gate scanning line, the gate electrode, and the conductive layer overlapping the data bus and the pixel electrode contact area are formed of the same material. (5) In the liquid crystal display according to claim (3),
The source, the drain, the data bus, and the pixel electrode contact area are formed directly on the substrate. (6) A method for manufacturing a liquid crystal matrix display having pixel electrodes disposed on a substrate, including: a) sources and drains of thin film transistors on the substrate, a data bus connected to the sources of the transistors, and forming a pixel electrode contact region connected to the drain, the connection between the data bus and the source being an extension from the data bus to the source in a common layer; The connection is an extension from the drain to the pixel electrode contact region in the common layer, the source and drain being spaced apart on the substrate, and the source, drain, data bus and pixel electrode contact region are the same material; b) forming a gate channel on the substrate between the source and drain, the channel being connected to the source and drain; c) forming an insulating layer over the source, drain, and channel; forming and eliminating the insulator layer from exposed portions of the data bus and pixel electrode contact regions; d) forming a gate electrode on the insulator layer, the gate electrode being connected to the source;
A method for manufacturing a liquid crystal matrix display, comprising steps arranged opposite a drain and a gate channel. (7) The method according to claim (6), further comprising the step of: e) forming a gate line on the substrate, and connecting the gate line and the gate electrode. (8) The method of claim (7), wherein the data bus portion is exposed, and further comprising: f) forming a first conductive superimposed layer on the exposed portion of the data bus, and forming a first conductive superimposed layer on the exposed portion of the data bus, The bus consists of steps electrically joined over mutual contact areas.
A method of manufacturing a liquid crystal matrix display. (9) The method according to claim (8), wherein the pixel electrode contact region portion is exposed, and further comprising: g) forming a second conductive superimposed layer on the exposed portion of the pixel electrode contact region; A method for manufacturing a liquid crystal matrix display, comprising the steps of: two electrically conductive superimposed layers and the pixel electrode contact area are electrically bonded over mutual contact areas. (10) In the method according to claim (9), the gate line, the gate electrode, and the first and second overlapping layers are
A method for manufacturing a liquid crystal matrix display, which is formed from metal in two steps. 11. The method of claim 6, wherein the source, drain, data bus and pixel electrode contact regions are formed in one step. (12) A method of manufacturing a liquid crystal matrix display according to claim (6), wherein the source, drain, data bus and pixel electrode contact regions are formed of N+ polysilicon. (13) A method for manufacturing a liquid crystal matrix display according to claim (12), wherein the channel is formed of undoped polysilicon. 14. The method of claim 8, wherein the gate electrode, gate line, and first conductive overlay are formed of the same material in one step. (15) The method according to claim (9), wherein the gate electrode, the gate line, the first conductive superimposed layer, and the second conductive superimposed layer are formed of the same material in one step. Production method.