JPH03241986A - Highly efficient coder and highly efficient decoder - Google Patents

Abstract

PURPOSE:To reduce coding distortion by interpolating a picture element with an interpolation device and a low pass filter(LPF) so as to attain ease of coding. CONSTITUTION:An input signal 1 is given to an interpolation device 15, in which number of vertical picture elements is interpolated twice. An interpolation signal 16 is subjected to band limit by a low pass filter(LPF) 17 and a high frequency component is eliminated. The eliminated frequency is a frequency not substantially included in the input signal to avoid a cause to picture quality deterioration. A filter signal 18 is block-processed by a block processing device 19 and a coder 21 applies 3-dimension coding, A component not eliminated by the LPF 17 is efficiently coded by applying variable length coding or the like in the coder 21. Then the interpolation device 15 and the LPF 17 are employed to interpolate the picture element for the ease of coding in this way, then the compression rate is improved and the coding distortion is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a high-efficiency encoding device and a high-efficiency decoding device used to reduce the amount of data for recording, reproducing, or transmitting interlaced image signals. It is.

Prior Art A block diagram of a conventional high-efficiency encoding device is shown in FIG. In the figure, 1 is an input signal, 2 is a blocker that blocks the input signal l, 3 is a blocked signal of the blocker, 4 is an encoder that encodes the blocked signal 3, and 5 is the coded signal of the encoder 4, 6 is a selector that compares the coded signals 5 and selects the coded signal 5 with a higher compression rate, and 7 is the coded output signal selected by the selector 6. .

In the conventional high-efficiency encoding device configured as described above, the input signal 1 is blocked by the blocker 2, and
It is sent to encoder 4. There are a plurality of encoders 4, for example, one performs intra-field encoding and one performs inter-field encoding. The encoded signals 5 are compared by a selector 6, and the one with the highest compression rate, that is, the one with the shortest code length, is selected, and a signal indicating the encoder (encoding means) thereof is output together with the encoded signal 5 to generate the code. The converted output signal becomes 7.

Further, a block diagram of a conventional high-efficiency decoding device is shown in FIG. 17. In the figure, 8 is an input signal, 9 is a selector for selecting a decoding means for decoding the input signal 8, and 10 is a selector. 11 is a decoder that decodes the input signal lO, 12 is the decoded signal decoded by the decoder ti, and 13 is an inverse block that deblocks the decoded signal 12. The deblocker 14 is the output signal deblocked by the deblocker 13.

In the conventional high-efficiency decoding apparatus configured as described above, the input signal 8 is switched by the selector 9 so that it is decoded by the decoding means corresponding to the encoding means of the high-efficiency encoding apparatus. The decoded signal 12 decoded by the decoder 11 selected in this way is deblocked by the deblocker 13 in accordance with the blocking performed by the high-efficiency encoder, and is output. A signal 14 is obtained.

Problems to be Solved by the Invention However, the above configuration requires multiple encoders or multiple decoders, so the hardware scale is large. Complex control is required to switch efficiently.

In view of the above, the present invention provides a high-efficiency encoding device and a high-efficiency decoding device that have relatively simple hardware and can obtain a compression ratio higher than that of a conventional high-efficiency encoding device and a conventional high-efficiency decoding device. The purpose is to provide a device for converting

SUMMARY OF THE INVENTION The present invention provides a pixel interpolation means for interpolating or low-pass filtering pixels between adjacent scan lines of an interlaced image input signal; consisting of pixels generated by the pixel interpolation means,
and coding means for coding the pixels blocked by the blocking means for blocking into pixel blocks containing at least two fields of pixels at the same horizontal and vertical positions as the pixel. a high-efficiency encoding device; a pixel interpolation means for interpolating or low-pass filtering pixels between adjacent scan lines of an interlaced image input signal; Blocking into a rectangular parallelepiped pixel block consisting of pixels generated by a pixel interpolation means and consisting of several horizontal pixels, several vertical pixels, and at least two fields of pixels at the same horizontal and vertical positions as the pixels. A high-efficiency encoding device comprising: orthogonal transformation means for orthogonally transforming pixels blocked by the means; and encoding means for encoding pixel information orthogonally transformed by the orthogonal transformation means; a pixel interpolation means that generates pixels between adjacent scanning lines of the image input signal by interpolation or a low-pass filter; and several pixels of the human input image signal and several pixels generated by the pixel interpolation means. and encoding means for encoding the blocked pixels by the blocking means for blocking into pixel blocks containing at least two fields of pixels at the same horizontal and vertical positions as the pixel. Using a signal encoded by the high-efficiency encoding device as an input signal, the input signal is decoded by a decoding means that decodes the decoded signal from a blocked state to each field. The present invention is characterized by comprising a thinning means for selecting only the pixels necessary for a non-interlaced signal and removing other pixels from among the pixels rearranged by the deblocking means for rearranging them at corresponding pixel positions and deblocking them. a pixel interpolation means for generating pixels between adjacent scan lines of an interlaced image input signal by interpolation or a low-pass filter; A block to be formed into a rectangular parallelepiped pixel block consisting of the pixels generated by the pixel interpolation means and consisting of several horizontal pixels, several vertical pixels, and at least two fields of pixels at the same horizontal and vertical positions as the pixels. A high-efficiency encoding device characterized by comprising: orthogonal transformation means for orthogonally transforming the pixels blocked by the orthogonal transformation means; and encoding means for encoding the pixel information orthogonally transformed by the orthogonal transformation means. an orthogonal transform, which is an inverse transform of the orthogonal transform used in the high-efficiency encoding device, on the signal decoded by a decoding means that decodes the input signal, using the decoded signal as an input signal. a converting means, and a deblocking means for rearranging the signals orthogonally transformed by the orthogonal transforming means into corresponding pixel positions of each field; each pixel rearranged by the deblocking means; A high-efficiency decoding device characterized by comprising a thinning means for selecting only pixels necessary for a non-interlaced signal and removing other pixels; a pixel interpolation means that generates pixels by interpolation or a low-pass filter, several pixels of a human image signal, several pixels generated by the pixel interpolation output, and several horizontal pixels, several vertical pixels, and orthogonal transformation means for orthogonally transforming the pixels blocked by the blocking means for blocking into rectangular parallelepiped pixel blocks consisting of at least two fields of pixels at the same horizontal and vertical positions as the pixels; A decoding means for decoding the input signal using, as an input signal, a signal encoded by a high-efficiency encoding device characterized by comprising an encoding means for encoding pixel information subjected to orthogonal transformation. An orthogonal transform means performs an orthogonal transform, which is the inverse of the orthogonal transform used in the high-efficiency encoding device, on the signal ζ decoded by the decoded signal ζ, and a non-interlaced signal among the signals orthogonally transformed by the orthogonal transform means. A thinning means for selecting only necessary pixels and removing other pixels, and a deblocking means for rearranging the Shingetsu thinned out by the thinning means from the blocked state to corresponding pixel positions of each field. a high-efficiency decoding device characterized by: a pixel interpolation means for generating pixels between adjacent scanning lines of an interlaced image input signal by interpolation or a low-pass filter; Blocked into a rectangular parallelepiped pixel block consisting of a pixel and several pixels generated by the pixel interpolation means, and also consisting of several horizontal pixels, several vertical pixels, and at least two fields of pixels at the same horizontal and vertical positions as the pixel. High efficiency characterized by comprising: orthogonal transformation means for orthogonally transforming pixels blocked by the blocking means, and encoding means for encoding pixel information orthogonally transformed by the orthogonal transformation means. As an input signal, the signal encoded by the encoding device is
orthogonal transform means for performing an orthogonal transform, which is the inverse of the orthogonal transform used in the high-efficiency encoding device, on the signal decoded by the decoding means for decoding the input signal;
The signal orthogonally transformed by the orthogonal transform means is rearranged from the blocked state to the corresponding pixel position of each field. and a thinning means for selecting only pixels necessary for a non-interlaced signal and removing other pixels from the low-frequency signal obtained by the high-frequency component removing means. This is a highly efficient decoding device characterized by:

It is a device.

Effect of the present invention 5+i? According to the ti precept mentioned in 1, the interlaced image hole number 3 is converted to non-interlaced by pixel interpolation, and the pixels at the same position between field 1 are also blocked, horizontally, vertically, and temporally (field). Three-dimensional encoding is performed. In conventional high-efficiency encoding devices or conventional high-efficiency decoding devices, pixel data of odd and even fields with different times are expanded as they are on one horizontal and vertical two-dimensional plane, and two-dimensional encoding is performed. Therefore, it is not efficient compared to direct three-dimensional encoding. Furthermore, if the rectangular parallelepiped is blocked and then the orthogonal transform is performed, a simple encoding device with only one encoder is constructed, which is superior to conventional high-efficiency encoding devices and conventional high-efficiency decoding devices. Therefore, there is no need to prepare multiple encoding means or multiple decoding means. Note that the high-efficiency encoding device of the present invention requires an LPF (low-pass filter) to interpolate and generate pixels, but if the encoding distortion is sufficiently moderate, the LPF of the high-efficiency encoding device Therefore, the high-efficiency decoding device of the present invention does not require an LPF. However, when the encoding distortion is large, aliasing distortion occurs due to the high-frequency components of the encoding distortion, so the LP of the high-efficiency decoding device
High frequency components must be removed by F.

Embodiment FIG. 1 shows a block diagram of a high-efficiency encoding device in an embodiment of the present invention. In FIG. 1, l is an input signal, 15 is an interpolator that interpolates input signal 1,
16 is the interpolation signal of the interpolator 15, and 17 is the interpolation signal 1
6 is an LPF that removes high frequency components, and 18 is an LPF
It is a filter signal from which high frequency components have been removed at step 17,
19 is a blocker that blocks the filter signal 18, 20 is a blocked signal blocked by the blocker 19, 21 is an encoder that encodes the blocked signal 20, and 22 is the encoded output of the encoder 21.

The operation of the high-efficiency encoding apparatus of this embodiment constructed as described above will be described below, and first the w1 section will be shown. FIG. 2 is a diagram showing pixel positions in one frame of an interlaced image signal.

In the figure, the circles shaded with diagonal lines are real pixels,
White circles are pixels generated by interpolation.

By generating pixels by interpolation, there are always pixels at the same position in consecutive fields. This facilitates three-dimensional rendering and compression. FIG. 3 shows an example of blocking. In the figure, circles with broken lines are pixels generated by interpolation, and circles with solid lines are actual pixels. The circles filled with diagonal lines are pixels that are blocked by a certain professional, and each field 1
A total of 20 pixels, including 0 pixels, constitute one block. There are 10 pixels that actually exist among the pixels that make up this block, and the number of pixels will double by interpolation, but since 1/2 of the total frequency components do not contain significant information, the pixels Since the overall amount of information is constant and can be easily encoded in three dimensions, if the LPF is used to remove insignificant information and encode it, the compression rate can be increased more than with conventional high-efficiency encoding devices. . In Figure 1, the force signal 1
is interpolated by the interpolator 15 to double the number of vertical pixels.

The interpolation signal 16 is band-limited by the LPF 17 and high frequency components are removed. This removed frequency is a frequency that is not originally included in the input signal and does not cause image quality deterioration. The filter signal I8 is divided into blocks by a block generator 19, and three-dimensionally encoded by an encoder 21. This encoder 21 can efficiently encode the components not removed by L P F 17 by performing variable length encoding or the like.

As described above, according to this embodiment, the interpolator 15 and the LPF 1
By interpolating pixels in step 7 to create a flock configuration that is easy to encode, the compression rate can be improved and encoding distortion can be reduced.

FIG. 4 is a block diagram of a high efficiency decoding device in an embodiment of the present invention. In the figure, 8 is an input signal that is a signal encoded by a high-efficiency encoding device, 23 is a decoder that decodes the input signal 8, and 24 is a decoder 2.
3 is a decoded signal decoded, 25 is a deblocking signal for deblocking the decoded signal 24, and 26
is a deblocked signal rearranged by the deblocking device 25, 27 is a thinner that thins out the deblocked signal in the vertical direction, and 28 is a signal thinned out by the thinning device 27.

The operation of the high-efficiency decoding device of this embodiment configured as described above will be explained below.The 0 input signal 8 is decoded by the decoder 23 and blocked by the inverse programmer 25. state to a non-interlaced signal. The non-interlaced deblocked signal 26 is decimated by a decimator 27 and converted into an interlaced signal. If the encoding distortion is sufficiently small, the LP of the high-efficiency encoding device
The signal components at frequencies that cause aliasing distortion are removed by thinning H27 by F, and an LPF is not necessary for a high-efficiency decoding device.

As described above, in this embodiment, a three-dimensional signal is converted into an interlaced signal by a decoder 23 that decodes a signal three-dimensionally encoded by a high-efficiency encoding device, a deblocker 25, and a thinner 27. By converting, a highly efficient three-dimensional encoding decoding device with a simple hardware configuration can be constructed.

Further, in the above embodiment, even if the order of the deblocking device 25 and the thinning device 27 is reversed, the same effect as in the above embodiment can be obtained. A block diagram is shown in FIG. Fourth
Items that perform the same actions as in the figure are given the same numbers. In the figure, 8 is an input signal that is a signal encoded by a high-efficiency encoding device, 23 is a decoder that decodes the input signal 8, and 24 is a signal that is decoded by the decoder 23. A decoded signal, 27 is a thinner that thins out the decoded signal in the vertical direction, 28 is a signal thinned out by the thinner 27, and 25 is a deblocked signal that deblocks the thinned signal 28. 29 is a deblocked signal rearranged by the deblocker 25.

The operation of the high-efficiency decoding device of this embodiment configured as described above will be described below. The input signal 8 is decoded by a decoder 23, and a thinner 27 thins out unnecessary pixels when converting the f-interlaced signal into two. The signal 28 that has been subjected to the thinning process is converted from a blocked state to an interlaced signal 28 by an inverse flow conversion 2S25. By performing thinning by the thinner 27 before deblocking, the number of pixels to be processed in deblocking can be reduced and deblocking can be facilitated.

As described above, according to this embodiment, the decoder 23 decodes the signal three-dimensionally encoded by the high-efficiency encoding device, the thinner 27 and the deblocker 25 convert the three-dimensional signal into an interlaced signal. By converting to It can be done.

FIG. 6 is a block diagram of a high efficiency decoding device in another embodiment of the present invention. In the same figure, 8 is an input signal that is a signal encoded by a high-efficiency encoding device, 23 is a decoder that decodes the input signal 8, and 24 is a signal that is decoded by the decoder 23. 25 is a decoded signal for deflocking the decoded signal 24;
26 is a deblocked signal rearranged by the deblocking device 25, 30 is an LPF that removes high frequency components of the deblocked signal, 31 is a filter output of LPF 30, and 27 is a filter output 32 is a signal thinned out by the thinner 27. This figure has almost the same configuration as the embodiment shown in FIG. 4, except that an LPF 30 is added.

The operation of the high-efficiency decoding device of this embodiment configured as described above will be described below. The steps from the input signal 8 to the deblocked signal 28 are the same as in the embodiment shown in FIG. 4, and will therefore be omitted. When the compression rate due to high-efficiency encoding is large, the decimator 27 is used in the LPF of the high-efficiency encoding device.
Although signal components at frequencies that cause aliasing distortion are removed, a large amount of coding distortion may occur at frequencies that cause aliasing distortion, and an LPF is required in a high-efficiency decoding device.

Therefore, by installing the LPF 30 immediately before the thinner 27, aliasing distortion can be removed and image quality can be improved.

As described above, according to this embodiment, the decoder 23 decodes the three-dimensional encoded signal by the high-efficiency encoding device, the deblocker 25, and the thinner 27 convert the three-dimensional signal into an interlaced signal. By converting, a highly efficient three-dimensional encoding decoding device with a simple hardware configuration can be constructed, and image quality can be improved by removing distortion due to aliasing of encoding distortion using the LPF 30.

FIG. 7 shows a block diagram of an example of a high-efficiency encoding device according to another invention. In FIG. 7, 1 is an input signal, 15 is an interpolator that interpolates the input signal 1, and 16 is an interpolator 15.
17 is an LPF that removes high frequency components of the interpolated signal 16, 18 is a filter signal from which the high frequency components are removed by the LPF 18, and 19 is a blocker that blocks the filter signal 18. 20 is a blocked signal that has been blocked by the blocking device 19, 33 is an orthogonal transformer that orthogonally transforms the blocked signal 2o, and 34 is an orthogonal transformed signal that has been orthogonally transformed by the orthogonal transformer 33. 21 is an encoder that encodes the orthogonal transform signal 33, and 35 is the encoded output of the encoder 21.

The operation of the high-efficiency encoding device of this embodiment configured as described above will be described below. LPF from input signal l
The operations up to step 17 are the same as those in the embodiment shown in FIG. 1, and their explanation will be omitted. The professional flower vase 19 is formed into blocks of rectangular parallelepipeds whose sides are in the horizontal direction, vertical direction, and time direction.

A block model is shown in FIG. FIG. 8 shows a block consisting of 4 horizontal pixels, 8 vertical pixels (including interpolation pixels), and 2 fields. Solid circles represent existing pixels,
The dashed circles indicate pixels generated by interpolation.

When creating two-dimensional blocks within a frame, there is no vertical correlation in the video image, which degrades the encoding efficiency, but by performing interpolation, horizontal and vertical correlation is always maintained regardless of whether it is a video or a still image. Furthermore, in still images, the correlation between fields 1 becomes very strong, similar to intraframe encoding,
Therefore, if the blocking of this embodiment is used, it becomes easy to improve the compression rate of the encoding device. In FIG. 7, the processed signal 20 is orthogonally transformed by an orthogonal transformer 33. In FIG. Orthogonal transforms include DCT (discrete cosine transform), Hadamard transform, and KL transform (Cal-Funley transform).
The signal after these conversions corresponds to the frequency of the original signal.

Therefore, if we perform such orthogonal transformation on blocked signals that have strong correlations in the vertical, horizontal, and temporal directions and arrange them in order of frequency height, the energy (maximum value) of the lower frequencies will be larger. Become. FIG. 9 shows an example of each component subjected to orthogonal transformation. In the figure, the shaded areas represent areas with a lot of energy, and the other areas represent areas with relatively little energy. Furthermore, the components are arranged so that the closer to the top left, the lower the frequency. In the same figure (a), the stationary part,
Figure fb) shows a large moving part, and Figure 5(C) shows a small moving part that has been orthogonally transformed. In the same figure fa), only the lowest order frequency in the time direction is present, while in the same figure (b)
In this case, a lot of energy is also generated in high-order time-direction components, but because the high-frequency components are attenuated due to the imaging characteristics of moving images, the energy in the horizontal and vertical high-order frequency components decreases. Therefore, the small movements that often occur in -S are shown in the same figure (a
) and 121(b), the distribution is as shown in FIG. 12(C). In FIG. 7, an orthogonal transformed signal 34 is encoded by an encoder 21.

This encoding is desirably adapted to the characteristics of orthogonally transformed images.An example of the encoding means will be described with reference to FIG. 1O. This figure shows the distribution of orthogonally transformed signals, and like FIG. 9, the signals are arranged so that the lower frequency components are in front of the upper left. In the figure, areas corresponding to components other than 0 are indicated by diagonal lines.

The area where the total value is 0 is very large, and the lower the frequency, the more values other than 0 occur. Therefore, we will consider a rectangular parallelepiped that includes all values other than 0, and encode only the signals inside the rectangular parallelepiped. In FIG. 10, a rectangular parallelepiped is illustrated by a broken line. At this time, the compression ratio is improved by run-length encoding O of the internal signal and Huffman encoding the other signals.

FIG. 11 shows an example of an encoder. 36 is an input signal of the encoder, 37 is a maximum H detector that detects the highest frequency position in the horizontal direction that is not 0 of the input signal 36, and 38
is the maximum frequency position in the horizontal direction detected by the maximum H detector 37, 39 is the maximum ■ detector that detects the highest frequency position in the vertical direction that is not 0 of the input signal 36, and 40 is the maximum ■ detector 39 41 is a maximum T detector that detects the highest frequency position in the time direction that is not 0 of the input signal 36, and 42 is the highest frequency position in the time direction detected by the maximum T detector 41. 43 is the highest frequency position of maximum H detector 37 and maximum V detector 3
9 and a delay device that delays the detection by the maximum T detector 41 by the time necessary for detection, 44 is the delay output of the delay device 43, and 45 is the delay output 44 at the highest frequency positions 3B, 40 .
42 is a selector that outputs a selection signal 46 that selects only the area surrounded by the lowest frequency position, and 47 is a selection signal 47.
48 is a coded signal variable-length coded by the variable-length coder 47. Three-dimensional encoding can be performed by an encoder having a simple configuration as described above, and there is no need for complicated switching of encoding means required in conventional high-efficiency encoding devices.

As described above, according to this embodiment, an interpolated signal is divided into blocks into rectangular parallelepipeds, subjected to orthogonal transformation, and then variable-length encoded by an encoder, thereby realizing a simple, high-efficiency encoding device with a high compression rate. can do.

FIG. 12 is a block diagram of a high-efficiency decoding device according to an embodiment of the present invention. In the figure, 8 is an input signal that is a signal encoded by a high-efficiency encoding device, 23 is a decoder that decodes the input signal 8, and 24 is a signal that is decoded by the decoder 23. A decoded signal, 49 is an orthogonal transformer that orthogonally transforms the decoded signal 24, 50 is an orthogonal transform signal that has been orthogonally transformed by the orthogonal transformer 49, and 25 deblocks the orthogonal transform signal 50. 26 is a deblocked signal rearranged by the deblocking device 25; 27 is a thinner that vertically thins out the deblocked signals 26; and 51 is the thinner 27.
This is a signal that has been thinned out.

The operation of the high-efficiency decoding device of this embodiment configured as described above will be described below. The input signal 8 is decoded by the decoder 23, and the orthogonal transformer 49 performs orthogonal transform, which is the inverse transform of the orthogonal transform performed by the high-efficiency encoding device. Next, the orthogonal transformed signal 50 is transformed from a blocked state to a non-interlaced signal by a deblocker 25.

The non-interlaced deblocked signal 26 is decimated by a decimator 27 and converted into an interlaced signal. If the encoding distortion is sufficiently small, the L of the high-efficiency encoding device
The PF removes signal components at frequencies that cause aliasing distortion in the decimator 27, and the high-efficiency decoding device does not require an LPF.

Further, in the embodiment of FIG. 12, the deblocking device 25
The order of the decimator 27 and the decimator 27 may be changed. FIG. 13 shows a block diagram of this embodiment.

In the same figure, 8 is an input signal which is a signal converted into H8 by a high-efficiency encoding device, 23 is a decoder that decodes the input signal 8, and 24 is a signal that is decoded by the decoder 23. 49 is an orthogonal transformer that orthogonally transforms the decoded signal 24, 50 is an orthogonal transform signal that has been orthogonally transformed by the orthogonal transformer 49, and 27 is an orthogonal transform signal that orthogonally transforms the orthogonal transform signal 50 in the vertical direction. 28 is a signal thinned out by the decimator 27, 25 is a deblocking signal that deblocks the decimated signal 28, and 52 is the inverse signal rearranged by the deblocking device 25. Professional.

It is a conversion signal.

In the embodiment configured as described above, the operation is the same as the embodiment shown in FIG. 12 except that the order of the deblocking device 25 and the thinning device 27 is reversed. Since the thinning process is performed before the deblocking process, the input signal of the deblocking device 25 is reduced to 1/2 of the value before the thinning process.
This makes deblocking easier.

As described above, according to this embodiment, the decoder 23, the orthogonal transformer 49, the deblocker 25, and the thinner 8 that decode the signal three-dimensionally encoded by the high-efficiency encoding device.
By converting the three-dimensional signal into an interlaced signal in step 27, a highly efficient three-dimensional encoding decoding device with a simple hardware configuration can be constructed.

FIG. 14 is a block diagram of a high efficiency decoding device in another embodiment of the present invention. In the same figure, 8 is an input signal which is a signal encoded by a high-efficiency encoding device, and 23
is a decoder that decodes the input signal 8, 24 is a decoded signal decoded by the decoder 23, 49 is an orthogonal transformer that orthogonally transforms the decoded signal 24, and 50 is an orthogonal transformer. It is an orthogonal transformed signal that has been orthogonally transformed by a converter 49, and 2
5 is a deblocking signal for deblocking the orthogonal transform signal 50, 26 is a deblocking signal rearranged by the deblocking device 25, and 30 is an LPF for removing high frequency components of the deblocking signal. Yes, 31 is LPF30
27 is a thinner that thins out the filter output in the vertical direction, and 53 is a signal thinned out by the thinner 27. This figure has almost the same configuration as the embodiment shown in FIG. 12, except that an LPF 30 is added.

The operation of the high-efficiency decoding device of this embodiment configured as described above will be described below. The steps from the input signal 8 to the deblocking device 25 are the same as in the embodiment shown in FIG. 12, and will therefore be omitted. When the compression rate due to high-efficiency encoding is large, the decimator 27 is used in the LPF of the high-efficiency encoding device.
Although signal components at frequencies that cause aliasing distortion are removed, there is a possibility that a large amount of coding distortion will occur at frequencies that cause aliasing distortion. Therefore, by installing the LPF 30 immediately before the thinner 37, aliasing distortion can be removed and image quality can be improved.

As described above, according to this embodiment, the decoder 23, orthogonal transformer 49, deblocker 25, and decimator 27 decode the three-dimensional encoded signal by the high-efficiency encoding device. By converting the signal into an interlaced signal, the hardware configuration is simple.
Therefore, by removing the distortion caused by the aliasing 2 of the encoding distortion, the image quality can be improved.

In the above embodiments, the illustrations in FIGS. 2, 3, 9, and 10 are all examples in which two fields F are used in the time direction, but when four or more fields are used, Good too. FIG. 15 shows how four fields of pixel interpolation are performed. Circles filled with diagonal lines indicate existing pixels, and white circles indicate interpolated pixels.

As described in detail, according to the present invention, it is possible to realize a high-efficiency encoding device and a high-efficiency decoding device with a high compression rate and low encoding distortion with a simple hardware configuration, and to put it into practical use. The effect is significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the high-efficiency encoding device of the present invention, FIG. 2 is a conceptual diagram showing the concept of interpolation of the high-efficiency encoding device of the present invention, and FIG. 3 is a block diagram showing an embodiment of the high-efficiency encoding device of the present invention. A conceptual diagram showing an example of blocking of an encoding device, FIG. 4 is a block diagram showing an embodiment of a high-efficiency decoding device of the present invention, and FIG. 5 shows an embodiment of a high-efficiency decoding device of the present invention. Block diagram, 6th
Figure 7 is a block diagram showing an embodiment of the high efficiency decoding device of the present invention, Figure 7 is a block diagram showing an embodiment of the high efficiency encoding device of the present invention, and Figure 8 is a high efficiency code of the present invention. 9 is a conceptual diagram showing the effect of the orthogonal transformer of the encoding device of the present invention; FIG. 10 is a conceptual diagram showing an example of the encoding means; FIG. 11 FIG. 1 is a block diagram showing an example of an encoder of a high-efficiency encoding device of the present invention.
Figure 2 shows an example of a high-efficiency decoding device according to the present invention.
13 is a block diagram showing an embodiment of the high-efficiency decoding device of the present invention, FIG. 14 is a block diagram showing an embodiment of the high-efficiency decoding device of the present invention, and FIG. Invention professional,
FIG. 16 is a block diagram of a conventional high-efficiency encoding device, and FIG. 17 is a block diagram of a conventional high-efficiency decoding device. 15.-Neyama'fake filial piety 1,
/7---Bro Nhui Otsu X Yong, 21.

Claims (1)

[Claims] (1) Pixel interpolation means for generating pixels between adjacent scanning lines of an interlaced image input signal by interpolation or a low-pass filter; blocking means for blocking the pixels generated by the pixel interpolation means into pixel blocks including at least two fields of pixels at the same horizontal and vertical positions as the pixel; and the pixels blocked by the blocking means. A high-efficiency encoding device characterized by comprising encoding means for encoding. (2) a pixel interpolation means for generating pixels between adjacent scan lines of an interlaced image input signal by interpolation or a low-pass filter; a blocking means for blocking the generated pixels into rectangular parallelepiped pixel blocks consisting of several horizontal pixels, several vertical pixels, and at least two fields of pixels at the same horizontal and vertical positions as the pixels; A high-efficiency encoding device comprising: orthogonal transformation means for orthogonally transforming blocked pixels; and encoding means for encoding pixel information orthogonally transformed by the orthogonal transformation means. (3) The high-efficiency encoding device according to claim (2), wherein the block unit is a rectangular parallelepiped consisting of several horizontal pixels, vertical pixels, and one frame. (4) The high-efficiency encoding device according to claim (3), wherein discrete cosine transform is performed in each of the horizontal and vertical directions, and orthogonal transform is performed to take a sum and a difference between fields. (5) a pixel interpolation means for generating pixels between adjacent scan lines of an interlaced image input signal by interpolation or a low-pass filter; blocking means for blocking the generated pixels into pixel blocks including at least two fields of pixels at the same horizontal and vertical positions as the pixels; and encoding for encoding the pixels blocked by the blocking means. a decoding means for decoding a signal encoded by a high-efficiency encoding device characterized in that the input signal is an input signal, and a signal decoded by the decoding means; a deblocking means that rearranges the blocked state into corresponding pixel positions in each field; and a deblocking means that selects only the pixels necessary for the non-interlaced signal from among the pixels rearranged by the deblocking means and converts them to other pixels. A high-efficiency decoding device characterized by comprising a thinning means for removing. (6) A pixel interpolation means that generates pixels between adjacent scanning lines of an interlaced image input signal by interpolation or a low-pass filter; blocking means for blocking pixels into rectangular parallelepiped-shaped pixel blocks consisting of several horizontal pixels, several vertical pixels, and at least two fields at the same horizontal and vertical positions as the pixels; A signal encoded by a high-efficiency encoding device comprising: orthogonal transformation means for orthogonally transforming the converted pixels; and encoding means for encoding pixel information orthogonally transformed by the orthogonal transformation means. as an input signal, a decoding means for decoding the input signal, and an orthogonal transform for performing an orthogonal transform, which is the inverse of the orthogonal transform used in the high-efficiency encoding device, on the signal decoded by the decoding means. means, deblocking means for rearranging the signals orthogonally transformed by the orthogonal transformation means from the blocked state to corresponding pixel positions of each field, and within each pixel rearranged by the deblocking means. A high-efficiency decoding device comprising thinning means for selecting only pixels necessary for a non-interlaced signal and removing other pixels. (7) The high-efficiency decoding device according to claim (6), wherein the block unit is a rectangular parallelepiped consisting of several horizontal pixels, several vertical pixels, and one frame. (8) The high-efficiency decoding device according to claim (7), wherein discrete cosine transform is performed in the horizontal direction and vertical direction, and orthogonal transform is performed between fields to take a sum and a difference. (9) a pixel interpolation means for generating pixels between adjacent scan lines of an interlaced image input signal by interpolation or a low-pass filter; a blocking means for blocking the generated pixels into rectangular parallelepiped pixel blocks consisting of several horizontal pixels, several vertical pixels, and at least two fields of pixels at the same horizontal and vertical positions as the pixels; Encoded by a high-efficiency encoding device characterized by comprising orthogonal transformation means for orthogonally transforming blocked pixels, and encoding means for encoding pixel information orthogonally transformed by the orthogonal transformation means. a decoding means for decoding the input signal using a signal as an input signal; and an orthogonal transform for performing an orthogonal transform, which is an inverse transform of the orthogonal transform used in the high-efficiency encoding device, on the signal decoded by the decoding means. a conversion means; a thinning means for selecting only pixels necessary for a non-interlaced signal and removing other pixels from among the signals orthogonally transformed by the orthogonal transformation means;
A high-efficiency decoding device characterized by comprising a deblocking means for rearranging the signals thinned out by the thinning means from the blocked state to corresponding pixel positions of each field. (10) The high-efficiency decoding device according to claim (9), wherein the block unit is a rectangular parallelepiped consisting of several horizontal pixels, several vertical pixels, and one frame. (11) The high-efficiency decoding device according to claim (10), characterized in that discrete cosine transform is performed in the horizontal direction and vertical direction, and orthogonal transform is performed that takes a sum and a difference between fields. (12) a pixel interpolation means for generating pixels between adjacent scanning lines of an interlaced image input signal by interpolation or a low-pass filter; a blocking means for blocking the generated pixels into rectangular parallelepiped pixel blocks consisting of several horizontal pixels, several vertical pixels, and at least two fields of pixels at the same horizontal and vertical positions as the pixels; Encoded by a high-efficiency encoding device characterized by comprising orthogonal transformation means for orthogonally transforming blocked pixels, and encoding means for encoding pixel information orthogonally transformed by the orthogonal transformation means. Using the signal as an input signal, a decoding means decodes the input signal, and an orthogonal transform, which is an inverse transform of the orthogonal transform used in the high-efficiency encoding device, is performed on the signal decoded by the decoding means. orthogonal transformation means; deblocking means for rearranging the signals orthogonally transformed by the orthogonal transformation means from the blocked state to corresponding pixel positions of each field; and each pixel rearranged by the deblocking means On the other hand, there is a high-frequency component removing means for removing aliasing distortion due to thinning for the non-interlaced signal, and a high-frequency component removing means selects only the pixels necessary for the non-interlaced signal from the low-frequency signal obtained by the high-frequency component removing means. A high-efficiency decoding device characterized by comprising a thinning means for removing pixels. (13) The high-efficiency decoding device according to claim (12), wherein the block unit is a rectangular parallelepiped consisting of several horizontal pixels, several vertical pixels, and one frame. (14) The high-efficiency decoding device according to claim (13), wherein discrete cosine transform is performed in each of the horizontal and vertical directions, and orthogonal transform is performed to take a sum and a difference between fields.