JPH03241790A - Multilayer circuit substrate - Google Patents
Multilayer circuit substrateInfo
- Publication number
- JPH03241790A JPH03241790A JP2037170A JP3717090A JPH03241790A JP H03241790 A JPH03241790 A JP H03241790A JP 2037170 A JP2037170 A JP 2037170A JP 3717090 A JP3717090 A JP 3717090A JP H03241790 A JPH03241790 A JP H03241790A
- Authority
- JP
- Japan
- Prior art keywords
- grounding
- multilayer circuit
- circuit board
- grounding conductive
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title abstract description 7
- 239000000463 material Substances 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 24
- 230000007261 regionalization Effects 0.000 abstract 2
- 239000002184 metal Substances 0.000 description 19
- 230000005855 radiation Effects 0.000 description 8
- 229920000742 Cotton Polymers 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、たとえば半導体メモリカードのような薄型の
電子機器に用いて好適な多層回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer circuit board suitable for use in thin electronic devices such as semiconductor memory cards.
筺体内に電子部品やメモリなどを搭載した多層回路基板
が内蔵された半導体メモリカードのような電子機器にお
いては、外部からの電磁波の侵入による静電気の発生や
内部から外部への不要輻射の放出を防止するために、シ
ールド手段が講じられている。In electronic devices such as semiconductor memory cards that have a built-in multilayer circuit board with electronic components and memory mounted inside the housing, it is necessary to prevent the generation of static electricity due to the intrusion of electromagnetic waves from the outside and the release of unnecessary radiation from the inside to the outside. Shielding measures are taken to prevent this.
従来のかかるシールド方法としては、筐体をプラスチッ
ク製の側壁部材に金属製の銘板を上板、底板として加熱
接着したものとし、これら金属銘板を接地電位に固定す
る方法がとられている。しかし、この方法によっても、
金属銘板間の側壁部材を通る内部からの不要輻射の放出
がかなりあり、充分なシールド効果を得ることができな
かった。As a conventional shielding method, a metal nameplate is heat-bonded to a plastic side wall member of the casing as a top plate and a bottom plate, and these metal nameplates are fixed to a ground potential. However, even with this method,
A considerable amount of unnecessary radiation was emitted from the inside through the side wall member between the metal nameplates, and a sufficient shielding effect could not be obtained.
これに対し、上板となる金属綿材、底板となる金属綿材
の一方もしくは双方の外周を側壁部材側に折り曲げるよ
うにした方法も提案されている。In contrast, a method has also been proposed in which the outer periphery of one or both of the metal cotton material serving as the top plate and the metal cotton material serving as the bottom plate is bent toward the side wall member.
2
これによると、金属銘板の上記折曲部分が筐体の上、底
板間を一部遮蔽することになり、これによって筐体側面
からの不要輻射の放出が低減される。2 According to this, the bent portion of the metal nameplate partially shields the top of the casing and between the bottom plates, thereby reducing the emission of unnecessary radiation from the side surface of the casing.
しかしながら、上記のように金属銘板を折り曲げてシー
ルド効果を増加させる方法では、金属銘板の曲げ加工が
必要となって筐体の構造も複雑となり、コストが上昇す
るし、生産性も低下するという問題があった。However, the above method of increasing the shielding effect by bending the metal nameplate requires bending the metal nameplate, which complicates the structure of the casing, increasing costs and reducing productivity. was there.
また、半導体メモリカードにおいては、商品名、製造会
社名などの文字やパターンが面積が広い金属綿材の表面
に印刷されていた。ところで、金属銘板を折り曲げて筐
体を製造する場合には、この新曲部をプラスチック製の
側壁部材にくい込ませるようにして一体成形するが、こ
の成形は、単に平板状の金属銘板を側壁部材の表面に接
着する場合よりも、充分高い温度で加熱して行なわれる
。Furthermore, in semiconductor memory cards, characters and patterns such as product names and manufacturing company names are printed on the surface of a metal cotton material having a large area. By the way, when manufacturing a casing by bending a metal nameplate, the new curved part is integrally molded by inserting it into the plastic side wall member, but this molding simply involves folding the flat metal nameplate into the side wall member. This is done by heating at a sufficiently higher temperature than when adhering to a surface.
そこで、印刷された金属銘板と側壁部材とを一体成形し
ようとすると、高温加熱のために、印刷が飛んでしまう
ことになり、外観が悪化する。そこで、製造された筐体
の金属銘板上に印刷することも考えられるが、この印刷
は非常に難かしく、コストの上昇を招くことになる。Therefore, if an attempt is made to integrally mold the printed metal nameplate and the side wall member, the printing will be blown off due to high temperature heating, resulting in a poor appearance. Therefore, it is conceivable to print on the metal nameplate of the manufactured casing, but this printing is extremely difficult and would lead to an increase in cost.
本発明の目的は、かかる問題点を解消し、簡単な構成で
もってシールド効果を高めることができるようにした多
層回路基板を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer circuit board that solves these problems and can enhance the shielding effect with a simple structure.
上記目的を達成するために、本発明は、回路パターンが
形成された内層基材が複数個積層されてなる多層回路基
板において、該内層基材夫々の外周に接地用導電パター
ンを設ける。In order to achieve the above object, the present invention provides a multilayer circuit board in which a plurality of inner layer base materials each having a circuit pattern formed thereon are laminated, and a grounding conductive pattern is provided on the outer periphery of each of the inner layer base materials.
多層回路基板の外周では、内層基材の厚みに等しい狭い
間隔で接地用導電パターンが配置されることになり、こ
れらが多層回路基材の面に平行な方向のシールド部材と
して作用する。On the outer periphery of the multilayer circuit board, grounding conductive patterns are arranged at narrow intervals equal to the thickness of the inner layer base material, and these conductive patterns act as a shield member in a direction parallel to the surface of the multilayer circuit base material.
そこで、この多層回路基板をプラスチック製の側壁部材
に金属銘板が接着されてなる筐体内に設けた場合、上記
の接地用導電パターンの配列が筐体の側壁に対するシー
ルド部材として作用し、金属銘板とともに、筐体内部全
体のシールドが達成される。Therefore, when this multilayer circuit board is installed in a case with a metal nameplate adhered to a plastic side wall member, the arrangement of the above-mentioned grounding conductive patterns acts as a shielding member for the side wall of the case, and together with the metal nameplate. , shielding of the entire interior of the casing is achieved.
以下、本発明の実施例を図面によって説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図は本発明による多層回路基板の一実施例を示す斜
視図であって、1a−1dは内層基材の回路パターン形
成面、2a〜2dは接地用導電パターン、3はスルーホ
ール、4a〜4dは切断部である。FIG. 1 is a perspective view showing an embodiment of a multilayer circuit board according to the present invention, in which 1a to 1d are circuit pattern forming surfaces of an inner layer base material, 2a to 2d are conductive patterns for grounding, 3 are through holes, and 4a -4d is a cutting part.
内層基材が4枚積層されているものとして、この実施例
を説明するが、説明を簡明にするために、内層基材につ
いては、回路パターンが形成される表面(回路パターン
形成面)のみを示している。This example will be explained assuming that four inner layer substrates are laminated. However, for the sake of simplicity, only the surface on which the circuit pattern is formed (circuit pattern forming surface) of the inner layer substrate will be explained. It shows.
第1図において、回路パターン形成面1a+1b+lc
、ldには、夫々回路パターン(図示せず)が形成され
ているとともに、夫々の外周に接地用導電パターン2a
、2b、2c、2dが形成されており、回路パターン形
成面1a、lb、lc、Id上の回路パターンによる回
路の接地線となっている。また、各内層基板には、回路
パターン形成面1a+1b+1c+1dの接地用導電パ
ターン2a、2b、2c、2dが形成されている部分か
ら所定個数のスルーホール3が設けられており、これら
スルーホール3内に導電材が充填されて、接地用導電パ
ターン2aと2bが、接地用導電パターン2bと2cが
、接地用導電パターン2cと2dが夫々電気的に接続さ
れている。In FIG. 1, circuit pattern forming surface 1a+1b+lc
, ld have a circuit pattern (not shown) formed thereon, and a grounding conductive pattern 2a on the outer periphery of each.
, 2b, 2c, and 2d are formed, and serve as grounding lines for the circuit formed by the circuit patterns on the circuit pattern forming surfaces 1a, lb, lc, and Id. In addition, a predetermined number of through holes 3 are provided in each inner layer board from the portions of the circuit pattern forming surface 1a+1b+1c+1d where the grounding conductive patterns 2a, 2b, 2c, and 2d are formed. Filled with a conductive material, the grounding conductive patterns 2a and 2b, the grounding conductive patterns 2b and 2c, and the grounding conductive patterns 2c and 2d are electrically connected, respectively.
かかる構成により、この多層回路基板の外周では、内層
基材の厚さdに等しい狭い間隔で接地用導電パターン2
a、2b、2c、2dが配置されることになり、これら
を接地電位に固定することにより、回路パターン形成面
1b、lc、ld上の回路パターンから発生する不要輻
射のうちのこれら回路パターン形成面1b、Ic、Id
に平行な成分の外部への放出を遮断するシールド効果が
得られる。With this configuration, on the outer periphery of this multilayer circuit board, the grounding conductive patterns 2 are arranged at narrow intervals equal to the thickness d of the inner layer base material.
a, 2b, 2c, and 2d are arranged, and by fixing them to the ground potential, these circuit patterns are eliminated from unnecessary radiation generated from the circuit patterns on the circuit pattern forming surfaces 1b, lc, and ld. Surface 1b, Ic, Id
A shielding effect is obtained that blocks the emission of components parallel to the outside.
そこで、かかる多層回路基板を、先の従来例のように、
平板状の金属銘板をプラスチック製の側壁部材に接着し
てなる筐体内に設ける場合でも、これら接地用導電パタ
ーン2a、2b、2c、2dのシールド作用により、側
壁部材からの不要輻射の外6−
部への放出が抑圧されることになる。Therefore, such a multilayer circuit board, like the previous conventional example,
Even when a flat metal nameplate is installed in a housing made by adhering to a plastic side wall member, the shielding effect of these grounding conductive patterns 2a, 2b, 2c, and 2d prevents unnecessary radiation from the side wall member. release to the body will be suppressed.
なお、回路パターン形成面1a上の回路パターンから発
生する不要輻射については、接地用導電パターン2a、
2b、2c、2dによるシールド効果はないが、この多
層回路基板が上記の筐体内に配置された場合、上板と下
板としての金属銘板間の間隔に比べて上板としての金属
綿材と回路パターン形成面1a(シたがって、接地用導
電パターン2a)との間隔が狭くなるので、これによる
シールド効果により、回路パターン形成面1aの回路パ
ターンから発生してプラスチック製の側壁部材を介して
放出される不要輻射はある程度低減される。In addition, regarding unnecessary radiation generated from the circuit pattern on the circuit pattern forming surface 1a, the grounding conductive pattern 2a,
2b, 2c, and 2d have no shielding effect, but when this multilayer circuit board is placed in the above-mentioned case, the gap between the metal cotton material as the top plate and the metal nameplate as the bottom plate is smaller than the distance between the metal nameplates as the top plate and the bottom plate. Since the distance from the circuit pattern forming surface 1a (therefore, the grounding conductive pattern 2a) becomes narrower, due to the shielding effect caused by this, the circuit pattern generated from the circuit pattern forming surface 1a passes through the plastic side wall member. The emitted unnecessary radiation is reduced to some extent.
また、各接地用導電パターン28〜2dはコ字状をなし
ているが、回路パターン形成面1a〜1dの全面にわた
って形成するようにしてもよい。但し、最上の回路パタ
ーン形成面1aの一辺にコネクタパターンを設ける場合
には、この部分以外の周辺に接地用導電パターン2aが
形成されることはいうまでもない。Further, each of the grounding conductive patterns 28 to 2d has a U-shape, but may be formed over the entire surface of the circuit pattern forming surfaces 1a to 1d. However, when a connector pattern is provided on one side of the uppermost circuit pattern forming surface 1a, it goes without saying that the grounding conductive pattern 2a is formed around the area other than this part.
ところで、これら接地用導電パターン28〜2dは、上
記のように、シールド効果をもつものであるが、形状が
コ字状をなしているために、アンテナ効果も生じ、外部
からの電磁波をノイズとして受信するおそれがある。こ
のようにノイズを受信すると、接地用導電パターン28
〜2dでの電位が接地電位から変動し、回路パターン形
成面1a〜ld上の回路によって処理される18号に歪
みが生ずる可能性がある。By the way, these grounding conductive patterns 28 to 2d have a shielding effect as described above, but because of their U-shaped shapes, they also produce an antenna effect, which causes electromagnetic waves from the outside to be treated as noise. There is a risk of receiving it. When noise is received in this way, the grounding conductive pattern 28
The potential at ~2d varies from the ground potential, and distortion may occur in No. 18 processed by the circuits on the circuit pattern forming surfaces 1a~ld.
これを防止するために、コ字状をなす接地用導電パター
ン28〜2d夫々の、たとえば、形状の対称点となる位
置に切断部4a〜4dを設ける。In order to prevent this, cutting portions 4a to 4d are provided in each of the U-shaped grounding conductive patterns 28 to 2d, for example, at positions that are symmetrical points of shape.
これにより、接地用導電パターン2a〜2dは、夫々コ
字状とは異なる形状の2つの部分からなることになり、
アンテナ効果が大幅に低減する。As a result, each of the grounding conductive patterns 2a to 2d consists of two parts each having a shape different from the U-shape.
Antenna effects are significantly reduced.
また、各接地用導電パターン28〜2dに夫々切断部4
8〜4dを設けると、内部で発生した上記の不要輻射は
これら切断部48〜4dを通って外部に放出され、シー
ルド効果が低減する。これを補償するためには、第2図
に示すように、回路パターン形成面la上に適当な抵抗
値の抵抗素子5を設け、これで接地用導電パターン2a
の切断部4aを短絡すればよい。In addition, cutting portions 4 are provided on each of the grounding conductive patterns 28 to 2d.
When 8 to 4d are provided, the above-mentioned unnecessary radiation generated inside is emitted to the outside through these cutting parts 48 to 4d, reducing the shielding effect. In order to compensate for this, as shown in FIG.
What is necessary is to short-circuit the cut portion 4a.
ここで、接地用導電パターン28〜2dに切断部41)
〜4dを設けないことは、これら切断部48〜4dが設
けられる部分の抵抗値がほとんど零ということであって
、シールド効果は最大となるが、アンテナ効果も最大と
なる。また、接地用導電パターン28〜2dに切断部4
a〜4dを設けるということは、これら切断部4a〜4
dが無限大の抵抗値ということであって、アンテナ効果
が最小となるが、切断部でのシールド効果も最小となる
。Here, cut portions 41) on the grounding conductive patterns 28 to 2d.
4d means that the resistance value of the portion where these cutting portions 48 to 4d are provided is almost zero, and the shielding effect is maximized, but the antenna effect is also maximized. In addition, cut portions 4 are provided on the grounding conductive patterns 28 to 2d.
Providing the cutting portions 4a to 4d means that the cutting portions 4a to 4d are
Since d is an infinite resistance value, the antenna effect is minimized, but the shielding effect at the cut portion is also minimized.
そこで、第2図に示すように、接地用導電パターン2a
の切断部4aを抵抗素子5で短絡すると、その抵抗値に
応じて、接地用導電パターン2a〜2dに切断部48〜
4dのみを設けた場合よりも、アンテナ効果とシールド
効果とが増加する。したがって、これらアンテナ効果と
シールド効果との兼ね合いから抵抗素子5の抵抗値を適
宜設定することにより、アンテナ効果を抑えて良好なシ
ールド効果を得ることができる。Therefore, as shown in FIG. 2, a grounding conductive pattern 2a
When the cut portion 4a of
The antenna effect and shielding effect are increased compared to when only 4d is provided. Therefore, by appropriately setting the resistance value of the resistive element 5 in consideration of the balance between the antenna effect and the shielding effect, it is possible to suppress the antenna effect and obtain a good shielding effect.
−
なお、抵抗素子5は接地用導電パターンにのみ設けたが
、他の接地用導電パターンにも設けるようにしてもよい
。- Although the resistive element 5 is provided only in the grounding conductive pattern, it may be provided in other grounding conductive patterns as well.
以上説明したように、本発明によれば、簡単な導電パタ
ーンを内層基板に設けることにより、多層回路基板自体
にシールド効果を持たせることができ、該多層回路基板
を内蔵する筐体のシールド手段を簡略化できるものであ
って、該筐体の設計の自由度が高まって生産性が向上す
るし、筐体の外面での化粧シールの貼付や印刷に対する
制約も大幅に緩和されることになる。As explained above, according to the present invention, by providing a simple conductive pattern on the inner layer board, the multilayer circuit board itself can have a shielding effect, and the shielding means for the casing in which the multilayer circuit board is built. This increases the degree of freedom in designing the casing, improving productivity, and greatly easing restrictions on pasting and printing decorative stickers on the outside of the casing. .
第1図および第2図は夫々本発明による多層回路基板の
実施例を示す構成図である。
■a〜1d・・・回路パターン形成面、2a〜2d・・
・接地用導電パターン、3・・・スルーホール、48〜
4d・・・切断部、5・・・抵抗素子。
10FIGS. 1 and 2 are block diagrams showing embodiments of a multilayer circuit board according to the present invention, respectively. ■a to 1d...Circuit pattern forming surface, 2a to 2d...
・Grounding conductive pattern, 3...Through hole, 48~
4d... Cutting portion, 5... Resistance element. 10
Claims (4)
れてなる多層回路基板において、該内層基材夫々の外周
に接地用導電パターンを設けたことを特徴とする多層回
路基板。(1) A multilayer circuit board formed by laminating a plurality of inner layer base materials provided with circuit patterns, characterized in that a grounding conductive pattern is provided on the outer periphery of each of the inner layer base materials.
にスルーホールを設け、該スルーホールを介して前記内
層基材上の前記接地用導電パターンを互いに電気的に接
続したことを特徴とする多層回路基板。(2) In claim (1), a through hole is provided on the outer periphery of each of the inner layer base materials, and the grounding conductive patterns on the inner layer base materials are electrically connected to each other via the through holes. Multilayer circuit board.
導体パターンは1個以上の切断部を有することを特徴と
する多層回路基板。(3) The multilayer circuit board according to claim (1) or (2), wherein the grounding conductor pattern has one or more cutting portions.
介して短絡したことを特徴とする多層回路基板。(4) The multilayer circuit board according to claim (3), wherein the cut portion is short-circuited via a resistive element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2037170A JPH03241790A (en) | 1990-02-20 | 1990-02-20 | Multilayer circuit substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2037170A JPH03241790A (en) | 1990-02-20 | 1990-02-20 | Multilayer circuit substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03241790A true JPH03241790A (en) | 1991-10-28 |
Family
ID=12490126
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2037170A Pending JPH03241790A (en) | 1990-02-20 | 1990-02-20 | Multilayer circuit substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03241790A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07202477A (en) * | 1993-12-28 | 1995-08-04 | Nec Corp | Printed board for improving electromagnetic wave interference |
US6533097B1 (en) * | 1998-11-13 | 2003-03-18 | Kabushiki Kaisha Nippon Conlux | Sheet material transfer device |
GB2381956A (en) * | 2002-05-27 | 2003-05-14 | Sendo Int Ltd | Suppression of rf interference on audio circuits |
JP2004303812A (en) * | 2003-03-28 | 2004-10-28 | Toshiba Corp | Multilayer circuit board and electromagnetic shield method thereof |
JP2010109248A (en) * | 2008-10-31 | 2010-05-13 | Mitsubishi Electric Corp | Circuit board and electronic equipment |
JP2010135549A (en) * | 2008-12-04 | 2010-06-17 | Mitsubishi Electric Corp | On-board electronic control device |
US20100319982A1 (en) * | 2009-06-23 | 2010-12-23 | Won Woo Cho | Electromagnetic wave shielding substrate |
-
1990
- 1990-02-20 JP JP2037170A patent/JPH03241790A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07202477A (en) * | 1993-12-28 | 1995-08-04 | Nec Corp | Printed board for improving electromagnetic wave interference |
US6533097B1 (en) * | 1998-11-13 | 2003-03-18 | Kabushiki Kaisha Nippon Conlux | Sheet material transfer device |
GB2381956A (en) * | 2002-05-27 | 2003-05-14 | Sendo Int Ltd | Suppression of rf interference on audio circuits |
JP2004303812A (en) * | 2003-03-28 | 2004-10-28 | Toshiba Corp | Multilayer circuit board and electromagnetic shield method thereof |
JP2010109248A (en) * | 2008-10-31 | 2010-05-13 | Mitsubishi Electric Corp | Circuit board and electronic equipment |
JP2010135549A (en) * | 2008-12-04 | 2010-06-17 | Mitsubishi Electric Corp | On-board electronic control device |
US20100319982A1 (en) * | 2009-06-23 | 2010-12-23 | Won Woo Cho | Electromagnetic wave shielding substrate |
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