JPH03238910A - Attenuator - Google Patents

Abstract

PURPOSE:To widen the operating temperature range by constituting the title attenuator with an IC chip integrating two T type attenuators and one FET, a DC bias control circuit and a nonlinear correction circuit. CONSTITUTION:A differential amplifier circuit 7 amplifies a difference between a signal and a reference voltage ES, a bias voltage VP of a gate GP of a FET connecting in parallel with a mirror attenuator 2 is varied to vary a resistance of a FETP connected in parallel so that a voltage V6 at a terminal 6 is the same as the reference voltage ES. Thus, the relation between the resistance of two FETS connected in series and the resistance of the PETP connected in parallel with the two FETS is changed in the relation so that the voltage V6 at the terminal 6 is always constant, and the characteristic impedance of the T type mirror attenuator is constant. The T type FET of the signal attenuator is constituted in a same IC chip of the mirror attenuator and since a gate of the series FETS is connected in common respectively to the gate of the parallel FET, each internal resistor, that is, the attenuator characteristic is the same for both the attenuators. Thus, operating temperature range is widened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an attenuator, and more particularly to an attenuator using an integrated circuit of field effect transistors.

Attenuators are widely applied in communication, measurement, and radio wave application fields, and in these cases, it is particularly required that the external control voltage and the amount of attenuation be linear.

[Conventional technology]

Conventionally, this type of 7-tube tenator consists of a PIN diode and a function generator.

[Problem to be solved by the invention]

In the conventional method described above, since the PIN diode is composed of a single unit, it is difficult to control accurately due to variations in characteristics of each PIN diode.

Further, a function generator also has disadvantages in that a circuit using a diode is complicated to adjust and has a narrow operating temperature range.

[Means for Solving the Problems] The 7-tensioner of the present invention includes (A) two FETs inserted in series between an input signal end and an output signal end, and a connection point between the FETs and a ground potential point. (B) a signal attenuator configured in a T-shape with a parallel FET inserted in the input terminal; (C) The output signal of the mirror attenuator is input to one input terminal, and a constant voltage is applied to the other input terminal. a DC bias control circuit having a first differential amplifier circuit that applies a reference voltage divided by and whose output terminal is connected to the gate of the parallel FET; (2) inputting a control voltage to one input terminal; The other input terminal is supplied with a divided voltage of a series circuit of a characteristic impedance and a feedback FET inserted between an external power supply terminal and a ground potential point, and a differential output voltage is commonly applied to the gates of the feedback FET and the parallel FET. a nonlinearity correction circuit having a second differential amplifier circuit that supplies the nonlinearity.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, 1 is a signal attenuator, 2 is a mirror attenuator, 3 is a DC bias control circuit, and 4 is a nonlinearity correction circuit.

The terminal 5 of the T-type mirror attenuator 't12 is terminated with 50 ohms.

The other terminal 6 is connected to the input of the control circuit 3.

The reference voltage Es of the first differential amplifier circuit 7 in the control circuit 3 is composed of a resistor R and a characteristic impedance of 50 ohms.

Now, the two Fs connected in series of mirror attenuator 2
When some bias voltage v3 is applied to the ET gate (Gs), the voltage V6 at the terminal 6 changes.

After amplifying the difference between the differential amplifier 7 and the reference voltage E, the differential amplifier 7 changes the gate GP bias voltage V of the parallel-connected FETs in the monitor attenuator 2 to increase the voltage at the terminal 6.
is connected in parallel so that it is the same as the reference voltage E? ”
Change the resistance of the FE T p.

Therefore, the relationship between the resistance of the two FETs connected in series and the resistance of FETP connected in parallel is
Since the voltage (2) always changes in a constant manner, the characteristic impedance of the T-type mirror attenuator is constant at 50Ω.

The T-type FET of the signal attenuator is composed of the same IC chip as the mirror attenuator, and the gates of the series FET and the gates of the parallel FET are connected in common, so each internal resistance, that is, the attenuator characteristics are the same for both attenuators. .

On the other hand, external control voltage ■. is applied to the differential amplifier circuit 9 from the terminal 8 and becomes a reference voltage.

The current of the feedback FET 10 is controlled by the output of the differential amplifier circuit 9, and the drain voltage of the feedback FET 10 becomes V.

Current flow through FET10 and resistance value R1 of FET10
, the relationship with the supply voltage DD of FETIO is as shown in equation (1).

On the other hand, when the equal deflection portion resistances of both attenuators 1 and 2 are expressed as shown in FIG. 2, the series and parallel resistances Rs, R
p is determined by the attenuation K and the characteristic impedance R0,
It is expressed as Equation 2) and Equation (3).

From equations (1)2 to (3) above, if Ro ''Ro is set, the attenuation amount is expressed by equation (A).

Therefore, if ■DD is a constant voltage, the amount of attenuation is the external control voltage■. is inversely proportional to.

Therefore, the FET signal attenuator 1 has the same equivalent circuit as the mirror attenuator 2, so RFIN and RFO
Always automatically shows a predetermined attenuation characteristic for the UT.

〔Effect of the invention] As explained above, the present invention provides two sets of T-shaped arrays.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of an attenuator. 1...Signal attenuator, 2...Mirror attenuator, 3...DC bias control circuit, 4...Group nonlinearity correction circuit, 5... 5oΩ
Termination terminal, 6... Control circuit input terminal, 7...
...First differential amplifier circuit, 8...External control input terminal, 9...Second differential amplifier circuit, 10.
...Return FET.

Claims (1)

[Claims] (A) Two series FETs inserted between the input signal end and the output signal end, and a parallel FET inserted between the connection point of the FETs and the ground potential point, forming a T-type (B) A characteristic impedance is connected to the input terminal, and the signal attenuator is formed on the same IC chip with the same configuration as the signal attenuator,
and a mirror attenuator connected in common to the gate of the series FET and the gate of the parallel FET, respectively; a DC bias control circuit that applies a reference voltage obtained by dividing a constant voltage by a resistor and a characteristic impedance, and has a first differential amplifier circuit whose output terminal is connected to the gate of the parallel FET; (D) one input; A control voltage is input to one end, and a divided voltage of a series circuit of a characteristic impedance and a feedback FET inserted between an external power supply end and a ground potential point is supplied to the other input end.
An attenuator comprising: a nonlinearity correction circuit having a second differential amplifier circuit that commonly supplies a differential output voltage to the gates of the feedback FET and the parallel FET.