JPH03238826A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a base resistance to be reduced and high-frequency characteristics of a bipolar transistor to be improved by setting the width of a polysilicon layer to be equal to or less than that of an emitter layer and by enclosing a side surface of the polysilicon layer for forming an insulation film for insulating between a base and an emitter. CONSTITUTION:The width of a polysilicon layer 32 is reduced to that of an emitter layer 31 or less and the side surface of the polysilicon layer 32 is coated with an insulation film, thus enabling insulation to be achieved between a base and an emitter only with this insulation film. Thus, an oxide film for an etching stopper at a lower side of a polysilicon layer 32 is not needed and factors for increasing the base resistance can be eliminated, thereby enabling the base resistance to be reduced and high-frequency characteristics of a bipolar transistor to be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar transistor applied to LSI etc. and a method for manufacturing the same.

[Conventional technology]

FIG. 7 is a cross-sectional view of a conventional bipolar transistor.
Electron Devices Meetlng)1
988. It has the same configuration as that described in Fig. 1(a) on page 740.

As shown in FIG. 7, a floating collector layer 2 is formed on a semiconductor substrate 1, an epitaxial layer 3 is formed on this collector layer 2, and an epitaxial layer 3. A trench isolation region 4 is formed from the collector layer 2 to the upper part of the substrate 1 so as to surround a predetermined region.

Then, an oxide film 5 is formed on the side surface of the trench isolation region 4, a channel cut layer 6 is formed in the substrate 1 below the trench isolation region 4, and a thick oxide film is selectively formed on the surface of the epitaxial layer 3. 7 is formed, a collector connection layer 8 reaching the floating collector layer 2 is formed on the epitaxial layer 3 exposed in the opening of the oxide film 7, and an intrinsic base is formed on the epitaxial layer 3 exposed in the other opening of the oxide film 7. A layer 9 and an external base layer 10 located outside this intrinsic base layer 9 are formed.

Further, a thin oxide film 11 is formed over a portion of the intrinsic base layer 9 and the extrinsic base layer 10.
An opening is formed on the upper side of the intrinsic base layer 10, and a polysilicon layer 1 containing emitter impurities is formed on the oxide film 11.
2 is formed, an emitter layer 13 is formed on the surface of the intrinsic base layer 9 in the opening of the oxide film 11 by impurity diffusion from the polysilicon layer 12 by heat treatment, and a silicide layer 14 is formed on the polysilicon layer 12. , an oxide film 15 is formed on the silicide layer 14, and a polysilicon layer 13.
An oxide film 16 is formed covering the side surfaces of the silicide layer 14 and the oxide film 15.

Further, a collector electrode 17 is formed on the oxide film 7 in contact with the collector connection layer 8, and a base electrode 18 is formed on the oxide film 15, 16 and in contact with the external base region 10. , the polysilicon layer 12 and the silicide layer 14 constitute a part of the emitter electrode.

By the way, in the bipolar transistor shown in FIG. 7, a polysilicon layer 12 is formed on the oxide film 11 in which an opening is formed, and when etching the polysilicon layer 12 into a predetermined shape, the silicide on the polysilicon layer 12 is first etched. layer 14
is patterned into a predetermined shape, and this silicide layer 14
The polysilicon layer 12 is anisotropically etched using the oxide film 11 as an etching mask and the oxide film 11 as an etching stopper.

Further, when etching the oxide film 16, the thin oxide film 11 formed on the entire surface of the external base layer 10 is simultaneously etched in a self-aligned manner to expose the peripheral portion of the external base layer 10. 10 and base electrode 1
It allows connection with 8.

(Problems to be Solved by the Invention) In the conventional case, as described above, since the oxide film 11 is used as an etching stopper for the polysilicon layer 12, the lower surface and side surfaces of the polysilicon layer 12 are covered with the oxide films 11 and 12. As a result, insulation between the base and emitter is ensured by these two participating films 11 and 12, and as a result, a point A at the end of the contact surface between the external base layer 10 and the base electrode 18 and the emitter-base junction interface are formed. There is a problem in that the distance between the end point B and the end point B becomes long due to the structure, and as a result, the base resistance becomes large, leading to a deterioration in the high frequency characteristics of the bipolar transistor.

Furthermore, since two oxide films 11.12 are formed around the polysilicon layer 12 due to the structure, these oxide films 11.1
There is also the problem that the process becomes complicated because patterning of the oxide film 11 and the formation of openings in the oxide film 11 are required.

This invention was made to solve the above problems, and aims to reduce the base resistance, improve the high frequency characteristics of bipolar transistors, and simplify the manufacturing process. shall be.

[Means to solve the problem]

A bipolar transistor according to the present invention includes an epitaxial layer formed on a floating collector layer on a semiconductor substrate, a base layer formed on the epitaxial layer, and a polysilicon layer for an emitter electrode formed on the base layer. In a bipolar transistor in which an emitter/vine layer is formed in the base layer by impurity diffusion, the width of the polysilicon layer is made equal to or less than the width of the emitter layer, and the side surface of the polysilicon layer is covered to form a layer between the base and emitter. It is characterized by the formation of an insulating film for insulation.

In addition, as a manufacturing method thereof, a base layer is formed in an epitaxial layer formed on a floating collector layer on a semiconductor substrate and separated into elements, and impurities are diffused from a polysilicon layer for an emitter electrode on the base layer. In a method of manufacturing a bipolar transistor in which an emitter layer is formed in a base layer, a step of introducing base impurities into a base formation region of the epitaxial layer;
forming a non-doped polysilicon layer on the surface of the epitaxial layer; forming a doped polysilicon layer containing emitter impurities on the non-doped polysilicon layer; and an emitter formation region on the doped polysilicon layer. forming a conductive mask layer on the upper side; using the conductive mask layer as an etching mask, anisotropically etching the doped polysilicon layer until the non-doped polysilicon layer is exposed; a step of leaving the doped polysilicon film; a step of removing the remaining non-doped polysilicon film other than the lower side of the doped polysilicon film; and a step of removing the side surfaces of both the polysilicon films and the side surface of the conductive mask film. a step of enclosing and forming an insulating film for insulating between the base and emitter;
forming a base layer in the base formation region by diffusing the base impurity through heat treatment; and forming a base layer in the emitter formation region by diffusing the emitter impurity in the doped polysilicon layer through the non-doped polysilicon layer through heat treatment. It is effective to include a step of forming an emitter layer.

[Function] In this invention, the width of the polysilicon layer is made equal to or less than the width of the emitter layer, and the sides of the polysilicon layer are covered with an insulating film, so that the insulation between the base and emitter is maintained only by the insulating film, which is different from the conventional method. This eliminates the need for an oxide film for an etching stopper under the polysilicon layer, eliminates a factor that increases base resistance, and improves high frequency characteristics by reducing base resistance.

In addition, we have a double polysilicon structure consisting of a non-doped polysilicon layer and a doped polysilicon layer, and the non-doped polysilicon layer is etched and sown to anisotropically sotch the doped polysilicon layer. The layer can be etched with good control, and there is no oxide film located below the polysilicon layer as in the conventional method.
Due to impurity diffusion from the doped polysilicon layer,
By forming the vine layer, the width of the final polysilicon layer becomes less than the width of the emitter layer, and the base layer is formed only by the insulating film that covers the sides of the polysilicon layer.
It becomes possible to maintain insulation between emitters.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of a bipolar transistor and a method for manufacturing the same according to the present invention.

As shown in FIG. 1, a floating collector layer 20 is formed on a semiconductor substrate 19, an epitaxial layer 21 is formed on this collector layer 20, and an epitaxial layer 21 is formed on the collector layer 20.
1. A trench isolation groove 22 is formed from the collector layer 20 to the upper part of the substrate 19 so as to surround a predetermined region.

Then, an isolation oxide film 23 is formed in the trench isolation groove 22, a channel cut layer 24 is formed in the substrate 19 below the isolation oxide film 23, a surface oxide film 25 is formed on the surface of the epitaxial layer 21, In the epitaxial layer 21 exposed in the contact hole 26 of this surface oxide film 25,
A collector connection layer 27 reaching the floating collector layer 20 is formed, and an intrinsic base layer 2 is formed on the epitaxial layer 21 exposed in the large opening of the surface oxide film 25.
8 and two external base layers located outside this intrinsic base layer 28, and a base layer 30 is formed,
An emitter layer 31 is formed in the intrinsic base layer 28 .

Further, a polysilicon layer 32 is located on the emitter layer 31, a silicide layer 33 is formed as a conductive mask layer on this polysilicon layer 32, and covers the side surfaces of the polysilicon 32 and the silicide layer 33 to form a base emitter. An enveloping oxide film 34a is formed as an insulating film between the layers, and a protective oxide film 34b is formed on the silicide layer 33 and the silicide layer on the surface of the external base layer 29, which will be described later. Thin silicide films 35 and 36 are formed on the exposed surface in the hole 26 and on the surfaces of the two external base layers, respectively, and a contact hole 37 for a base contact is formed on the silicide film 36,
A collector electrode 38 is formed on the silicide film 35, and three base electrodes are formed on the silicide film 36.

By the way, FIG. 2 is a diagram showing the planar layout of the bipolar transistor shown in FIG. 1, and x-x' in FIG.
The cross section in FIG. 1 corresponds to FIG. 1, and in FIG. 2, a silicide layer 33 on a polysilicon layer 32 is connected to an emitter electrode 41 via a contact hole 40.

Next, the manufacturing process will be explained in detail with reference to FIG. 3.

First, as shown in FIG. 3(a), a floating collector layer 20 is formed on a substrate 19, and as shown in FIG. 3(b), an epitaxial layer 21 is formed on the floating collector layer 20. At this time, the surface of the floating collector layer 20 is lifted due to high heat treatment during the formation of the epitaxial layer 21, and the thickness of the floating collector layer 20 is increased.

Then, as shown in FIG. 3(e), trench isolation grooves 22 are formed by etching until they reach the substrate 19, and then, as shown in FIG. 3(d), other elements such as adjacent transistors are etched. In order to ensure separation from the channel cut layer 24, impurities are introduced into the substrate 19 below the groove 22 at a high concentration by ion implantation or the like, as shown in FIG. Then, an isolation oxide film 23 is formed in the trench 22.
is embedded.

Next, as shown in FIG. 3 (), after a surface oxide film 25 is formed on the surface of the epitaxial layer 21,
As shown in g), the surface oxide film 25 of the collector forming region, emitter, and base region is removed to form a contact hole 26 and an opening, respectively, and a floating collector layer 20 is formed in the epitaxial layer 21 exposed in the contact hole 26. A collector connection layer 27 is formed by introducing impurities of the same conductivity type at a high concentration.

Hereinafter, the processing process within the area surrounded by the broken line in FIG. 3(g) will be described with reference to FIG. 4.

As shown in FIG. 4(a), an ion beam 42 is irradiated into the opening of the surface oxide film 25 in the emitter and base forming regions, and an intrinsic base impurity 43 is introduced.
As shown in b), a non-doped polysilicon layer 44 is formed on the entire surface, and as shown in FIG. , as shown in FIG. 4D, the ion beam 47 hits the doped polysilicon layer
The emitter impurity 46 is further introduced by the irradiation.

At this time, the step shown in FIG. 4(d) is a step of introducing an emitter impurity 46 which will become a diffusion source during the heat treatment of the emitter, which will be described later. When forming the
) is not necessarily necessary. however,
From the viewpoint of controllability of the amount of impurity introduced, it is preferable to control the amount of impurity introduced by introducing impurities using an ion beam, which has good controllability, since the controllability is poor if the impurity is diffused only in the doped polysilicon layer 45.

Then, as shown in FIG. 4(e), a heat-resistant silicide layer 33 is formed on the entire surface, and as shown in FIG. After pattern etching, the doped polysilicon layer 45 is anisotropically etched using the silicide layer 33 as a mask until the non-doped polysilicon layer 44 is exposed, as shown in FIG.

At this time, since the emitter impurity 46 contained in the doped polysilicon layer 45 is decomposed and released by etching the doped polysilicon layer 45, the emitter impurity released by gas analysis or plasma spectroscopic analysis is 46, it is detected that the non-doped polysilicon layer 44 is exposed due to a drastic decrease in the detected amount, and the anisotropic etching of the doped polysilicon layer 45 is stopped after a slight over-etching. g)
The non-doped polysilicon layer 44 is exposed as shown in FIG.
In addition, the doped polysilicon layer 45 remains under the silicide layer 33.

By the way, in general, damage caused by anisotropic etching of polysilicon tends to have adverse effects such as surface roughness on the surface of silicon film and silicon substrate because they are of the same silicon type, but in this case, non-doped polysilicon Layer 44 is interposed between doped polysilicon layer 45 and epitaxial layer 21 to serve to absorb damage to epitaxial layer 21 .

Furthermore, the detection of the end point of etching of the doped polysilicon layer 45 is as described above, and is a technology that is fully possible with current semiconductor process technology, and it is possible to detect the end point of etching of the doped polysilicon layer 45, and it is possible to detect the end point of etching of the doped polysilicon layer 45. Accordingly, the doped polysilicon layer 45 can be processed with good control.

Next, as shown in FIG. 4(h), the non-doped polysilicon layer 44 is removed by a method such as wet etching that does not leave any damage on the surface of the epitaxial layer 21, and the epitaxial layer 21 is completely exposed. As shown in (f) of the same figure, an oxide film 34 is formed on the entire surface, and as shown in (j) of the same figure, an oxide film 34 is formed on the entire surface,
As shown in the same figure (j), the oxide film 34 is left only on the side surfaces of the silicide layer 33, the doped polysilicon layer 45, and the non-doped polysilicon layer 44 by anisotropic etching, and the contact opening in the base formation region is The ion beam 48 is etched until a portion is formed, and a covering oxide M 34 a is formed, and then, as shown in FIG. The external base layer impurity 49 is introduced to lower the base resistance and increase the speed of the transistor.

Furthermore, as shown in FIG. 4(f), heat treatment is performed to activate the intrinsic base layer 28 and the two external base layers to form the base layer 30, and to form an emitter layer in the doped polysilicon layer 45. The impurity 46 and the emitter impurity 46 introduced by ion implantation are diffused into the epitaxial layer 21 through the non-doped polysilicon layer 44 to form the emitter layer 31, and the non-doped polysilicon layer 44
The doped polysilicon layer 45 is made uniform by heat treatment and becomes a polysilicon layer 32 containing a certain amount of impurity, and then a contact opening in the base forming region is opened to further reduce the base resistance. The same figure (1
As shown in 1), after the silicide film 36 is formed, a protective oxide film 34b for surface protection is formed on the silicide layer 36, as shown in FIG. Film 34b is selectively removed to form contact holes 37, and each contact hole 26.
Each electrode 38, 39 is formed on the substrate 37, and a series of manufacturing steps of the bipolar transistor is completed.

By the way, in FIGS. 1 to 4, the polysilicon layer 3
2 is heavily emphasized, but in reality it is the conventional 7th
The thickness is approximately the same as that of the polysilicon film shown in the figure, and the same applies to the cases of FIGS. 5 and 6, which will be described later.

Therefore, since the width of the polysilicon layer 32 can be made smaller than the width of the emitter layer 31, by covering the side surfaces of the polysilicon layer 32 with the enveloping oxide film 34a, etching of the lower side of the polysilicon layer as in the conventional method is avoided. The oxide film for the stopper is not required, and the insulation between the base, emitter and base can be maintained only by the enveloping oxide film 34a, and the factors that increase the base resistance can be eliminated, and by reducing the base resistance, high frequency It is possible to improve the characteristics.

Furthermore, since the silicide film 36 was formed in the contact opening in the base formation region, as shown in FIG.
The distance between point C at the emitter side end of the silicide film 36, which corresponds to point A in the figure, and the dot at the end of the emitter-base junction interface is determined from the distance between points A and B in FIG. It is also possible to significantly reduce the base resistance, making it possible to further reduce the base resistance.

Furthermore, since a double polysilicon structure is formed of a non-doped polysilicon layer 44 and a doped polysilicon layer 45, and the doped polysilicon layer 45 is anisotropically etched using the non-doped polysilicon layer 44 as an etching stopper, the doped polysilicon layer 45 is 45 can be etched with good controllability, and the emitter layer 31 can be formed by diffusing the emitter impurity 46 from the doped polysilicon layer 45 without placing an oxide film under the polysilicon layer as in the conventional method. This makes it possible to make the final width of the polysilicon layer 32 less than or equal to the width of the emitter layer 31, and the enveloping oxide film 3 that covers the side surfaces of the polysilicon layer 32
4a alone makes it possible to maintain insulation between the base and emitter.

Furthermore, etching the doped polysilicon layer 45,
Since the etching of the non-doped polysilicon layer 44 is divided into two stages and the base and emitter layers 30 and 31 are formed in a self-aligned manner, the base 2 emitter layers 30 and 31 can be formed with good controllability, suppressing variations in device characteristics. At the same time, the process can be simplified compared to conventional methods.
Furthermore, since the process is similar to that of CMO3 except for the step of forming the gate oxide film, it can be applied to Bi-CMO3 devices.

In addition, as another example, as shown in FIG.
Even if the contact portions between the base electrode and the three base electrodes are made into one, the present invention can be practiced and the same effect as the above-mentioned embodiment can be obtained.

Moreover, instead of trench element isolation, as shown in FIG.
Needless to say, the isolation oxide film 50 may be formed by OCOS element isolation.

Furthermore, it goes without saying that the present invention can be applied to any type of bipolar transistor, npn type lpnp type.

Further, the conductive mask layer is not limited to the silicide layer 33 described above, but also has heat resistance and conductivity, and the doped polysilicon layer 4
Any material may be used as long as it serves as an etching mask in step 5 and also functions as a barrier metal to prevent aluminum from entering the polysilicon layer 32 at the emitter contact portion, and TiN, TiW, or the like may be used.

Further, in place of the enveloping oxide film 34a, another insulating film may be formed for base-emitter insulation.

〔Effect of the invention〕

As described above, according to the present invention, the width of the polysilicon layer is made equal to or less than the width of the emitter layer, the side surfaces of the polysilicon layer are covered with an insulating film, and the insulating film 6 provides insulation between the base and the emitter. This eliminates the need for an oxide film for an etching stopper under the polysilicon layer, which is required in the past, and eliminates the cause of increased base resistance, reducing base resistance and improving the high-frequency characteristics of bipolar transistors. In addition, since the doped polysilicon layer is anisotropically etched using the non-doped polysilicon layer as an etching stopper, the doped The polysilicon layer can be etched with good control, and the width of the final polysilicon layer after the emitter layer formation step by diffusion of impurities from the doped polysilicon layer can be made smaller than the width of the emitter layer. A bipolar device with a structure that allows insulation between the base and emitter to be maintained only by the insulating film that covers the sides of the polysilicon layer, and eliminates the insulating film below the polysilicon layer, which was a factor in lowering the base resistance in the past. You can get a transistor.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an example of the bipolar transistor and its manufacturing method of the present invention, FIG. 2 is a plan view different from FIG. 1, and FIG. 3 is a cross-sectional view showing the manufacturing process up to the middle of FIG. 1. ,
FIG. 4 is a sectional view showing the manufacturing process from the middle of a part of FIG. 1, and FIGS. 5 and 6 are sectional views of other embodiments, respectively.
FIG. 7 is a cross-sectional view of a conventional bipolar transistor. In the figure, 1 is a semiconductor substrate, 20 is a floating collector layer, 21 is an epitaxial layer, 30 is a base layer, 31 is an emitter layer, 32 is a polysilicon layer, 33 is a silicide layer, 34a is an encapsulating oxide film, and 43 is a 44 is a non-doped polysilicon layer, 45 is a doped polysilicon layer, 46 is an emitter impurity, and 49 is an extrinsic base impurity. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) An epitaxial layer is formed on a floating collector layer on a semiconductor substrate, a base layer is formed on the epitaxial layer, and an impurity is diffused from a polysilicon layer for an emitter electrode formed on the base layer to form the base. In a bipolar transistor in which an emitter layer is formed in a bipolar transistor, the width of the polysilicon layer is made equal to or less than the width of the emitter layer, and an insulating film for insulating between the base and emitter is formed by covering the side surface of the polysilicon layer. A bipolar transistor characterized by: (2) A base layer is formed in an epitaxial layer formed on a floating collector layer on a semiconductor substrate and separated into elements, and impurities are diffused into the base layer from a polysilicon layer for an emitter electrode on the base layer. A method for manufacturing a bipolar transistor in which an emitter layer is formed, including the steps of: introducing a base impurity into a base formation region of the epitaxial layer; forming a non-doped polysilicon layer on a surface of the epitaxial layer; and the non-doped polysilicon layer. forming a doped polysilicon layer containing emitter impurities on the doped polysilicon layer; forming a conductive mask layer above the emitter formation region on the doped polysilicon layer; and etching the conductive mask layer with an etching mask. a step of anisotropically etching the doped polysilicon layer until the non-doped polysilicon layer is exposed, leaving the doped polysilicon film under the conductive mask layer; a step of removing the non-doped polysilicon film other than the lower side; a step of forming an insulating film for insulating between the base and emitter by covering the side surfaces of both the polysilicon films and the side surface of the conductive mask film; forming a base layer in the base forming region by diffusing the base impurity through heat treatment; and forming a base layer in the emitter forming region by diffusing the emitter impurity in the doped polysilicon layer through the non-doped polysilicon layer by heat treatment. 1. A method of manufacturing a bipolar transistor, comprising the step of forming an emitter layer.