JPH03238808A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03238808A JPH03238808A JP2034744A JP3474490A JPH03238808A JP H03238808 A JPH03238808 A JP H03238808A JP 2034744 A JP2034744 A JP 2034744A JP 3474490 A JP3474490 A JP 3474490A JP H03238808 A JPH03238808 A JP H03238808A
- Authority
- JP
- Japan
- Prior art keywords
- devices
- exposure
- custom
- patterned
- sections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 10
- 230000007261 regionalization Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract description 4
- 238000001459 lithography Methods 0.000 abstract description 3
- 230000010485 coping Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70458—Mix-and-match, i.e. multiple exposures of the same area using a similar type of exposure apparatus, e.g. multiple exposures using a UV apparatus
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Electron Beam Exposure (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は半導体及び表示体装置等の製造方法に関して為
されたものであり複数の露光装置描画装置を同一層のパ
ターン形成工程に用いることにより特性の向上及び多品
種化に対応可能ならしめるものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention has been made regarding a manufacturing method for semiconductors, display devices, etc., and is achieved by using a plurality of exposure devices and drawing devices in the pattern forming process of the same layer. This makes it possible to improve characteristics and respond to diversification.
[従来の技術]
従来半導体装置のパターン形成工程に於いてはマスク、
レチクルなどを用いる露光装置によるのが一般的であり
電子ビーム等を用いる描画装置はスルーブツトが低いこ
ともあり極微細パターン及び極少量のデバイスの試作に
用いられており両者の技術が同時に用いられることはな
かった。[Prior art] In the pattern forming process of conventional semiconductor devices, masks,
It is common to use an exposure device that uses a reticle, etc., and a writing device that uses an electron beam, etc. has a low throughput, so it is used for prototyping ultra-fine patterns and devices in a very small amount, and both techniques are used at the same time. There was no.
又、従来の露光装置と描画装置がそれぞれ感光域の異な
るレジストを使用していたこともあり同一層での重複使
用は非現実的であった。Further, since conventional exposure equipment and drawing equipment each use resists with different photosensitive areas, it is impractical to use the same layer overlappingly.
[発明が解決しようとする課題]
半導体装置及び表示体装置などの利用範囲が拡大するの
に伴い特性の向上、デバイスのカスタム化の要求が高ま
り素子寸法の微細化(パターン全面が微細化するとは限
らない)及び小ロツト化が進み従来の露光装置を用いた
場合は解像度の限界及び装置効率の低下が甚だしいがE
B描画装置を使用した場合はウェハー全面を描画するた
めにスループットが低いことが問題であった。[Problems to be solved by the invention] As the scope of use of semiconductor devices and display devices expands, demands for improved characteristics and customization of devices increase, and element dimensions become finer (the entire pattern becomes finer). ) and smaller lots, and when conventional exposure equipment is used, there are limits to resolution and a significant drop in equipment efficiency.
When the B lithography system was used, the problem was that the throughput was low because the entire wafer surface was scribed.
[課題を解決するための手段]
本発明は上記問題点を解決するために為されたものであ
り同一レジストに感光する光源を有する露光装置及び描
画装置を用い同一層を分割露光及び描画することによっ
てスループットを低下させずに特性の向上、デバイスの
カスタム化を計ったものであり以下に実施例に従い本発
明の詳細について述べる。[Means for Solving the Problems] The present invention has been made to solve the above-mentioned problems, and involves dividing exposure and drawing of the same layer using an exposure device and a drawing device having light sources that are sensitive to the same resist. The present invention is intended to improve characteristics and customize the device without reducing throughput.The details of the present invention will be described below with reference to Examples.
[実施例コ
(実施例1)
第1図に本発明実施例1による製造方法を用いた半導体
装置のチップレイアウト図を示す。[Example 1 (Example 1)] FIG. 1 shows a chip layout diagram of a semiconductor device using the manufacturing method according to Example 1 of the present invention.
図中、2にはチップのカスタム部分であるマスクROM
スタンダードセル部分がある。In the figure, 2 shows a mask ROM which is a custom part of the chip.
There is a standard cell part.
半導体装置の設計に当たってチップ内を各機能ごとにセ
ル化し標準パターン部分(1=3#4#5)とカスタマ
イズ化する部分(2)に分け、パターン作成工程におい
ては標準パターン部分は1線を用いたステッパーによる
露光方式を用い高速にパターニングした。When designing a semiconductor device, the inside of the chip is divided into cells for each function and divided into a standard pattern part (1=3#4#5) and a customized part (2), and in the pattern creation process, one line is used for the standard pattern part. High-speed patterning was performed using an exposure method using a stepper.
さらに同一レジスト層を用いカスタマイズ部分(2)を
Arレーザーの高調波(3638X)を用いたレーザー
描画装置を用いて描画を行った。Furthermore, using the same resist layer, a customized portion (2) was drawn using a laser drawing device using harmonics (3638X) of an Ar laser.
本実施例においてはレジストとして1線対応のポジレジ
ストを使用した。In this example, a positive resist corresponding to one line was used as the resist.
3638′にのArレーザー光はi線対応のポジレジス
トを良く感光するため比較的高速でパターニングするこ
とができた。Since the Ar laser beam of 3638' irradiates well the i-line compatible positive resist, it was possible to pattern it at a relatively high speed.
ステッパーによるパターニング部分と描画装置によるパ
ターニング部分とのアライメントについては下地基板の
アライメントパターンを用いても良く又はステッパーに
よる露光後、現像を行いそのパターンを用いてアライメ
ントを行い多重露光を行っても可能であった。For alignment between the patterned part by the stepper and the patterned part by the drawing device, it is possible to use the alignment pattern of the underlying substrate, or it is possible to perform multiple exposure by developing after exposure by the stepper and aligning using that pattern. there were.
(実施例2)
第2図に本発明実施例2による製造方法を用いて製作し
た液晶表示体装置の電極パターン外形図を示す。(Example 2) FIG. 2 shows an outline diagram of an electrode pattern of a liquid crystal display device manufactured using the manufacturing method according to Example 2 of the present invention.
本実施例においては(7)で示された画素制御用トラン
ジスタ部及び周辺回路部をg、i線供用レジストを用い
一括転写露光装置でパターニングした後各画素分割の為
のパターニング部(8)をArレーザー描画装置を用い
て描画した。In this example, the pixel control transistor section and the peripheral circuit section shown in (7) are patterned using a batch transfer exposure device using a resist for g and i lines, and then a patterning section (8) for dividing each pixel is formed. Drawing was performed using an Ar laser drawing device.
液晶表示体においてはパネル面積の大型化と共にフント
ラスト向上のために各画素間のギャップは狭くなる傾向
にある為大面積用露光装置が必要であると共に露光パタ
ーンは微細化の度合いを強めている。In liquid crystal displays, as the panel area becomes larger, the gap between each pixel tends to narrow in order to improve the film stability, so large-area exposure equipment is required, and exposure patterns are becoming increasingly finer. .
本実施例では周辺回路部及び制御用トランジスタ部ば1
0μ前後であるのに対して画素分割の為のパターニング
は2μ程度である必要があった。In this embodiment, the peripheral circuit section and the control transistor section are
While it is around 0μ, patterning for pixel division needs to be around 2μ.
両者を同時に満たす露光装置はコスト面、スループット
面から非現実的であった。An exposure apparatus that satisfies both requirements at the same time has been unrealistic from a cost and throughput standpoint.
[発明の効果コ
上記実施例において述べたような方法を用いて同一レイ
ヤーのパターニングをパターンの要求する特性に応じて
露光装置又は描画装置を使い分けることによってスルー
プットを犠牲にせずもつとも効率の良いデバイスを作成
することができた。[Effects of the invention] By using the method described in the above embodiment to pattern the same layer using different exposure devices or drawing devices according to the characteristics required by the pattern, it is possible to create a highly efficient device without sacrificing throughput. I was able to create it.
本実施例1に於いては多種少量品の効率的な生産が達成
でき実施例2においては大面積)くターンと微細パター
ンの効率的な共存が達成できた。In Example 1, efficient production of a wide variety of products in small quantities was achieved, and in Example 2, efficient coexistence of large-area turns and fine patterns was achieved.
第1図は本発明の実施例1による工Cチップのセルレイ
アウト図。
第2図は本発明の実施例2による液晶表示体装置の電極
パターン図。
1・・・・・・・・・周辺回路部
2・・・・・・・・・ROM部
3・・・・・・・・・A / D変換回路部4・・・・
・・・・・CPU部
5・・・・・・・・・工10部
6・・・・・・・・・画素電極部
7・・・・・・・・・画素制御トランジスタ部8・・・
・・・・・・画素分割ラインFIG. 1 is a cell layout diagram of an engineered C chip according to a first embodiment of the present invention. FIG. 2 is an electrode pattern diagram of a liquid crystal display device according to a second embodiment of the present invention. 1...Peripheral circuit section 2...ROM section 3...A/D conversion circuit section 4...
......CPU section 5......Engineer 10 section 6...Pixel electrode section 7...Pixel control transistor section 8...・
・・・・・・Pixel dividing line
Claims (1)
ーン形成工程をマスク等を用いる露光装置とCADデー
タ等により制御される描画装置の両者を用いて行う等複
数の露光、描画装置を用いて行うことを特徴とする半導
体装置の製造方法。In semiconductor devices, display devices, etc., the pattern formation process for the same layer can be performed using multiple exposure and drawing devices, such as using both an exposure device using a mask and a drawing device controlled by CAD data, etc. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2034744A JPH03238808A (en) | 1990-02-15 | 1990-02-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2034744A JPH03238808A (en) | 1990-02-15 | 1990-02-15 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03238808A true JPH03238808A (en) | 1991-10-24 |
Family
ID=12422835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2034744A Pending JPH03238808A (en) | 1990-02-15 | 1990-02-15 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03238808A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7847270B2 (en) | 2005-06-21 | 2010-12-07 | Kabushiki Kaisha Toshiba | Semiconductor manufacturing apparatus and method thereof |
-
1990
- 1990-02-15 JP JP2034744A patent/JPH03238808A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7847270B2 (en) | 2005-06-21 | 2010-12-07 | Kabushiki Kaisha Toshiba | Semiconductor manufacturing apparatus and method thereof |
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