JPH0323791A - Digital interpolation filter - Google Patents

Abstract

PURPOSE:To decrease the number of picture element data lines, to reduce a circuit scale and power consumption and to reduce manufacture cost by convoluting a valid picture element data onto a thinned picture element data position. CONSTITUTION:In the case of reproducing an interpolation picture element by L line such as 3 lines, the picture element data interleaved by 2X3-1=5 lines (line n-2, n-1, n, n+1, n+2) is multiplexed into 3 lines, i.e., lines n-2/n-1, n/n+1, n+2/n+1 by convoluting the picture element data to the position of the interpolated picture element among lines. In the case of reproducing the interpolation picture element by line n-1, a coefficient is multiplied with multiplexed 7-picture element data by line n-2/n-1 and a coefficient is multiplied with multiplexed 3-picture element data by line n/n+1 and the sum is used as the interpolation picture element data to be convoluted onto the picture element position. That is, multiplexing is applied. Thus, duplicated line n-2/n-1 is reproduced as the line n-1 including the interpolated picture element. Thus, the circuit scale is reduced, the power consumption is decreased and the manufacture cost is reduced.

Description

[Detailed Description of the Invention] [Summary] A digital method for regenerating interpolated pixels in a decoder from pixel data thinned out in a houndstooth pattern using line offset quincunx type subsamples in an image processing encoder. Regarding interpolation filters, we aim to provide digital interpolation filters that have a smaller circuit scale, lower power consumption, and lower manufacturing costs. In a digital interpolation filter that reproduces the thinned out interpolated pixels from the thinned out digital data and simultaneously generates pixel data for L lines, 2L-1 lines of the thinned out digital data are interpolated between the lines. a multiplexing unit that multiplexes data for L lines so that the pixel data is folded into the position of the interpolated pixel, and reproduces interpolated pixel data from data for each two adjacent lines of the multiplexed L lines. By incorporating an interpolation circuit consisting of L filter elements and (L-1) adder circuits, and interpolating pixel data from the interpolation circuit into L lines of multiplexed pixel data from the multiplexing section. The switching circuit is configured to include a switching circuit that reproduces the pixel data of the L line.

[Industrial application field]

The present invention provides line offset and
The present invention relates to a digital interpolation filter for reconstructing interpolated pixels in a decoder from pixel data thinned out in a houndstooth pattern using quincunx type subsamples.

[Conventional technology]

In image processing, an image signal is generally encoded in an encoder and transmitted to a decoder via a transmission path or the like.

Then, in the decoder, the encoded image signal is decoded and the image signal is reproduced.

In image processing that employs recent high-efficiency encoding/decoding, as shown in FIG.
A/D converter 11 that performs /D conversion, a multiplexing circuit 12 that multiplexes output data of the A/D converter 1l, a digital spatial filter 13 as a preprocessing section, and quantizes the data from the digital spatial filter 13. An encoding unit 14 that allocates, for example, a Huffman code in time series, and an encoding unit 14
A memory buffer l5 buffers the output code according to the speed of the transmission line.

In the digital spatial filter 13 described above, line offset quincunx type subsampling is performed to thin out pixels in a houndstooth pattern, and pixels are thinned out to 172. Although this sampling structure has a lower spatial resolution in diagonal directions, it is known that human visual characteristics are less sensitive to diagonal directions than to horizontal and vertical directions. 7 (pixels) to prevent aliasing noise due to sub-sampling
A two-dimensional transversal filter of ×3 (lines) is used.

On the other hand, the decoder 2 also includes a buffer memory 21 for buffering, a decoding section 22 that performs inverse transformation of the encoding section 14 of the encoder 1, and a digital spatial filter l of the encoder 1.
a digital spatial filter 23 as a post-processing unit that reproduces the interpolated pixel data thinned out in step 3; a separation unit 24 that separates a plurality of parallel lines of the digital spatial filter 23;
, and a D/A converter 25 that performs D/A conversion.

The present invention is a digital interpolation filter (two-dimensional filter) that reproduces the interpolation pixels thinned out in a houndstooth pattern by the quincunx type subsamples during the line offset shown in FIG.
23.

FIG. 6 is a diagram illustrating reproduction of interpolated pixels from pixels whose number of pixels has been thinned out to 1/2 in a houndstooth pattern.

That is, the pixels from the decoding unit 22 in FIG. 5 are triplexed (
As shown by the single circles in FIG. 6, they are arranged every other line in a grid pattern. For this reason, the digital interpolation filter 23 performs interpolation calculations using surrounding pixels in areas where no pixels exist to reproduce the image. For example, the 6th
In the figure, in order to reproduce the center pixel (interpolated pixel) indicated by the dotted line circle, 10 surrounding pixels are used, and therefore,
We will prepare a 10-tap calculation LSI consisting of 10 multipliers (which multiply the coefficients in the figure and the pixel values) and one adder which calculates the sum of the outputs of these multipliers. .

Further, FIG. 7 is also a diagram for explaining the reproduction of interpolated pixels from pixels whose number of pixels has been thinned out to 1/2 in a houndstooth pattern.
In the figure, in order to reproduce three interpolated pixels at the same time, they are quintuple (divided into five lines).In other words, using the multiplication coefficients shown in Figure 6, the pixels on lines 1, 2, and 3 are The interpolated pixels of line 3 are reproduced from the pixels of lines 2 and 3.4, and the interpolated pixels of line 4 are reproduced from the pixels of lines 3 and 4.5.

FIG. 8 is a circuit diagram showing an example of a digital interpolation filter that reproduces the interpolated pixels shown in FIG. 7. In FIG. 8, the pixel data decoded by line memories 1-1 to 1-4 are divided into five lines, that is, line n-2. n-
1, n, n+1. n+2 (line n+2 is decoded original data), and for each line, arithmetic LSIs 2-1 to 2-5 each consisting of a plurality of multipliers (for example, seven) and one adder are provided, The outputs of these calculation LSIs 2-1 to 2-5 are sent to an adder 3-1.
By adding up 3-3, lines n-1, n,
n+1 interpolated pixels are being reproduced. Note that these interpolation pixels are stored in line memories 1-2 . by a selector (not shown).
1-3. Each line data n-l, n. n+1
The data is multiplexed with 3 lines of data to produce complete 3-line data.

Note that the arithmetic LSI includes, for example, a plurality of delay circuits (corresponding to one pixel), a multiplier that performs multiplication with coefficients C1 to C9, and a multiplier, as shown in FIG. 9 (an example of N=9 taps). The output is constructed by an adder.

[Problem to be solved by the invention]

However, in the digital interpolation filter described above, when regenerating each interpolation pixel of the L line, 2
It generates L-1 lines of pixel data and requires 2L-1 arithmetic LSIs. As a result, there are problems in that the number of arithmetic LSIs increases, the circuit size increases, and therefore power consumption and manufacturing costs increase accordingly.

Therefore, an object of the present invention is to provide a digital interpolation filter with a reduced circuit scale, reduced power consumption, and reduced manufacturing cost.

[Means to solve the problem]

Means for solving the above problems are shown in FIGS. IA to ID. That is, as shown in FIG. 1A, when reproducing interpolated pixels of L line, for example, 3 lines, 2×3
−1=5 lines of thinned pixel data (line n
-2・n−1・n・n+l. pixel data is folded into the position of the interpolated pixel between the lines, ie, the lines n 2/n 1 . n/n+l
．． Multiplex to n+ 27n+l.

When regenerating the interpolated pixels of line n-1, as shown in FIG. The resulting three pixel data of line n/n+l are multiplied by the coefficients shown, and the sum is folded into the pixel position shown as interpolated pixel data, that is, multiplexed. As a result, the duplex line n-2/n-1 is reproduced as a line n-l that also includes interpolated pixels.

In addition, when regenerating the interpolated pixels of line n,
As shown in figure C, the multiplexed line n −2/n−
Multiply the 3 pixel data of 1 by the coefficient shown, and multiply the 7 pixel data of multiplexed line n/n + l by the coefficient shown, and put these sums as interpolated pixel data at the pixel positions shown. Fold in, that is, multiplex. As a result, the duplexed line n/n+1 is reproduced as a line n that also includes interpolated pixels.

Furthermore, when reproducing the interpolated pixels of line n+l,
As shown in Figure ID, multiplexed line n/n+l
Multiply the 7 pixel data of , by the coefficient shown, multiply the 3 pixel data of multiplexed line n+2/n+1 by the coefficient shown, and fold these sums into the pixel position shown as interpolated pixel data, that is. , multiplex. As a result, the duplicated line n+2/n+1 is reproduced as a line n+l that also includes interpolated pixels.

There are L filter elements (operation LSIs) used in the calculation of the interpolation pixels shown in FIGS. IB to 1D, and these coefficients may be switched by, for example, a value in a memory.

[For production]

According to the above-mentioned means, by folding effective pixel data into thinned out pixel data positions, the number of pixel data lines used for interpolation pixel calculations is reduced, and therefore the calculation LSI for interpolation pixel calculations is also reduced. The amount will decrease accordingly.

〔Example〕

FIG. 2 is a block circuit diagram showing a first embodiment of the digital interpolation filter according to the present invention, in which FIGS.
This realizes the principle shown in Figure D. In FIG. 2, similarly to FIG. 8, the thinned-out pixel data from the decoding unit 22 of FIG. n-1, n, n+1,
Multiplex to n+2.

The selector 4-1 selects the line n- from the line memory 1-1 in response to a clock CL that switches every time equivalent to one pixel.
2 pixel data and line n- from line memory 1-2
1 pixel data. That is, the selector 4-1 operates so as to fold the pixel data of line n-2 into the interpolated pixel position of line n-1.
-2/n-1 is a precaution.

Similarly, the selector 4-2 selects the pixel data of line n from the line memory 1-3 and the pixel data of line n+l from the line memory 1-4 in response to a clock CL that changes every time equivalent to one pixel. Multiplex. That is, the selector 4-2 operates so as to fold the pixel data of line n into the interpolated pixel position of line n+l.
/ n +1 is a life warning.

Similarly, the selector 4-3 selects the pixel data of the line n+l from the line memory 1-4 and the original line n+ in response to the clock CL which switches every time equivalent to one pixel.
2 pixel data are multiplexed. That is, the selectors 423 operate so as to fold the pixel data of line n+2 into the interpolated pixel position of line n+l.
Create +2/n+l.

The calculation LSIs 2-1 to 2-3 have the same structure as shown in FIG. 9, and in this case, the number of taps is seven. The three calculation LSIs 2-1 to 2-3 perform calculations on interpolation pixels together with two adders 3-1 and 3-2. That is, the calculation LSI 2-1.2-2 and the adder 3-1 reproduce the interpolated pixels of line n-1 shown in FIG. IB.

In this case, the calculation LSI 2-1 is provided with the following coefficients C1 to C7 from a memory (not shown), and the calculation LSI 2-2 is provided with the following coefficients C1 to C7.

These calculation LSIs 2-1, 2-2 and adder 3-1 also reproduce the interpolated pixels of line n shown in FIG. is given the inverse coefficient described above. In other words, the calculation LSI
2-1 is given, and the calculation LSI 2-
2 is given. Furthermore, calculation LSI2-2.2
-3, and adder 3-2 on line n+1 shown in FIG.
The interpolated pixels are reproduced. In this case, the calculation LSI 2-
2 is given the following coefficients C1 to C7, and the calculation LSI
2-3 is given the following coefficient C I -C 7.

Note that the calculations for the interpolation pixels of line n-1, the calculations for the interpolation pixels of line n, and the calculations for the interpolation pixels of line n+l are performed alternately, and the coefficients given to these are switched accordingly. shall be.

The selectors 5-1 to 5-3 also operate in response to a clock CL that changes at a time corresponding to one pixel. That is, the selector 5-1 operates to fold the interpolated pixel of line n-1 obtained at the output of the adder 3-1 into the interpolated pixel position of line n-1. In this case, line n-1 (interpolated pixel) obtained by adder 3-1 is
1. Line memory 1-2 for calculations such as 2-1 and 3-1
Since it is delayed from line n-1 (thinned pixels) from
A delay circuit 6-1 is introduced to compensate for this. Further, the selector 5-2 operates to fold the interpolation pixel of line n obtained at the output of the adder 3-1 into the interpolation pixel position of line n. In this case as well, adder 3-
The line n (interpolation pixel) obtained in 1 is the circuit 4-2.2-
Since there is a delay from line n (thinned pixels) from the line memory 1-3 by the calculation amount such as 2.3-1, a delay circuit 6-2 is introduced to compensate for this. Furthermore, the selector 5-3 selects the line n+ obtained at the output of the adder 3-2.
The interpolation pixel of l is folded into the interpolation pixel position of line n+1. In this case as well, line n+1 (interpolation pixel) obtained by the adder 3-2 is connected to the circuits 4-3, 2-3.
Since the line n1 (thinned pixel) from the line memory 1-4 is delayed by the calculation amount such as 3-2, a delay circuit 6-3 is introduced to compensate for this.

In this way, in the circuit shown in Figure 2, the pixel data that has been thinned out is divided into five lines, and then the pixel data is multiplexed (converted into three lines) by folding the pixel data into the interpolated pixel position. A calculation LSI for reproducing interpolated pixels is provided.

FIG. 3 is a block circuit diagram showing a second embodiment of the digital interpolation filter according to the present invention.
igh Definition TeleVision
) This is applied to the luminance and color signals of the post-processing section of the DPC'M band compression device. In Figure 3, human power IN
Two types of color signals, a luminance signal thinned out in a staggered pattern and a luminance signal with a number of samples of 173, are input to I and IN2.As shown in FIG. The luminance signal of n+1 is multiplexed, and the luminance signal of line n+2 and the luminance signal of line n.
Color signals of n+l and n+2 are multiplexed.

Therefore, in FIG. 3, since other pixel data has already been folded into the interpolated pixel position, the positions correspond to the line memories 1-1 to 1-4 and selectors 4-1 to 4-3 in FIG. There are no structural elements, and line memory 1-1' acts as a two-line delay circuit that converts line n/n+1 to line n-2/n-1, and line memory 1-2' converts line color/n+2 to line It acts as a 1-line delay circuit that changes color/n+1. Also, the selector 4' is connected to the line n
・Line color from n+l and line memory 1-2'/n+
1.

Arithmetic LSIs 2-1, 2-2.2-3 in FIG. 3, delay circuit 6-2 (also serves as delay circuit 6-3 in FIG. 2), adder 3-1.3-2, and selector 5- 1.5-2・5-3
Since the circuit operation is the same as that shown in FIG. 2 described above, the explanation thereof will be omitted.

Note that in the above embodiment, three lines n− including interpolated pixels
Although the reproduction of lines 1, n, and n+1 has been described, it goes without saying that the present invention can also be applied to reproduction of 4 or more lines. For example, in the case of reproducing L lines, it is sufficient to generate 2L-1 lines by folding other pixel data into interpolated pixel positions, and to provide the above-mentioned calculation LSI for this.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reduce the circuit scale of an arithmetic LSI, etc., thereby reducing power consumption and manufacturing costs.

[Brief explanation of the drawing]

FIGS. IA to ID are diagrams showing pixel arrays for explaining the basic principle of the present invention, FIG. 2 is a block circuit diagram showing a first embodiment of the digital interpolation filter according to the present invention, and FIG. is a block circuit diagram showing a second embodiment of the digital interpolation filter according to the present invention, FIG. 4 is a diagram showing a pixel arrangement used in the filter of FIG. 3, and FIG. 5 is a block diagram showing general image processing. Circuit diagram, Figures 6 and 7 are pixel array diagrams explaining line offset quincunx type subsampling, Figure 8 is a circuit diagram showing a conventional digital interpolation filter, and Figure 9 is the operation of Figure 8. 1 is a circuit diagram showing an example of an LSI. 1-1 to 1-4... line memory, 4-1 to 4-3.4'... selector, 2-1 to 2-3
... Arithmetic LSI (filter element), 5-1 to 5-3
...Selector, 6-1 to 6-3...Delay circuit.

Claims (1)

[Claims] 1. Digital data whose pixels are thinned out in a houndstooth pattern using line offset quincunx type subsampling is reproduced by thinned out interpolated pixels, and at the same time pixel data for L lines is generated. In the digital interpolation filter to be generated, a multiplexing unit that multiplexes 2L-1 lines of the thinned out digital data into L lines of data so that pixel data is folded into the position of the interpolated pixel between the lines. (1-1 to 1-4, 4-1 to 4-3), and L filter elements (2-
1 to 2-3) and (L-1) adder circuits (3-1, 3
-2) and a switching circuit (5-2) that reproduces L-line pixel data by folding the interpolated pixel data from the interpolation circuit into the L-line multiplexed pixel data from the multiplexer. 1 to 5-3). 2. Multiple lines of digital data whose pixels are thinned out in a houndstooth pattern using line offset/quincunx type subsampling are multiplexed so that the pixel data is folded into the position of the interpolated pixel that has been thinned out in advance. In a digital interpolation filter that reproduces interpolated pixels thinned out from the digital data of the digital data and simultaneously generates pixel data for multiple lines, the interpolated pixel data is reproduced from the multiplexed data for each of two adjacent lines. Filter element (2-1 to 2-
3) and an interpolation circuit consisting of adder circuits (3-1, 3-2), and interpolated pixel data from the interpolation circuit is folded into the multiplexed digital data for the plurality of lines to generate pixel data for the plurality of lines. A switching circuit that reproduces (
5-1 to 5-3).