JPH0323776A - Circuit device for leading out pulse signal - Google Patents

Abstract

PURPOSE: To prevent the device from being influenced by a drop-out fault by counting clock signal pulses and resetting the counting by a horizontal frequency pulse signal outputted from the output side of a check circuit or a programmable fixed value memory. CONSTITUTION: A counter 14 acting as an address counter counts up clock signal pulses. An address value obtained from the output side of the counter 14 is inputted to the programmable fixed value memory 15 and many pulse signals are extracted from the output side of the memory 15. When the counter 14 arrives especially at a prescribed count value, a pulse signal is sent from the memory 15 and the counter 14 is reset to an initial address value by the signal. Then a synchronizing pulse signal of which validity is checked to synchronize a digital phase control loop is supplied to the counter 14. Consequently the device is prevented from being influenced by a drop-out fault.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a circuit device for deriving a signal, the video signal being extracted from a magnetic tape of a video magnetic tape device, and for clamping the video signal. and a threshold circuit for separating a synchronization signal from a clamped video signal.

A synchronization pulse separation circuit for RAS television signals of video recorders is known from DE 2 625 775 A1. In this circuit, a trigger circuit separates the synchronization pulse from the BAS television signal to which it is applied. The sync pulse controls two circuits provided to clamp and blank the BAS television signal.

Furthermore, a pulse separation circuit is known from DE 34 44 764 C2, which has a feedback-coupled operational amplifier as a clamping stage.

The clamp stage controls a downstream converter to separate the synchronization pulses in the video signal.

Furthermore, a digital sync separator with a counter is known from US Pat. No. 4,491,870. This counter counts the pulses of the clock signal. The counter is reset by the horizontal sync pulse via a logical AND combination.

A decoder device is connected to the output side of the counter.
The decoder device derives the gating signals of the vertical sync signal and the color sync signal from the applied sync signal.

This known circuit arrangement is susceptible to dropout disturbances in the reproduced video signal.

Therefore, the pulse signal derived from the synchronization signal of the video signal extracted from the magnetic tape has an error.
This error leads to incorrect segment switching or time error correction.The object of the invention is to improve a circuit arrangement of the type mentioned at the outset to ensure that the synchronization pulses contained in the video signal are evaluated,
The goal is to construct the system so that it is not affected by dropout failures. Means for Solving the Problem The above problem consists of a circuit for forming a clock signal and a circuit for checking the pulse state and pulse width of the synchronization pulse depending on the clock signal and the gate pulse signal in the separated synchronization signal. and a digital phase control loop having a counter coupled in feedback via a programmable fixed value memory, said counter counting the pulses of the clock signal and at the output of the check circuit or the programmable fixed value memory. The counter is configured to supply an address signal to a programmable fixed-value memory and to allow the pulse signal and the gate pulse signal to be retrieved at the output of the fixed-value memory. is resolved.

The circuit arrangement according to the invention having the features of claim 1 has the following advantages. That is, disturbances in the extracted video signal caused by error locations in the magnetic tape or imperfections in the head tape contact have little effect on the pulse signal derived from the synchronization signal. By deriving the pulse signal without being influenced by disturbances, functions on the reproduction side, such as magnetic head switching, clamping, amplification control, burst gating, or time error correction, can be performed reliably.

Advantageous developments of the invention according to claim 1 are possible with the measures recited in the subclaims. It is particularly advantageous if the time-critical circuit elements, such as monostable flip-flop stages or analog phase control circuits, are constructed digitally. Therefore, the circuit arrangement of the present invention is free from aging and temperature drift.

Embodiments An embodiment of the invention is shown in the drawings and is explained in more detail in the following description. In the figure, reference numeral 1 indicates a magnetic tape, and the magnetic tape l is scanned by two magnetic heads 2 and 3 of a rotary scanning device (not shown) on a track running diagonally with respect to the tape edge of the magnetic tape. If the magnetic table l is wound 180' around the rotary scanning device, it is necessary to connect the magnetic heads 2 and 3 to the input side of the stage 5 via the control switch 4. Stage 5 preamplifies and equalizes the signal extracted from the magnetic tape l. Stage 5 is followed by a stage 6 having a dropout detector and a frequency demodulator. A frequency demodulator provides a video signal containing synchronization pulses, and a dropout detector provides a dropout signal upon signal loss of the FM signal.

The video signal obtained is fed on the one hand to a clamping stage 7 and on the other hand to a sync pulse separation circuit 8.

In the embodiment, the synchronous pulse separation circuit 8 consists of a peak value rectifier. The peak value rectifier detects the voltage value of the synchronous ground of the negatively rectified synchronous pulse. The detected electric FE value is used as a reference level for the comparator. A comparator separates the sync pulse from the applied video signal.

The separated sync pulses are connected to the AN along with the dropout signal.
The video signal demodulated by the clamp pulse signal which is logically combined in the D stage 9 and further conducted to the clamp stage 7 as a clamp pulse signal is clamped to the synchronous ground in terms of DC voltage. A converter 10 downstream of the clamping stage 7 therefore separates the synchronization pulse signal from the clamped video signal as a function of the reference level of the reference voltage Rll.

The separation of the synchronization pulses by the converter lO operates more precisely than the synchronization pulse separation circuit 8 used for forming the clamp signal. Therefore, time errors in the video signal can be accurately detected based on the side edges of the synchronization pulse signal. Under normal operating conditions, the synchronous pulse separation circuit 8 and comparator 10 deliver isochronous pulses. However, in the event of a fault, the peak value rectifier present in the synchronous pulse separation circuit 8 is charged to a negative value: That is, for a short period of time it is charged to such a value that the synchronization pulse cannot be separated. In order to avoid this situation in case of a dropout, the peak value rectifier is controlled by a dropout signal and stores the previously detected voltage value during this time.

In the present invention, the synchronization pulse signal sent out by the comparator 10 is checked for plausibility (rhythmability). The synchronization pulse signal is then examined in relation to the pulses of the clock signal generated by the clock generator. In an embodiment, the clock signal is an HDTV video signal (l
250 scan lines) is combined with 264 times the horizontal frequency. If the scan line frequency is 3 1 25 kHz, the frequency of the clock signal is 27 MHz.

To check the pulse width and pulse condition,
The 7 MHz clock signal and the separated synchronization signal are supplied to the check circuit 13.

Check circuit 13 includes a counter for counting pulses of the clock signal. The counting process starts when a falling edge is present in the synchronization signal and stops again when a rising edge is present. The number of clock pulses counted represents the width of the synchronization pulse applied each time. In an embodiment, there must be 20 clocks of a 27 MHz clock signal for one synchronization pulse to send out information for a valid synchronization pulse. This number also takes into account the tolerance range caused by the asynchrony of the 27 MHz clock signal to the extracted video signal. If a dropout exists during the counting interval, the counting process is interrupted under control via the dropout signal and the counter is reset.

As mentioned at the beginning, the pulse status of the synchronization pulse is also checked. For this purpose, the check circuit 13 is supplied with a gate pulse signal having a predetermined time window from a digital phase control loop. The phase control loop is counter 1
4. Programmable fixed value memory 15 and OR stage l6
Consists of. The time window of the gate pulse signal limits the interval in which a synchronization pulse in the synchronization pulse signal can be expected. The counter 14, which acts as an address counter, has two
Count the pulses of the 7 MHz clock signal. The address value obtained at the output of the counter 14 is further conducted via an address path to a programmable fixed value memory l2, at whose output a number of pulse signals combined at a horizontal frequency can be extracted. In particular, when a predetermined counting state is reached, a pulse signal is emitted from the programmable fixed value memory 15, which resets the counter 14 to the initial address value via the OR connection l6. Furthermore, a synchronization pulse signal, checked for plausibility, is supplied to a counter 14 for synchronization of the digital phase control loop.

The accuracy of the circuit arrangement according to the invention is determined by the clock frequency of the clock signal generated by the clock generator l2. Synchronization pulse signals, the accuracy of which is not dependent on temperature changes, aging or the occurrence of dots, are required for the various playback circuits of the video magnetic tape unit, whose validity has been checked. However, the requirements of this regeneration circuit for the synchronous pulse signal are quite different.

If the synchronization pulse taken to derive the clamp signal drops out during the blanking interval,
It must be suppressed so that clamping errors do not occur. The clamping signal is therefore advantageously derived from the synchronization pulse signal HBind delivered by the check circuit 13. In contrast, the pulses required for head switching must be available even in the case of impaired video signals. This pulse is preferably taken off from the output of the programmable fixed value memory 15. The same applies to the pulses used in the compensator for the evaluation of time errors.

In circuit design, the check circuit 13 preferably consists of a programmable component (GAL), which can be programmed as a state machine and sets the temporal state of the synchronization pulse to a predetermined condition or to a predetermined condition. Interrogate according to the request protocol. It has proven advantageous in circuit technology to replace the digital phase control loop with counter 14, programmable fixed value memory 15 and OR combination l6 by a programmable component (GAL). An arbitrarily formed pulse signal can be derived using the obtained address decoding device.

Effects of the Invention According to the present invention, it is possible to reliably evaluate synchronization pulses included in a video signal and to ensure that the synchronization pulses are not affected by dropout failures.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating an embodiment of the present invention. l...Magnetic tape, 2.3...Magnetic head, 5...
- Preliminary amplification stage, 6... Frequency demodulator, 7... Clamp stage, 8... Pulse separation stage, 11... Reference voltage source,
l2...Clock generator, 13...Check circuit,
14...Counter, 15...Memory

Claims (1)

[Claims] 1. A circuit device for deriving a pulse signal to be combined with a synchronizing signal of a video signal, the video signal being taken out from a magnetic tape of a video magnetic tape device, which clamps the video signal. and a threshold circuit for separating a synchronization signal from a clamped video signal, comprising: - a circuit (12) for forming a clock signal; - a synchronization signal in the separated synchronization signal; a circuit (13) for checking the pulse state and pulse width of the pulses as a function of the clock signal and the gate pulse signal; - a counter (14) coupled in feedback via a programmable fixed value memory (15); a digital phase control loop having: said counter (14) counting the pulses of the clock signal and being resettable by a horizontal frequency pulse signal at the output of the check circuit (13) or the programmable fixed value memory (15); A circuit device for deriving a pulse signal, characterized in that the counter supplies an address signal to a programmable fixed value memory, and a pulse signal and a gate pulse signal can be taken out at the output side of the fixed value memory. 2. The check circuit (13) can be controlled by the dropout signal as follows: when a dropout exists, the pulse signal (HBand) is not sent to the phase control loop (14, 15, 16). 2. The circuit arrangement according to claim 1, wherein the circuit arrangement is controllable. 3. The check circuit (13) is provided with another counter, which starts to count the clock pulses of the clock signal when there is an edge in the synchronization signal; It is stopped again by a trailing edge and reset by a dropout signal, and furthermore a logic coupling device is provided on the output side of the counter, said device being provided for evaluating the counting state of another counter. The circuit device according to item 1.