JPH03237488A - Television screen display device - Google Patents

Abstract

PURPOSE:To erase displayed characters at every scanning line by using a masking range control circuit controlling a masking range corresponding to an output from a comparator and a polarity switching circuit switching the polarity of an output from the masking range control circuit. CONSTITUTION:By sending the data stored in an n-bit register 13 and the data obtained from a n-bit up counter 1 to the comparator 14, comparing control is carried out so that the baundary of the masking range is designated with the use of every scanning line in a screen. By imparting an output from the comparator 14 to the masking range controlling circuit 15, such processes are carried out that high and low level signals are outputted in scanning line areas upper and lower than the baundary of the masking range, respectively. These signals are inputted to the output polarity switching circuit 16, whose output and an output from a chrominance signal selecting circuit 10 and the value of a shift register 9 where the dot patterns of characters are stored are inputted to three input AND circuits 11, whose outputs are sent to an image signal output circuit 12. Thus, the displayed characters can be erased, i,e., masked at every scanning line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television screen display device.

[Conventional technology]

FIG. 3 is a block diagram of a conventionally used circuit configuration, and FIG. 4 is a display function diagram showing the TV screen display capability obtained by the circuit configuration.

In the figure, (1) is a counter, (2 is a data bus,
(3) is a vertical position detection circuit, (4) is an oscillation circuit, (5)
is a horizontal position detection circuit, (6) is a timing control circuit, (
7) is a CRTRAM, (8) is a CRTROM, (9) is a shift register, OQ is a color signal selection circuit, OQ is a two-manual AND circuit, and 0 is an image signal output circuit.

Next, a horizontal synchronizing signal (hereinafter referred to as H
5YNC name) as n-bit up counter (1)
and generates data representing all the scan line IHA areas of the screen according to the count up. After that, by sending the output data of the n-bit up counter (1) and the value of the vertical position detection data sent from the data bus (2) via the CPU (not shown) to the vertical position detection circuit (3), −
The position of the scanning line, ie the vertical position of the screen, is determined. thus,
Once the vertical position of the screen is determined, the output data of the vertical position detection circuit (3) is sent to the oscillator circuit (4) which generates a clock signal to generate a clock signal representing all horizontal positions in the scan line, and this clock The horizontal position of the screen is determined by applying signals and horizontal position detection data from a data bus (2) via the CPU to a horizontal position detection circuit (5).

After determining the vertical and horizontal positions of the 'C screen in this way, the vertical position detection circuit (3) and the horizontal position detection circuit (
By sending the output data of 5) to the timing control circuit (6), the following circuits, namely, screen display data memory (hereinafter referred to as CRTRAM) <7>, screen display character memory (hereinafter referred to as CRTROM) (8) )・Controls the timing of sending data to the shift register (9).

Thereafter, data is sent from the data bus (2) via the CPU to the CRTRAM (7), which stores the specifications of the oil and color of the characters to be displayed on the screen, according to the timing controlled by the writing timing control circuit (6). Inputs the data value that specifies the type and color of the characters to be sent. Next, the timing control circuit (6) is stored in the CRTRAM1 (8) which stores the dot arrangement pattern of the dots necessary for the character composition, that is, which dot in the drawing is used to indicate the character of the specified type and color.
) while measuring the timing with the CRTRAM (7).
), the ROM contents specified by this data are read out, and the output data is stored in the shift register (9) at - hours while the timing is controlled by the timing control circuit (6). data and CR
The screen display was performed by inputting the output of the color signal selection circuit 0Q read out from the TRAM (7) to the two-manual AND circuit 0υ, and giving the output to the image signal output circuit □□□. To erase displayed characters, use CRTRAM (7)
By rewriting the data of the color signal selection circuit 00 and changing the data of the color signal selection circuit 00, the instantaneous "15
I was able to do it. When the display of the screen associated with one field scan is finished, a new next one is started at the vertical synchronization number (hereinafter abbreviated as v5ync) that determines one field.
Screen display for field scanning is performed.

[Problem to be solved by the invention]

As the function of information transmission through T V m-screen display progresses, as shown in Fig. 3, the conventional time G+= or T
When erasing characters on the V screen, it was done instantaneously one character at a time. This has the disadvantage that it lacks visual impression due to the variety of display formats.

This invention solves the problems of the conventional ones as described above)
It was developed for the purpose of erasing characters in multiple rows and columns that can be displayed on a TV screen, one scanning line at a time.

[Means to solve the problem]

The TV screen display device according to the present invention includes an n-bit register that inputs data on a data bus via a CPU that is added in parallel to a character generation circuit, and a counter that uses the value of this n-bit register and Hsync as count sources. A comparison circuit for comparing count values, a mask range control circuit for controlling the mask range according to the output of the comparison circuit, and a polarity switching circuit for changing the polarity of the output of the mask range control circuit are provided.

[Effect]

The circuit configuration in this invention erases a multi-column character group in one
This is done for each scanning line.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of the circuit configuration necessary for the present invention, and FIG. 2 is a display function diagram showing the TV screen display function obtained by the circuit configuration.

Referring to Figure 1, this circuit configuration is constructed by adding n-bit register 0, polarity switching circuit OQ, comparison circuit 04), and mask range control circuit 0!5 in parallel to the conventional character generation circuit. . Therefore, the circuit configuration will be explained in detail. First, in Figure 1, the n-bit up counter (1) inputs the H5YNC signal and the VSYNC13 signal, and sends the processed data to the vertical position detection circuit (3) and comparison circuit 04), which are one of the conventional circuit configurations. Output. The n-bit register (13) inputs data sent via the data bus (2) via the CPU.

The comparison circuit 0Φ inputs the output data of the n-bit counter (1) and the n-bit register 03, and outputs the processed data to the mask range control IW path 05. The mask range control circuit 09 outputs the processed data to the polarity switching (b) path (1). The three-man power AND circuit 0υ outputs the output data of the shift register (9) and polarity switching circuit θQ, which is one of the conventional circuit configurations. is input, and the processed data is sent to the plane image signal output circuit 0.
By outputting more information, the screen display function according to the present invention is obtained. Here, the conventional circuit configuration is the third
The alpha power of the character generation circuit configured within the dotted line shown in the figure includes the vertical position detection circuit (3), timing control circuit (6), CRTRAM (7), CRTROM (8), shift register ( 9), the circuit configuration 11 is configured so that data moves as shown by the arrow in this figure.

Next, the operation will be explained. First, the H5YNC signal is sent to the n-bit up counter (1) to create data that can represent all scan line areas, ie all vertical positions, of the screen. Thereafter, the output data of the n-bit up counter (1) is applied to the conventionally used character generation circuit α, and at the same time, it is also applied to the circuits necessary for an embodiment of the present invention. Therefore, when we look in detail at the operation of the circuit required for one embodiment of this invention, we first see that the CPU
Data for setting the boundary of the mask range is stored in the n-bit register OJ from a data bus (2) via a data bus (not shown). After this, by sending the data stored in the n-bit register (to) and the data obtained by the n-bit up counter (1) to the comparison circuit 0◆, all the scanning lines of the screen are used to determine the boundaries of the mask range. By performing comparison control to specify the mask range control circuit (1G), a high level signal is generated in the scanning line area above the border of the mask range, and a high level signal is generated in the scanning line area below the border of the mask range. Processing is performed so that a low level signal is output.The signal is input to this output polarity switching circuit m, and this output, the output of the color signal selection circuit αO, and the shift register (9) in which the character dot pattern is stored are input. ) by inputting the value to the three-man AND circuit αυ and sending its output to the image signal output circuit, it becomes possible to erase (mask) the displayed characters at one scanning line rate as shown in Figure 2. .

Further, by incrementing the value of the n-bit register a4 by software at the cycle of Vsync, it becomes possible to move the mask range over time and erase the displayed characters smoothly.

It is also possible to use a display method in which the displayed characters move and disappear over time by keeping the mask range constant and changing the character display position using software at the cycle of Vsync.

〔Effect of the invention〕

As described above, according to the present invention, there is provided an n-bit register that inputs data on a data bus via a CPU, and a comparison circuit that compares the count value of this n-bit counter with the count value of a counter whose count source is Hsync. ,
A mask range control circuit that controls the mask range according to the output of this comparison circuit and a polarity switching circuit that changes the polarity of the output of this mask range control circuit are used to create the display character, so that the displayed characters can be displayed at one scanning line rate. It can be erased gradually.

It is also possible to change the mask range over time using software to smoothly erase displayed characters. This makes it possible to improve the impression level and variety of forms of the display screen.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the bridge necessary for this invention,
Fig. 2 is a display function diagram showing the TV display function obtained by the circuit configuration, Fig. 3 is a block diagram showing the conventional circuit configuration, and Fig. 4 is the TV display function obtained by the circuit configuration. FIG. 3 is a display function diagram showing a screen display function. In the figure, (1) is a counter, (2) is a data bus,
(3) is a vertical position detection circuit, (4) is an oscillation circuit, (5)
is the horizontal position detection circuit, (6 is the timing control circuit, (
7) is a CRTRAM, (8) is a CRTROM, (9) is a shift register, Q3i and n bit registers, 0 is a comparison circuit, q is a mask range control circuit, and OQ is a polarity switching circuit. In addition, in the figure, the W4- symbol indicates the same or equivalent part.

Claims (1)

[Claims] A vertical position detection circuit that inputs data on a data bus via the CPU and processing data of an n-bit amplifier counter controlled by a horizontal synchronization signal and a vertical synchronization signal, and an oscillation circuit that inputs processing data of this vertical position detection circuit. a horizontal position detection circuit that inputs the clock signal generated by this oscillation circuit and the output data of the vertical position detection circuit; and a timing control that inputs the processed data of this horizontal position detection circuit and the output data of the vertical position detection circuit. a screen display data memory for inputting the timing controlled by this timing control circuit and data on the data bus via the CPU; and a screen display for inputting the processed data of this screen display data memory and the output data of the timing control circuit. A character memory, a shift register that inputs the contents of this screen display character memory and output data of a timing control circuit, and an image signal output circuit that outputs a color signal according to the output of this shift register are configured in parallel. , an n-bit register, a comparison circuit that compares the value of the n-bit register and the value of the n-bit counter, a mask range control circuit that controls the mask range of the image signal according to the output of the comparison circuit, and the mask range. A television screen display device comprising a polarity switching circuit that receives output data from a control circuit.