JPH0323721A - Waveform equalization circuit - Google Patents

Abstract

PURPOSE:To facilitate the design of an analog circuit and to compress a circuit scale by performing waveform equalization by correcting the distortion of transmission line characteristic with only one A/D converter operated with a frequency twice the sampling rate value to be transmitted. CONSTITUTION:The A/D converter 2 converts an analog signal 1 transmitted in a sampling value to a digital signal with the frequency 2NHz twice the sampling rate, and a synchronizing signal is detected at a synchronism detection circuit 14 from a signal latched with the frequency NHz, and an NHz re- sampling clock and a 2Hz clock are generated at a clock generation circuit 15. Also, delay of even-numbered clocks is supplied on the digital signal of 2NHz rate at a delay circuit 4 with the 2NHz clock, and the waveform equalization is performed by mixing a distortion correction signal with the transmission characteristic having the same delay quantity generated from a variable filter 9, and a sampling value signal is outputted which is latched and transmitted with the frequency NHz. In such a way, the analog circuit can be unified to one system by using only one A/D converter, and the design of the circuit can be performed easily.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an equalization circuit that removes transmission line distortion when transmitting sample values, and in particular, it relates to an equalization circuit that eliminates transmission line distortion when transmitting sample values, and in particular, it reduces the number of analog circuits to one system, thereby facilitating circuit design. The present invention relates to a waveform equalization circuit.

[Conventional technology]

As one of the high-definition broadcasting systems, MUSE (Mul
Tiple Sub-Nyquist Sample
g Encoding) system was developed by NHK. This MUSE method transmits signals as sample values. Sample values are transmitted as impulse responses with cosine roll-off characteristics that satisfy the Nyquist condition, but if there is distortion in the transmission path characteristics, interference between sample values occurs. The condition for not causing this interference is that the transmission path has the above-mentioned cosine roll-off characteristic. Therefore, rMU is used as a device to correct distortion of transmission line characteristics.
“Waveform equalizer with built-in SE decoder” (Iwadate et al. IEICE Technical Report Vol. 88 No. 300, P. 1 to P. 7
) is known as a waveform equalizer. According to this document, an A/D converter operating at a clock frequency of NHZ resamples the sample values to be transmitted, and an A/D converter operating at a clock frequency of 2 MHz to generate a correction signal for correcting distortion in the transmission path. A operating at z
/D converter and two A/D converters are required. [Problems to be Solved by the Invention] The above-mentioned conventional technology uses an A/D converter for A/D converting sample values to be transmitted, and an A/D converter for creating a signal for correcting transmission path distortion. In addition, the design must be such that the characteristics of these two A/D converters and the characteristics of the analog circuit up to the input of these A/D converters are precisely matched.

An object of the present invention is to facilitate the design of the analog circuit described above.

[Means to solve the problem]

The above purpose is to use an A/D operating at a clock frequency of 2 MHz.
A latch circuit that converts an analog signal transmitted as a sample value into a digital signal using one converter and latches this digital signal at a frequency of MHz, and a synchronization detection circuit that detects a synchronization signal from the signal latched by the latch circuit. A clock generation circuit is provided which generates 2 NHZ and NHZ clocks from this, and the A/
The delay amount of the equalization circuit that equalizes the digital signal converted by the D converter is set to 2 NHz clock for an even number of clocks, and the signal after equalization is set to NHz that has the same phase as the latch clock before and after the synchronization signal detection circuit. This is achieved by latching with a clock. [Operation] The A/D converter converts the sampled analog signal into a digital signal at a frequency of 2 MHz, which is twice the sample rate. This digital signal is latched by an NHz resampling clock, and a synchronization signal is detected from this by a synchronization signal detection circuit. A clock generation circuit generates an N Hz resample clock and a 2 N H2 clock from the detected synchronization signal. This results in N
The Hz resample clock provides a phase for resampling the transmitted sample values. In addition, the 2 MHz rate digital signal is delayed by an even number of 2 Hz clocks, and a distortion correction signal with the same delay amount and transmission line characteristics is mixed to perform waveform equalization. .

This equalized signal is latched by the N Hz resampling clock and outputs a sample value signal to be transmitted.

As a result, it is possible to obtain sample values that have undergone waveform equalization, so it is possible to use one A/D converter and one analog circuit system, making circuit design easier. , one embodiment of the present invention will be explained with reference to FIG. 1st
, In one embodiment of the figure, l is a terminal for inputting an analog signal transmitted with a sample value, 2 is an A/D converter, and 3 is an A/D converter.
is an input terminal for the sampling clock in the A/D converter 2, 4 is a delay circuit, 5 is an adder, 6 is a latch circuit that holds the signal, 7 is an input terminal for the data latch clock in the latch circuit 6, 8 9 is a variable filter for waveform equalization, 10 is a reference signal detection circuit for detecting a reference signal for determining distortion of transmission line characteristics, and 11 is a detected reference signal. 12 is a La Sochi circuit, 13 is an input terminal for a data latch clock in the latch circuit 12, and 14 is a synchronization signal. The synchronization detection circuit for detecting the
A clock generation circuit 16 generates the z clock. H
z resample clock output terminal, 17 is 2 N H
This is the output terminal of the z clock. FIG. 2 shows a sample value transmission signal when the transmission path characteristic is a normal cosine roll-off characteristic. Signal 2 shown by dashed line
01 is the analog signal to be transmitted. This signal 201
is input from input terminal 1 and guided to A/D converter 2. A/D converter 2 is led from terminal 3 with 2N
Operated by Hz clock, analog signal 201
The digital signal 2b 1, 2 al, 26 2, 2
Convert to a2, -=. This digital signal 2b l,
2cLl, 2m2, 2α2, . . . are guided to a delay circuit 4, a variable filter 9, and a latch circuit 12. The latch circuit 2 latches the digital signal using an NHZ resampling clock derived from a terminal 13. This NHZ resampling clock uses the sample value transmitted signals 2al,
This is a clock with a phase that latches 2cL2, 2α3, . The resampled signals 2α1, 2a2, 2α3, . . . latched by the latch circuit 2 are guided to the synchronization detection circuit 14. The synchronization detection circuit 14 receives the resampled signal 2α1,
2cL2, 2cL3, . . . and guides the detected synchronization signal to the clock generation circuit king 5. The clock generation circuit 15 detects the synchronization signal from
Generates a Hz resample clock and a 2NH clock, and outputs an NH resample clock from the output terminal 16.
Further, the output terminal 17 outputs a 2 MHz clock. In this case, the NHz resample clock is phase synchronized with the synchronization signal latched by the latch circuit 12, and its phase is the same as that of the sample signals 2α1 and 2cL2 in FIG.
, 2(L3, . . . ) is in phase with the phase that can latch.

The delay circuit 4 is a delay circuit having the same delay amount as that of the variable filter 9, and outputs digital signals 2b1, 2cLl, 262, 2a2, - derived from the A/D converter 2.
delay. The delayed digital signal is sent to an adder 5
be led to. Further, the variable filter 9 receives digital signals 261.2α1, 262 derived from the A/D converter 2.
, 2 (12, . . . ) generates a signal for correcting the distortion of the transmission line characteristics, and guides the correction signal to the adder 5.The microcomputer controls the tap coefficients that determine the characteristics of the variable filter that corrects the distortion of the transmission line characteristics. The adder 5 also adds the correction signal derived from the variable filter 9 to the digital signal derived from the delay circuit 4 to correct distortion of the transmission path characteristics. The digital signal is guided to the latch circuit 6 and the reference signal detection circuit 10 as a waveform-equalized signal.
The Hz resample clock is connected to the N terminal of output terminal l6 in order to prevent malfunctions due to changes in clock duty.
It is chosen to have the same phase as the Hz resample clock. A
/The amount of delay from the D converter 2 to the latch circuit 6 is 2.
By setting the NHz clock to an even number of clocks, the latch circuit 6 has a sample phase of 2α in the latch circuit 2.
1, 2cL2, 2cL3, . . . can be latched in the same phase. The sample value signal after waveform equalization latched by the latch circuit 6 is outputted from the output terminal 8.

On the other hand, the reference signal detection circuit 10 extracts a signal (for example, Vl
ts) and guides it to the microcomputer 11. The microcomputer l1 calculates the distortion of the transmission line characteristics from the derived reference signal, determines the tap coefficients that determine the characteristics of the variable filter 9 that corrects the distortion, and guides the determined values to the variable filter 9. An outline of the above operation will be explained using a frequency spectrum. Third
A characteristic 301 indicated by a broken line in the figure is an example of an ideal characteristic of a transmission path having a cosine roll-off characteristic.

When distortion occurs in the transmission line characteristics and the characteristic becomes 302, A/
Due to sampling by the D converter 2, the frequency spectrum of the digital signals 2b1, 2cLl, 262, 2cL2, . . . has characteristics 302 and 304. A variable filter 9 generates a correction signal that corrects the distorted signal so that it has ideal characteristics 301. As a result, the transmission line has a characteristic of 301, which is converted to N by the latch circuit 6.
By latching with the Hz resampling clock, sample values can be obtained without causing aliasing distortion due to sampling. As described above, there is one A/D converter that operates with a 2 Hz clock, and the digital signal derived from this converter is latched using an NHZ resampling clock. Furthermore, a synchronization signal is detected from this latched signal, and an NHz resample clock and a 2NH2 clock whose phase is synchronized with the detected synchronization signal are generated. In addition, the delay amount of the circuit that corrects the distortion of the transmission line characteristics and equalizes the waveform is 2 N
By using an even number of Hz clocks, it is possible to latch the signal after waveform equalization in which the distortion of the transmission path characteristics has been corrected with a clock having the same phase as the NHz resampling clock. This allows equalization of transmission line characteristic distortion in a region where there is no aliasing due to sampling, and it is possible to obtain sample values with good characteristics. FIG. 4 shows another embodiment of the present invention. The difference between the embodiment in FIG. 3 and the embodiment in FIG. 1 is that instead of the delay circuit 4, there is a latch circuit 18, an input terminal 19 for the NH2 sample clock, and a delay circuit that delays by the NH2 resampling cycle. 20, the rest is the same as the embodiment shown in FIG. Below, the operation will be explained with respect to points that differ from the embodiment shown in FIG. The latch circuit l8 has an input terminal 1
By the NHZ resample clock derived from 9,
Digital signals 2b1, 2α1, 2b2, 2a . Latch the sample values 2al, 2a2, 2a3, . . . from 2,=-. The latched sample value 2cL1, 2a
2, 2a3, - are guided to the delay circuit 20. When the delay amount of the variable filter 9 is 2M clocks with a 2 MHz clock, the delay amount of the delay circuit 20 is N.
The resample clock of Hz is (M-1) clocks. As a result, the amount of delay between the signal guided from the delay circuit 20, which is corrected by the adder 5, and the correction signal guided from the variable filter 9 is made equal. The operation of the above embodiment will be explained using the frequency spectrum shown in Fig. 3. The frequency spectrum of the digital signal sampled by the A/D converter 2 has the characteristic 30.
It becomes 2,304. The variable filter 9 generates a correction signal for correcting the distortion of the transmission line characteristics with respect to this characteristic, as in the embodiment shown in FIG. Since the signal to be corrected is sampled by the latch circuit 18 using the NHz resampling clock, the characteristic 303 is folded back. The signal on the side corrected by this is N/2H
The characteristic is that signals of z or higher are folded around N/2 Hz. This aliased signal is corrected by the distortion correction signal from the variable filter 9 that is not aliased. However, since the sample is sampled by the latch circuit 6 using the MHz sample clock, the correction signal also undergoes aliasing, and this aliasing also corrects the aliasing of the signal to be corrected. Therefore, at the output of the latch circuit 6, a waveform-equalized sample value without distortion of the transmission path characteristics can be obtained.

Further, according to this embodiment, the delay circuit 2o only needs to operate at NHZ, and together with the latch circuit 18, the delay amount can be half that of the delay circuit 4 of FIG. This allows the number of delay stages to be reduced and the operating speed to be halved, thereby reducing power consumption.

FIG. 5 shows another embodiment of the present invention. The difference between the embodiment in FIG. 5 and the other embodiments is that in the embodiment in FIG.
3.25, a variable filter e27, a variable filter o28, and an adder 29, but the rest is the same as the embodiment shown in FIG.

Hereinafter, the operation will be explained regarding the differences from the embodiment shown in FIG. 4. The latch circuit 21 is connected to the NH connected to the input terminal 22.
2 from A/D converter 2 with the resample clock of z
A 7-latch circuit 25 that latches the MHz sample signal receives A with a 2 MHz clock derived from the input terminal 26.
The 2 MHz sample signal from the /D converter 2 is latched and output to the latch circuit 23. Latch circuit 2
Reference numeral 3 denotes an NHz resample clock introduced from the input terminal 24, which latches the 2NHz sample signal introduced from the launch circuit 25. These latch circuits 21, 2
3, 25 and NHZ resample clock and 2NHZ
2 M derived from A/D converter 2 with a clock of
The Hz sample signal is serial/parallel converted into 2-bit 1-. The signal latched by the latch circuit 21 is transmitted to the variable filter e2'! Also, the signal latched by the latch circuit 23 is passed through the variable filter 0
It will lead you to 28. Variable filter e27 and variable filter o
28 are the same as the filters of the variable filter 9 that are configured with only even and odd taps. Therefore, from the microcomputer, information on even-numbered taps is guided to the variable filter g27, and information on odd-numbered taps is guided to the variable filter 028 as tap coefficients that determine filter characteristics for correcting characteristic distortion of the transmission path. As described above, the correction signals generated separately for even-numbered taps and odd-numbered taps are led to the adder 29 to generate a correction signal for transmission line distortion. This is led to adder 5 and corrected.

In the first embodiment described above, the correction signal for transmission line characteristic distortion is equivalent to sampling with a NHz clock when adding in the adder 29, and the distortion correction signal has a spectrum of N/2Hz or more. / 2 Hz folded around the z axis. However, by adding in the adder 29, the correction value obtained from the 2 NHZ sample value is folded back by NH Hz / 2, and the same waveform equalization as in the embodiment explained in FIG. 4 can be performed. .

Furthermore, according to this embodiment, a correction signal is generated for correcting the distortion of the transmission path characteristics with respect to the transmitted sample value, so the signal processing is performed almost entirely at NHz.
The resampling clock rate is sufficient, and the use of a 2 MHz clock requires only an A/D converter and one latch circuit. Therefore, power consumption can be reduced.

The serial/parallel conversion circuit using the latch circuits 21, 23, 2.5 shown in FIG. 5 is an example, and the structure is not limited to this.

〔Effect of the invention〕

According to the present invention, a single A/D converter that operates at twice the frequency of the transmitted sample value rate can perform waveform equalization without aliasing distortion due to sampling, or alias distortion due to sampling. Even if distortion occurs, it is possible to perform waveform equalization according to the aliasing distortion and remove the aliasing distortion, so it is possible to satisfactorily equalize the waveform of the distortion in the transmission line characteristics, and the analog circuit system is Only one system is required up to the /D converter input stage, making it easy to design an analog circuit and reducing the circuit scale.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing sample value transmission, Fig. 3 is a diagram showing the distortion of transmission path characteristics as a frequency spectrum, and Fig. 4 is a diagram showing the present invention. Block diagram showing another embodiment of the invention. FIG. 5 is a block diagram showing another embodiment of the invention. 1... Analog signal input terminal to which the sample value is transmitted,
2... A/D converter that performs sampling at 2 NHz, 4... Delay circuit, 5... Adder, 6...
・Latch circuit operated by N H2 clock, 8...
A terminal for outputting a signal subjected to waveform equalization, 9...variable filter. DESCRIPTION OF SYMBOLS 10... Reference signal detection circuit, l1... Microcomputer, 12... Latch circuit operated by NHZ clock, 14... Synchronous signal detection circuit, 15... Clock generation circuit, 18... Latch Circuit, 20...Delay circuit,
21...Latch circuit, 23...Latch circuit, 25.
...Latch circuit, 27...Variable filter e, 28...
・Variable filter o. , Pit 3 Figure 4

Claims (1)

[Claims] 1. In a circuit that equalizes the transmission path distortion of a receiver using a transmission system that transmits sample values, the analog signal transmitted by the sample values is converted to a frequency (2 times the sample value rate frequency (NHZ)). A/D that performs A/D conversion with a clock of 2 MHz)
converter and 2 output from the A/D converter.
a first holding means for latching the NHz rate digital signal with an NHz clock; a synchronization signal detection circuit for detecting a synchronization signal from the NHz rate digital signal held by the first holding means; and a synchronization signal detecting circuit that is synchronized with the synchronization signal. NHz
and a clock generation circuit that generates a 2 NHZ clock, an equalization circuit that detects transmission line distortion of the 2 NH rate digital signal output from the A/D converter and corrects the transmission line distortion, and an output from the equalization circuit. A second holding means is provided for latching a signal corrected for transmission line distortion by an NHz clock, and the NHz clock input to the first holding means and the second holding means is an NHz clock generated by the clock generation circuit. A waveform characterized in that a clock is used, the first and second holding means hold the transmitted sample value, and the signal delay amount in the equalization circuit is an even number of clocks with a 2 MHz clock. Equalization circuit. 2. The equalization circuit includes means for delaying a 2 MHz rate digital signal, a circuit for generating an equalization signal for correcting transmission line distortion, and a signal derived from the delay means and the equalization signal. 2. The waveform equalization circuit according to claim 1, further comprising a mixer for performing waveform equalization by mixing. 3. The equalization circuit includes third holding means for latching the 2 NHZ rate digital signal with an NHZ clock;
a delay circuit that delays using a Hz clock; a circuit that generates an equalization signal for correcting transmission path distortion; and a mixer that performs waveform equalization by mixing the signal from the delay circuit and the equalization signal. The waveform equalization circuit according to claim 1, characterized in that it comprises: 4. The circuit that generates an equalization signal for correcting transmission line distortion includes a circuit that exchanges 2-bit serial/parallel digital signals at a 2 NHZ rate, and a circuit that generates equalization signals from each converted 2-bit parallel data. Consisting of a first equalization signal generation circuit and a second equalization signal generation circuit, the 2NH
4. The waveform equalization circuit according to claim 3, wherein said 2-bit serial/parallel conversion circuit operates with the z clock.