JPH0323666A - Dram - Google Patents

Abstract

PURPOSE:To improve flattening properties of a memory ceil part and then reduce layout area by making higher an N<+> part at the bit wire side of an active area than other areas. CONSTITUTION:The bit wire side of N<+> of an active area 5 is made higher than other areas. In this case, Si etching is performed to the entire memory cell except the hit wire contact part, thus obtaining an N<+> part and making higher the part which contacts with a bit wire 3 than the surrounding. Then, a gas oxide film and a lead Wire are formed and then oxide film deposition is performed. Then, oxide film is selectively eliminated to connect a storage node to a transfer gate. Then, after forming a storage node 4 and a cell plate 2, the bit wire 3 is formed.

Description

[Detailed description of the invention] [Industrial application field] This invention relates to DRAM.

[Conventional technology]

Figure 9 is a plan view of a conventional memory cell, Figures 10 to 15
The figure is a sectional view of each manufacturing process along line C-D in figure jg9. In the figure, (1) is the lead wire, and (2) is the cell plate. 13+ is a bit line, (4) is a storage node, (5) is an active area, (6) is an insulating film, (7)
(8) is a photoresist, and (8) is a contact hole.

Next, the manufacturing process will be explained. first. The active area (5) and isolation region are formed using the LOGOS isolation method. Then, form NS/D or deposit an oxide film (10th
figure). Next, the oxide film is selectively removed using a photoresist, polysilicon is formed, and a storage nozzle (4) is formed by selectively etching using the resist (FIGS. 11 to 13).

Next, polysilicon is formed and selectively etched using a resist to form a cell plate (Fig. 14).
After devoting in2, a contact hole {8) to the bit line n is opened, and then a bit line (3) is formed.

[Problem to be solved by the invention]

Conventional DRAM memory cells were constructed as described above, which caused problems such as a step difference occurring at the contact part to the bit line, poor flatness, and a short channel length compared to the layout area. there were.

This invention was made to solve the above-mentioned conventional problems, and aims to improve the flatness of the memory cell portion and reduce the layout area.

[Means to solve the problem]

In the DRAM memory cell according to the present invention, the N portion of the active area on the bit line side is made higher than the other portions.

[Effect]

In the DRAM memory cell of this invention, the N bit line side of the active area is made high, so by stacking the stack capacitors in the low part,
Flatness can be improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a plan view of a DRAM memory cell portion according to an embodiment of the present invention, and FIGS. 2 to 8 are cross-sectional views taken along line AB in FIG. 1 at each process step.

In the figure, (1) is a word line, (2) is a cell plate, {3} is a bit line, {4} is a storage node, and (5) is a cell plate.
) is an active area, (6) is an insulating film, (7) is a photoresist, and (8) is a contact hole.

Next, the process flow will be explained. First, one memory cell is made entirely of Si except for the bit line contact area.
Perform etching. Then, it becomes the N part, and the part that makes contact with the bit line is higher than the surrounding area (@Figure 2 ~
3rd F21). At this time, only the bit line contact portion may be selectively elongated. Next, a gate oxide film, lead layer formation, and oxide film deposition are performed (FIG. 4). Next, the oxide film is selectively removed to connect the storage node and the transfer game. Next - after forming the storage node {4) and the cell plate (2) (see Figures 5 to 7, bit line 13 after forming the oxide film)
(Figure 8).

〔Effect of the invention〕

As described above, according to the present invention, by forming the transfer gate in an inclined part, the channel length can be made longer than the layout area, and the level difference of the contact to the n part of the pit line + is reduced, and its flatness is improved. It has the effect of making you feel better.

[Brief explanation of the drawing]

1 to 8 show an embodiment of a DRAM memory cell according to the present invention, in which FIG. 1 is a plan view and FIGS. 2 to 8 are a 1V? 9 is a plan view of a conventional DRAM memory cell, and FIGS. 10 to 15 are sectional views taken along line CD in FIG. 9 during the manufacturing process. In the figure, (rl) is a word line, and (2) is a cell plate. (
31 is a bit line, 14) is a storage node, (5) is an active area, (6) is an insulation pattern, and {7} is a photoresist. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] In the transfer gate transistor of the DRAM memory cell part, N^+ on the bit line side of the active area
A DRAM characterized in that a portion of the active area is formed at a lower position higher than other active area portions.