JPH0323597A - Rom random write system - Google Patents

Abstract

PURPOSE:To eliminate the unnecessary time for supply and ejection of a read- only memory ROM to improve the throughput of write to the ROM by successively starting the write at the time of mounting the ROM and successively stopping the write at the time of arrival at the address just preceding the write start address. CONSTITUTION:When detecting that ROMs 1-1 to 1-m are mounted, a ROM mounting detecting part 8 registers addresses, which are supplied to ROMs 1-1 to 1-m, in a start address table 5-1 as start addresses correspondingly to ROMs 1-1 to 1-m. The address, data, power, a write pulse, or the like is successively supplied in the cyclic mode to perform write and check of ROMs 1-1 to 1-m; and when the write and check arrives addresses just preceding start addresses registered in the start address table 5-1, the write is stopped to eject ROMs. Thus, the unnecessary time for supply and ejection of ROMs is eliminated to improve the throughput.

Description

[Detailed Description of the Invention] [Summary] The present invention is an automatic machine that automatically supplies and writes ROMs and then automatically discharges them. In order to resolve the decline in processing performance due to time, the purpose is to improve the processing performance for writing to ROM by cyclically sequentially performing write and read checks from the address where the ROM is mounted. [Industrial Application Field] The present invention provides a ROM in which writing is performed randomly.
This is related to the random writing method. In the child industry, FROM. ．． As programmable ROMs such as EFROM are increasingly being used and their capacities are increasing, it is desired to improve the processing capacity of automatic machines. A gag programmer has been known as a high-speed ROM writing device for the purpose of eliminating waste and improving processing performance [problems to be solved by conventional technology and inventions]. In this case, as shown in FIG. 4(a), multiple ROMs are mounted and data is written to them by simultaneously supplying address, data, tS, and a write pulse, and the writing time per one is It is intended to be shortened. However, as shown in Figure 4 (b), for example, after ROMs ■ or ■ are supplied (mounted), writing is started at the same time, so writing is stopped while a large number of ROMs are being supplied. The problem was that 4 hours were wasted. To eliminate this wasted time, see Figure 4 (
As shown in c), it is desired to start sequential writing after supplying the ROM to improve the overall processing capacity. In the present invention, writing and checking are sequentially started upon mounting the ROM, and there is no need to depend on the ROMO loading/unloading time. [Means for solving the problem] The means for solving the problem will be explained with reference to Figure 1. In FIG. 1, a start address table 51 is a table in which, when a ROM to be written is mounted, an address supplied in a vIi ring manner is registered as a start address in association with the ROM.

The ROM mounting detection section 8 detects that a ROM is mounted. (Operation) As shown in FIG. 1, in the present invention, when the ROM mounting detection unit 8 detects the mounting of the ROM, the address supplied to the ROM is set as the start address and the start address table 5-1 is stored. It is registered in association with the relevant ROM, and the address, disk, power supply, write pulse, etc. are sequentially supplied in a circulating manner to write to the relevant ROM.
A check is performed, and writing is stopped and ejected when the address immediately before the start address registered in the start address table 5-1 is reached. Therefore, R.O.
By starting writing and checking sequentially with the implementation of M, and stopping writing when the address reached immediately before writing and checking was started, processing capacity is improved by eliminating wasted time due to ROM loading and unloading. This makes it possible. [Example] First, the concept of the present invention will be explained using FIG. 2. In Figure 2 (A), ROM (#1) to ROM (#8
) in parallel as shown. These ROMs (#1
) or ROM (#8) at the same time, and in the order of mounting, a mounting completion signal is supplied to the AND circuit in the figure to supply power and write pulses to the corresponding ROM. Next, using Figure 2 (mouth), we will explain the operation of Figure 2 (A). In Figure 2 (opening), set the write address to 0000H.
to 7FFF (for 256K ROM) in a circular manner.

fi+ In this state, when the implementation of ROM (#1) is completed, the H level implementation completion No. 13 is installed in the ROM (#1).
I) and supplies power and a write pulse to start writing from address "ooooH", for example.

{2}Next, when the mounting of the ROM (#2) is completed, an H-level mounting completion signal is input to the AND circuit of the ROM (#2), and power and write pulses are supplied to write the address " 0183} Start writing from {”. (3) Similarly, for ROM (#3), start writing from address '03568', for example. In the same way, the posts will be opened in the order in which the implementation is completed.

(4) For the ROM for which writing has started in the above manner, when writing has been done up to the stop address immediately before the start address at which writing started, the mounting completion signal that was being supplied to the AND circuit of the ROM is set to L level;
Stop writing.

And then discharge.

As described above, by sequentially starting writing from the time when ROM mounting is completed and sequentially stopping writing when writing has been performed to the address immediately before starting writing,
There is no need to wait for writing while multiple ROMs are installed, making it possible to improve the efficiency of the writing process. Next, the structure and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 and 3. In FIG. 1, ROM (#1) 1-1 to ROM (#m) l-
m is m ROMs, FROM, EPROM
etc.

Lever 2-1 to lever 2-m are ROM (#1) I
-X or ROM (#m)1 This is a lever with a contact that can be closed/opened by operating it when mounting/ejecting -m. The switch sections 3-1 to 3-m are connected to a power source (VPF, vc
c) and write pulse W, etc. in ROM (#I)]
-J or ROM (#m)1 This is to supply or not supply to -m. The memory 5 is a memory for storing programs, data, etc., and is provided with a start address table 5-1 according to this embodiment.

Address register 6 holds the address notified from CPU13, and ROM (#l)1-1 is not LROM.
(ttm)1 This is a register for supplying to m.

The data register 7 holds the data notified from the CPU13, and stores the data in the ROM (#1) 1-1 or ROM (#1).
This is a register for supplying m>l −m. The ROM actual vt detection unit 8 detects that ROM(#l)l-1 to ROM(#m)1-m is installed, and the ROM(#l)l-1 to ROM
This is to detect the closed state of levers 2-1 to 2-m that are operated when mounting M (#m)l-m. ? The OM use control section 9 controls the switch sections 3-1 to 3-m.
ROM (#l)l-1 or ROM (#l) by controlling
m) It supplies power, write pulses, etc. to the implemented one of 1-m. Operation SW & display section 10
is a display unit that displays operation switches that give various operation instructions and the current writing status. The POWER control unit 11 supplies Mfl(V■
, ycc, etc.). The write pulse control unit 12 controls ROM (#1) 1-1 to ROM (#1) 1-1 to ROM (
#m) Controls the write pulse W supplied to 1-m.

The CPU 13 performs write control based on the program stored in the memory 5. Next, the operation of the structure shown in FIG. 1 will be explained in detail using the flowchart shown in FIG.

FIG. 3(a) shows the start address table 5-1. This is provided in the memory 5 in FIG.
This is a table that registers the start address at which writing started in association with the ROM. In Figure 3 (opening), ■ reads the master data. This indicates that data to be written to the ROM is read from an external storage device (not shown) and expanded on the memory 5 in FIG. @ writes the write address and sends the data. This is shown in Figure 1 CPLI
13 sends the address to address register 6 and data to data register 7, respectively, and I? OM (#1
)1-1 to ROM (tFm)l -m. @ determines whether or not the i-th (1=1 to m) socket has a ROM. This means that the contact point of the i-th level 2-1 of the levers 2-1 to 2-m in FIG. 1 is closed (RO
M is implemented f! 3i) is detected. If YES (ROM (#i)
(if l-i is implemented), execute @. N
If O, execute [phase]. [Phase] determines whether or not writing is in progress. If YES (when the start address is registered in the corresponding ROM in the start address table 5-1), since writing is already in progress, [Phase] is used. ]. If NO (if the entry of the corresponding ROM in the start address table 5-1 has been cleared), it means that writing is not in progress, so execute step (2). ■ registers the current write address as the start address in the start address table 5-1, and turns on the t source (V, c, ■,,) and the write pulse W.
To 《supply》. This is the Suinochi part 3-1 in Figure 1.
This represents turning on the power supply (Vcc, Vee) and the write pulse W to the ROM (#l)l-i. [Stock] determines whether m pieces of Cheseok have been completed.
If YES, execute [phase]. In case of NO, 1=1+11, . , No -na or [Phase] Repeatedly execute the ROM set (implementation) by the processing of 6 or more O or O, and registers the start address at the start address table 5-1 at the time of detection. [Stock] writes. This represents writing data to ROM. ■ Performs a lead check. This is the [? This indicates that OM is read and checked to see if correct data has been written. [Phase] determines whether the i-th (i-1 to m) write has been completed. This is ROM (#j)1-
For i (i-1 to m), this indicates that the current write address refers to the start address table 5-1 to determine whether or not the current write address is the address immediately before the start address and writing has been completed. If YES, the corresponding start address in the start address table 5-1 is cleared in [phase] and V cc-. V PP, W, OF
Set to F and execute [phase]. If No, execute [phase]. [Phase] determines whether m changes have been completed. If YES, execute [Phase]. N
In the case of O, repeat t=i+lL and [phase] to ◎ in ■. Completion of writing to the ROM is detected by the above processes from [phase] to ◎. ◎ increases the write address by 1. (2) determines whether the work is interrupted or not. This determines whether or not there is a command from the operator to interrupt the work. YES
If , it ends. If NO, steps 0 and subsequent steps are repeated.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of one embodiment of the present invention, FIG. 2 is a conceptual explanatory diagram of the present invention, FIG. 3 is a flowchart explaining the operation of the present invention, and FIG. 4 is an explanatory diagram of the prior art. In the figure, 1-1 to 1-m are ROM, 2-1 to 2-
m is a lever, 3-1 to 3-m are switch parts, 5 is a memory, 5-1 is a start address table, 6 is an address register, 7 is a data register, and 8 is l? OM mounting detection section, 9 is ROM usage control section, I1 is POWER system
In the C part, l2 represents a speech pulse control part, and l3 represents a CPU. 〔Effect of the invention〕

Claims (1)

[Claims] In a writing method in which writing to a ROM is performed randomly, when a ROM to which writing is to be performed is mounted, an address that is supplied in a circular manner to multiple ROMs at the same time is set as the start address of the ROM. A start address table (5-1) to be registered is provided, and when a ROM is installed, the start address is registered in this start address table (5-1) in association with the ROM, and the address, data, power supply and write information are The present invention is characterized in that it is configured such that writing to the ROM is performed sequentially by supplying a pulse, etc., and writing is stopped when the address immediately before the start address registered in the start address table (5-1) is reached. ROM
Random writing method.