JPH03235298A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable a normal operation with high probability by respectively providing more than three circuits for programming a spare row or spare column and spare address, and more than three spare decoder circuits to be connected with this circuit in a spare memory cell. CONSTITUTION:When one defractive bit is generated in a memory cell Mc13, a redundant circuit is made operable state by a master circuit 14 at the time of wafer process. Simultaneously, the address of a row including fault defecting bits and the addresses of more than two rows adjacent to the row are programmed to plural address programs 15. Thus, not only when the address of the row including the fault generating bit but also when designating the addresses of the row adjacent to the address, a spare decoder DE is operated and respective corresponding space rows are selected. Thus, when the DE 16 is operated, a normal decoder 12 is turned to an operation inhibiting state by a normal disable circuit 18, and any access is performed to the Mc16 defect. Thus, the memory of the normal operation can be obtained be obtained can be obtained with high probability.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and in particular, a method for converting a defective bit generated in a chip and a plurality of rows or columns adjacent to the defective bit into a plurality of spare rows or columns. Regarding redundant circuits to be replaced.

[Conventional technology]

In a semiconductor memory device, when a bit defect due to a pattern defect, crystal defect, etc. occurs in a chip during wafer processing, the defective bit is replaced with a normally operating spare bit to repair the memory chip. This chip relief is performed by a redundant circuit that has been inserted into the chip in advance.

FIG. 2 shows an address selection circuit and a redundancy circuit of a conventional semiconductor memory device.

In the figure, (21) is an address buffer (22) which is a decoder circuit in normal operation, (23) is a memory cell, and (2) is a decoder circuit in normal operation.
4) is a master circuit for enabling the redundant circuit, (25) is an address program circuit for specifying a row or column to be replaced, (26) is a spare decoder circuit, (27) is a spare memory cell, (28) is a normal disable circuit for disabling the normal decoder circuit when the redundant circuit is used.

In normal row or column selection in which no defective bits occur in the memory cell, the signal from the address buffer is decoded by the decoder circuit (22) to select one row or column in the memory cell. ing. On the other hand, if a defective bit occurs in a memory cell, a redundant circuit is used to select a spare row or column, and at the same time prohibit selection of a normal row or column. That is, at the wafer process stage, the redundant circuit is enabled by the master circuit (24), and the address of the row or column containing the defective bit is programmed into the address program circuit (25). As a result, even if a row or column address containing a defective bit is selected, the normal decoder circuit (22) is disabled by the normal disable circuit (28), and at the same time, the spare row or spare memory cell in the spare memory cell is disabled. Column is selected. At this time, only one spare row, spare row, or spare column is selected for one row or column containing a defective bit.

If the cause of the defective bit is present only in the generated defective bit, the above spare conversion can be performed without any problem. However, if the cause of the defective bit occurrence is not only in the bit where the defect occurred, but also in the bits surrounding it, and those bits are not recognized as defective at the time of defect detection, then such a hit Semiconductor memory devices containing such devices operate unstablely and are potentially dangerous.

[Problem to be solved by the invention]

In the conventional redundant configuration of semiconductor memory devices, one row or column containing a defective bit is replaced with only one spare row or column. However, causes of defective bits such as pattern defects and crystal defects may also occur around the defective bits, and it is not possible to guarantee that all repair chips using conventional methods will operate normally. There was a problem.

This invention was made to solve the above-mentioned problem, and even when the cause of defective bits is also present in peripheral bits as mentioned above, it is possible to return to a semiconductor memory device that operates normally with a higher probability. The purpose is to make relief possible.

[Failure to solve the problem]

A semiconductor memory device according to the present invention is provided with at least three or more spare rows or spare columns in a spare memory cell, and at the same time, a program circuit that can program at least three or more spare addresses and a spare decoder circuit that is connected to each of them. It is something that

[Effect]

In the semiconductor memory device according to the present invention, in spare conversion when a defective bit occurs, the row or column including the defective bit and at least two or more adjacent rows or columns are simultaneously converted into spares. To obtain a semiconductor memory device that operates normally with a higher probability by replacing many of the bits within the distribution range even when the cause of occurrence is distributed to bits surrounding a defective bit.

(Example) An embodiment of the invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory device showing an embodiment of the present invention. In the figure, (11) is an address buffer, (12) is a decoder circuit in normal operation, and (13) is a decoder circuit in normal operation.
is a memory cell, (14) is a master circuit for enabling the redundant circuit, (15) is an address program circuit for specifying the address of the row to be replaced, (1
6) is a spare decoder circuit, (17) is a spare memory cell, and (18) is a normal disable circuit for disabling the normal decoder circuit when the redundant circuit is used.

Next, the operation of this invention will be explained.

If a single defective bit occurs in a memory cell, during wafer processing, the master circuit enables the redundant circuit and at the same time identifies the address of the row containing the defective bit and at least two or more rows adjacent to that row. The address of 1 is programmed into a plurality of address program circuits (15).

As a result, the spare decoder operates not only when the address of the row containing the defective bit is specified, but also when the addresses of several adjacent rows are specified, and the corresponding spare row is selected. Become so. Furthermore, when the spare decoder operates as described above, the normal disable circuit disables the normal decoder from operating, so that the row containing the defective bit in the memory cell and the rows around it are not accessed.

In the above embodiment, a redundant configuration using a spare row is shown, but a redundant configuration using a spare column or both a spare row and a spare column may be used.

〔Effect of the invention〕

As described above, according to the present invention, in a redundant configuration of a semiconductor memory device, not only a row or column containing a defective bit but also a plurality of rows or columns adjacent to the row or column can be converted into spares at the same time. Therefore, even if the cause of defective bits affects adjacent bits, a normally operating semiconductor memory device can be obtained with a higher probability.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a redundant portion of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a redundant portion of a conventional semiconductor memory device. In the figure, (1
1) is an address buffer, (12) is a decoder, (13
) is a memory cell, (14) is a master circuit, (15) is an address program circuit, (16) is a spare decoder,
(17) is a spare memory cell, and (18) is a normally disabled circuit.

Claims (1)

[Claims] A semiconductor memory device characterized in that when a row or column containing a defective bit is replaced with a spare row or column, a plurality of rows or columns adjacent to the row or column containing the defective bit are also replaced at the same time.