JPH03235295A - Non-volatile storage device - Google Patents

Abstract

PURPOSE:To decrease the number of leaked current paths generating a memory cell to be connected to a bit line, and to stablize operations by commonly connecting only the source of the memory cell to be connected to a word line and connecting an MOS transistor at an interval with a ground potential. CONSTITUTION:At the time of write, a first address select signal 2 is selected and at such a time, a first MOS transistor Tr1 is conducted. At such a time, a second address select signal 5 is not selected and a second Tr4 is not conducted. When a bit line B1 is turned to 9V and the word line is turned to 12.5V, a memory cell 1.1 is selected and written. Then, memory cells M3.1 and M4.1 connected to the line B1 cuts the path from the source to a ground potential 3 by not conducting Tr4, and the leaked current is not generated in this path. Similarly, at the time of read, the Tr4 is not conducted and the leaked current is not generated. Thus, the number of leaked current paths to the ground potential to be connected to one bit line is decreased and both write/read operations can be stablized.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a non-volatile memory device such as an EPROM using a FAMO5 type memory element in which information can be written electrically, and particularly to a non-volatile memory device such as an EPROM. It provides an array structure of elements.

[Conventional technology]

Conventionally, this type of nonvolatile memory device has generally had an array structure of memory elements as shown in FIG. FIG. 2 is a perspective view of FAMO5 type memory elements arranged in a matrix with m rows in the row direction and one column in the column direction.
(W!) to (Wm) are word lines that divide rows, (B1
) to (Bn) are bit lines that divide columns, and memory elements (hereinafter referred to as memory cells) CM (1-1)) to (M (m,
m)) is located. Also, each memory cell I
The lower potential side terminal (hereinafter referred to as source) is at ground potential (3
)It is connected to the.

Next, I will explain about L's work + tricks. To write information to a memory cell, set the voltage of the unconnected drain of one bit line to about 9V, and set the word line]? :IZ5V the connected gate
This is achieved by the fact that hot carriers are generated in the channel region of the memory cell, and the hot carriers are accumulated in the floating gate. That is, when writing information to the memory cell (M(1,1)) in FIG. 2, the bit line (B1) is set at 9Vl and the word line (Wl) is set at IL5V.

After the desired information has been written as described above, f times are read. In this case, the bit line (Bl) is set to about 1V and the word line (Wl) is set to about 5V. From this, when the memory cell (M(1,1)) is written, the threshold voltage is high, so lζ becomes non-conductive. If the reverse f4 is not written, the threshold voltage is low, so it becomes conductive. At this time, information can be read accurately due to the conduction current generated.

[Problem to be solved by the invention]

Since the array structure of conventional non-volatile memory devices was formed in one piece as described above, a large number of memory cells are connected to one bit line, and the source of the memory cell is at ground potential. Even if the leakage current generated by one memory cell is small, the total leakage current from one bit line to the ground potential becomes quite large, and this reduces the write efficiency by There were problems such as a decrease in operating margin.

The present invention was made to solve the problems such as the leakage from one bit line to the ground potential.
The purpose of this invention is to improve a non-volatile memory device that reduces current and improves operational stability.

[Means and effects for solving the problem] The memory array structure according to the present invention connects at least one word line with one wood cut in order to reduce the leakage current path caused by the memory cell connected to one bit line. The sources of only the memory cells are connected in common, and a MOS transistor is inserted between the memory cells and the ground potential to reduce the leakage current path from the bit line to the ground potential.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1ζ.

FIG. 1 is a perspective view of a nonvolatile memory device that is an embodiment of the present invention, and for simplicity, shows a memory array structure of four rows and four columns. In the figure, (Bl) to (B4) are bit lines, (Wl) to (W4) are word lines, and the memory cell determined by the intersection of the bit line and word line is (M(1・1)). ~(M(4,4)).

In addition, the sources of the memory cells I (M(1,1)) to (M(2,4)) connected to the word lines (Wl) and (W2) are commonly connected, and this common connection terminal is connected to the ground potential (3). A first MOS transistor (1) is inserted between E and E. Here, the gate input signal of the first MOS transistor (1) is sent to the memory cell I and the first address selection signal (2
), and memory cells (M(3,1)) to (M(4,4)) connected to word II (W3), (W4)
Commonly connect the sources of , and connect this common connection terminal to the ground potential (
During 3), the gate input signal of the second MOS transistor (4) is the second address selection signal (5) for memory cell selection. Note that the address selection signals (2) and (5) are different from each other.

Next, operation E will be explained. Memory cell (M(1,1
)) When writing and reading data, we will explain one problem. When writing first, address selection signal (2)
is selected and makes the first MOS transistor (1) conductive. At this time, the address selection signal (5) becomes non-selected and the second MOS transistor (4) becomes non-conductive.

Here, bit 1i (Bl) is about 9V, word IN is 1
When the voltage reaches about 25V, the memory cell (M(1,1)) is selected and written. At this time, bit II (Bl
) connected to memory cells (M(3,1)) and (
Since the path from the M(4,1) method source to the ground potential (3) is cut off when the second MOS transistor (4) becomes non-conductive, no leakage current occurs through this path. . As a result, a sufficiently high voltage is applied to the memory cell (M(1,1)) without a drop in level, and sufficient write efficiency can be obtained.

Also, in the case of reading, the address selection signal (2)
is selected and makes the first MOS transistor (1) conductive. At this time, the address selection signal (6) is non-selected.
The second MOS t-transistor (4) becomes non-conductive.

Here, the bit line (B1) is about 1V, the word line (Wl
) becomes about 5V, the memory cell (M(1,1)) is selected, and if it is written, it becomes non-conductive because the threshold voltage is high. On the other hand, if it is not written, the threshold voltage is low and it becomes conductive. At this time, the memory cells (M(3,
1)) and (M(4,1)), the path from its source to the ground potential (3) is the second MOS transistor (4).
Since this path is disconnected by becoming non-conductive, no leakage current occurs.

This reduces the amount of current generated by the current paths of other memory cells in the current generated when the memory cell becomes conductive, allowing accurate reading.

Note that in the above embodiment, the first. Second transistor (1)
, (4) has been described for the case of a MOS transistor, but of course, the same effect can be obtained with either a P-channel type or an N-channel type by operating as described in the previous section.

〔Effect of the invention〕

As described above, according to the present invention, the memory cell array structure is divided into source parts, and the source is selected by the address selection signal, so that the leakage current path to the ground potential connected to one bit line is reduced. Since this decreases, there is an effect that a nonvolatile memory device that is stable in both write operations and read operations can be obtained.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing a memory cell array structure of a nonvolatile memory device according to an embodiment of the present invention, and FIG. 2 is a perspective view showing a memory cell array structure of a conventional nonvolatile memory device. In the figure, (1) is the first MOS transistor, (
(3) is the ground potential, (4) is the first address selection signal,
) is the second MOS l-transistor, (5) is the second address selection signal, (Bl - Bn) is the bit line, (Wl
~Wm) is the word line, (M(1,1) ~M(m,
n)) indicates a memory cell. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] Diffusion regions having a conductivity type opposite to that of the substrate are disposed on the substrate at regular intervals, the upper portions of the diffusion regions are covered with an insulating film, a charge storage layer is disposed on the spacing and above the insulating film, and a charge storage layer is disposed on the top of the charge storage layer. In a nonvolatile memory device in which memory elements capable of electrically recording information and having at least a structure in which electrodes are arranged are arranged in a matrix in the row and column directions, the low potential side terminals of the memory elements are connected to at least one or more terminals. A first MOS transistor is commonly connected along the row line direction and inserted between the commonly connected low potential side terminal and ground potential, and the first MOS transistor
The gate input signal of the S transistor is used as a first address selection signal, and a second MOS transistor is inserted in the same manner as above for at least one row line different from the row line, and the second MOS transistor is 1. A nonvolatile memory device characterized in that a gate input signal of a MOS transistor is a second address selection signal different from the address selection signal, and low potential side terminals of a storage element are at least two different terminals.