JPH03235139A - Memory controller - Google Patents

Abstract

PURPOSE:To allow the high speed function of a D-RAM to function effectively by enhancing the address locality of a write cycle, in the case the D-RAM is utilized for a memory unit. CONSTITUTION:The computer system is provided with an arithmetic control part 10, write buffer 11, write cycle determining part 12, selector part 13, bus interface 14, bus 15, and a memory unit 16. In such a state, in the case a write operation of data is executed to the memory unit 16 for which a D-RAM is used, such a write cycle request as the address locality becomes high is executed. In such a way, a high speed function of the D-RAM can be displayed effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a memory control device used, for example, in a microcomputer system.

(Prior Art) Conventionally, for example, in a microcomputer system, a cache memory has been used to speed up access to main memory by a processor (CPU). In such systems, the proportion of write cycles in memory cycles when main memory is accessed tends to be higher than in systems that do not use cache memory. For this reason, in a method using a cache memory, it is necessary to speed up the write cycle.

By the way, when using D-RAM (dynamic RAM) as main memory, there is a page mode function or static column function.
) mode function to speed up continuous access within the same row address. however,
If the address locality of the write cycle (probability of consecutive accesses within the same row address) is low, there is a problem that the speed-up function of the RAM does not function effectively as described above.

(Problems to be Solved by the Invention) For example, in a system using a cache memory, it is necessary to speed up the write cycle.

However, the speed-up function of the conventional D-RAM is not necessarily effective when the address locality of the write cycle is low.

An object of the present invention is to be able to improve the address locality of write cycles in memory cycles,
The object of the present invention is to provide a memory control device that can speed up memory access as a result.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a method for determining the next write cycle to be executed so as to improve the address locality of the write cycle when a write cycle request for a memory unit occurs. A memory control device comprising determining means for determining an address of a request.

With such a configuration, the memory unit has, for example, D-R
When AM is used, the speed-up function of DRAM can be enabled by increasing the address locality of write cycles.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a computer system according to the same embodiment. This system includes, for example, a calculation/control unit 10 of a microprocessor. a write buffer 11 that stores addresses and data of write cycle requests;
A write cycle determining unit (determining means) 12 for determining the address of the write cycle request to be executed next, a selector unit 13 for selecting the address and data of the write cycle request from the write buffer 11, a memory unit 16, and a bus 15. It is equipped with a bus interface 14 through which addresses and data are transferred.

The write cycle determining unit 12 determines the previously determined address (
This address is compared with the address of the write cycle request from the write buffer 11, and an address that increases the address locality of the write cycle is determined. The selector unit 13 selects the address and data of the write cycle request in response to the notification from the write cycle determination 112. The memory unit 16 has a memory made of, for example, a D-RAM, and has a high-speed function such as a page mode function or a static column mode function.

Next, the operation of this embodiment will be explained.

First, an arithmetic/control unit 1 (l) outputs a predetermined address and data as a write cycle request when it becomes necessary to write data to the memory unit IB during execution of data processing based on a predetermined program. The address and data output from the arithmetic/control unit 10 will be stored in the write buffer yll.The write buffer 11, as shown in FIG.
~Aa and an area for storing data D1 to Dfl. If there is no empty area in the write buffer 11, the write cycle request of the arithmetic/control unit IO is placed in a standby state.

When the address and data from the calculation/control unit 10 are stored in the write buffer 11, the write cycle determination unit 12
determines the write cycle request to be executed next to the currently executing write cycle. That is, the write cycle determining unit 12 compares the address stored in the write buffer 11 with the previously determined address, determines an address with high address locality, and notifies the selector unit 13 of the address. The previously determined address is the address of the write cycle request currently being executed. Address locality means that the probability of consecutive accesses within the same row address is high in high-speed functions such as the D-RAM page mode function or static column mode function. There is a high degree of consistency between the upper addresses of

The selector unit 13 selects the address and data of the write cycle request notified from the write cycle determining unit 12 from the write buffer 11, and transfers the address and data to the bus interface
Output to 4. The bus interface 14 will transfer the address and data from the selector section 13 to the memory unit 16 via the bus 15.

In this manner, when a write cycle request is generated from the arithmetic/control unit 10, the address and data of the write cycle request are transferred to the memory unit 16. Predetermined data is written into the memory unit 1B at the address of the write cycle request.

In this case, in the present invention, among the write cycle requests of the arithmetic/control unit 10, an address having high address locality with respect to the write cycle request currently being executed is selected and transferred to the memory unit 16.

Therefore, in the memory unit 16 using D-RAM, for example, a high-speed function such as a page mode function or a static column mode function becomes effective in response to a write cycle request with high address locality.

[Effects of the Invention] As detailed above, according to the present invention, for example, D-RAM
When performing a data write operation to a memory unit using a memory unit, it is possible to make a write cycle request that increases address locality. For this reason,
For example, the speed-up function of D-RAM can be effectively utilized. As a result, even if the ratio of write cycles to memory cycles increases in a system using a cache memory, for example, it is possible to speed up the write cycles and, as a result, speed up memory access.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a computer system according to an embodiment of the present invention. 10... Arithmetic/control unit, 11... Write buffer,
12...Write cycle determining section, 13...Selector section, 1B...Memory unit.

Claims (2)

[Claims] (1) When a write cycle request to a memory unit occurs, a buffer means for storing the requested address and data; and based on the address stored in this buffer means, the address locality of the write cycle is high. A memory control device comprising: determining means for determining the address of a write cycle request to be executed next time so that the address and data determined by the determining means are transferred to the memory unit. Device. (2) When a write cycle request is made to a memory unit, the buffer means for storing the address and data of the request is compared with the address stored in this buffer means and the address of the previous write cycle request. , determining means for determining the address of the write cycle request to be executed next so that the address locality of the write cycle is high based on the comparison result, and storing the address and data determined by the determining means in the memory unit. 1. A memory control device comprising: a transfer means for transferring data.