JPH03228292A - Gaas semiconductor storage - Google Patents

Abstract

PURPOSE:To improve the resistance to a soft error without deteriorating the noise margin by setting the cathode potential of a Schottky diode added to a memory cell at a level higher than the source power supply of a driver FET of the memory cell. CONSTITUTION:A 1st Schottky diode 13 uses a 1st output node 8 and a 1st medium node 16 as an anode and a cathode respectively. A 2nd Schottky diode 14 uses a 2nd output node 9 and the node 16 as an anode and a cathode respectively. Then a 3rd load element 15 is connected between the node 16 and a 1st power supply. In such a constitution, the capacity can be added to the storage nodes 8 and 9 without substantially deteriorating the voltage amplitude of the data on a memory cell. Thus it is possible to improve the resistance to a soft error without deteriorating the noise margin.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gallium arsenide semiconductor memory device, and particularly to improvements in the circuit configuration of its memory cells.

[Conventional technology]

Figure 2 shows, for example, the 1981 IEDM (Inte
rnationalElectron Device
FIG. 3 is a circuit configuration diagram of a memory cell in a conventional gallium arsenide semiconductor memory device described on page 83 of the preliminary collection.

In the figure, 1 and 2 are normally-on metal semiconductor field effect transistors (hereinafter, metal-semiconductor field effect transistors are abbreviated as MESFETs), and 3 to 6 are normally-off MESFETs. Normally-on type MESF
ETI and normally-off type MESFET3 load normally-on type MESFET1, and normally-off type MESFET1
FE73 is the driver and node 9 is the input node. node 8
The normally-on type MESFET I has its drain connected to the power supply 7, and its gate and source are commonly connected to the drain 8 of the normally-off type MESFET 3. Further, the normally-off type MESFET 3 has its gate connected to the input node 9 and its source grounded. Similarly, the normally-on type MESFET 72 and the normally-off type MESFET 4 are / -? T) Off type ME
SFET2 is the load, normally-off MESFET4 is the driver, and node 8 is the input node. A second E/D inverter circuit with node 9 as an output node is configured, and the normally-on type MESFET 2 has its drain connected to the power supply 7, and its gate and source are common and is a normally-off type MESFET.
It is connected to the drain 9 of SFET4. Further, the normally-off type MEsFET 4 has its gate connected to the input node 8 and its source grounded. The first and second E/D inverter circuits have a configuration of a flip-flow 21 circuit in which the input and output of each are cross-connected. Furthermore, nodes 8 and 9 serve as storage nodes where data is stored. The normally-off MESFET 5 is a transfer gate connected between the storage node 8 and the bit line 10, and the word line 12 is input to the gate. Similarly, normally-off MESFET 6 is a transfer gate connected between storage node 9 and bit line 11, and word line 12 is input to its gate.

Next, the operation will be explained.

When the memory cell is in a non-selected state, the word line 12 is at a low level, and the transfer gates 5 and 6 are both non-conductive, so that the memory cell is separated from the bit lines 10 and 11. At this time, high and low pairs of data are held in the memory cell by the following mechanism.

FIG. 3 is a diagram showing the transfer characteristics of the first or second E/D inverter, in which the solid line 17 is the transfer characteristic of the inverter, and the broken line 18 is the solid line 17 folded back symmetrically with respect to y=x. It is a curve.

Since the driver FET becomes non-conductive when the input is at a low level, the output is pulled up to a high level by the load FET. Here, if the potential of the power supply 7 is set to 1.5V, the high level of the output is about to be raised to 1.5V, but in reality, the output is input to the gate of the other inverter, so the gate and source of the driver FET Due to the presence of a parasitic Schottky diode formed between them, the Schottky barrier height is clamped at approximately ΦB, and this value is normally approximately 0.6V. Next, when the input level to the inverter rises and exceeds the threshold voltage of the drive FET, the driver FET becomes conductive, and the current drive capacity of the driver FET is usually set to be several times larger than the current drive capacity of the load FET. Therefore, the output level rapidly decreases to Low level. When the input level to the inverter further increases, the output level is gradually raised due to the presence of a parasitic Schottky diode formed between the gate and drain of the driver FET. In this way, the first or second E when the memory cell is not selected is
The transfer characteristic of the /D inverter is as shown by the solid line 17 in the figure. Furthermore, since the inputs and outputs of the first and second E/D inverters are cross-connected to each other, the potentials of the storage nodes 8 and 9 in the non-selected state are the solid line 17 and the broken line 1.
It is determined by the intersection points A and B of 8. That is, the storage nodes 8 and 9 hold one pair of high and low data.

Next, when the memory cell is brought into a selected state, the word line 12 becomes high level during reading, the transfer gates 5 and 6 are made conductive, and the held data is read onto the bit lines 10 and 11. The data read onto these bit lines is further amplified by a subsequent circuit and output to the outside. To write data to a memory cell, the word line 12 is set to H1gh level to put the memory cell in a selected state, and the bit lines 10 and 11 are strongly set to High level and the other to Low level by the write circuit. Write the data on the line to the storage node of the memory cell.

[Problem to be solved by the invention]

Since the memory cell in the conventional gallium arsenide semiconductor memory device is configured as described above, the high level of data held in the memory cell is limited by the height of the Schottky barrier between the gate and source of the driver FET 3 or 4. The voltage will be about 0.6V. For this reason, the voltage amplitude of the data held by the memory cell is small, and as will be explained below, there is a problem in that soft errors are likely to occur due to the incidence of alpha rays.

In other words, MESFETs generally have an active region doped with impurities on a gallium arsenide semiconductor substrate, but when this active region is at a high potential, electrons generated in the substrate by the incidence of α rays are absorbed by this active region. collected into the active area at high potential. Therefore, the high-side storage node potential of the memory cell decreases. The amount of this decrease is usually more than 0.6V, and therefore, due to the incidence of α rays on the High side storage node, the potential of the High side storage node decreases from the potential of the Low side storage node, causing data inversion. . This becomes unrecoverable until the next write.

Therefore, in order to increase the resistance of the memory cell to the incidence of α rays and reduce the probability of data inversion, Schottky diodes 13 and 14 are connected between storage nodes 8 and 9 and GND in the forward direction, as shown in FIG. One possible method is to increase the capacity of the storage nodes 8 and 9 by inserting them into the storage nodes 8 and 9. That is, by increasing the capacitance of the storage node, the amount of change in potential for the same amount of charge collection is reduced, and the soft error occurrence rate is reduced. However, this method has the following problems.

First, for example, in FIG. 4, if node 8 holds data at H1gh level and node 9 holds data at low level, there is a connection between the gate and source of driver FET 4 between storage node 8 on the High side and GND. In addition to the parasitic Schottky diode, the added Schottky diode 14 is connected in parallel.
The Schottky current of the Schottky diode to node 8 increases, and the potential of node 8 decreases. In particular, in memory cells, the current supply capacity of normally-on type MESFET I and 2 of the load is reduced as much as possible in order to reduce power consumption, so the substantial area of the Schottky diode connected between node 8 and GND is The potential of node 8 decreases significantly due to the increase in . When the potential of node 8 on the High side decreases, the voltage amplitude of the data held in the memory cell decreases, which not only does not improve the effect of reducing the soft error rate by adding a diode, but also reduces the noise margin. .

In this way, conventional memory cells are prone to soft errors caused by α rays, and even if capacitance is added as shown in Figure 4, not only will the data voltage amplitude decrease and the effect will not improve, but the noise margin will also decrease. There was a problem with the decline.

This invention was made to solve the above-mentioned problems, and it adds capacity to the storage node without reducing the voltage amplitude of data held in the memory cell, thereby making the memory cell highly resistant to soft errors. An object of the present invention is to obtain a gallium arsenide semiconductor device having the following properties.

[Means to solve the problem]

A gallium arsenide semiconductor memory device according to the present invention is provided between each storage node inside a memory cell and an intermediate node having a higher potential than the power source of the source of a driver FET, with each storage node serving as an anode; Connect a Schottky diode with the cathode of
Further, a load element is connected between the intermediate node and the source power source of the driver FET.

[Effect]

In this invention, with the above configuration, the potential of the cathode of the Schottky diode added to the memory cell is made higher than the power supply of the source of the driver FET of the memory cell. Capacitance can be added to the node, and as a result, soft error resistance can be increased without reducing noise margin.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of a memory cell of a gallium arsenide semiconductor memory device according to an embodiment of the present invention, in which the same reference numerals as in FIGS. 2 to 4 indicate the same or corresponding parts, and 15 is a normally-on MESFET. The cathodes of Schottky diodes 13 and 14 in the circuit diagram shown in FIG. It has become something that has been done.

Next, the operation will be explained.

When the memory cell is in an unselected state, the word line 12 is low.
Since the transfer gates 5 and 6 are in a non-conductive state, the storage node of the memory cell is electrically disconnected from the bit line.

At this time, the storage node of the memory cell holds one pair of data (high and low) based on exactly the same principle as in the conventional example. Assuming that high level data is stored in node 8 and low level data in node 9, in the conventional example, the storage potential of node 8 decreases due to the current flowing from node 8 to GND via Schottky diode 14. However, in the present invention, the node 16 is not directly connected to GND, but has a higher potential than GND because the load element 15 is connected between it and GND, and therefore the potential of node 8 decreases. Prevented.

In other words, normally a Schottky diode has a property that the current increases exponentially with respect to the bias voltage under bias conditions of the Schottky barrier height.
The rate of increase in current is high, and therefore the current flowing through Schottky diode 14 decreases rapidly as the potential at intermediate node 16 increases. The High level of the node 8 is determined by two factors: the current flowing through the Schottky diode 14 and the current flowing to GND through the gate of the driver FET 4. By increasing the potential of the intermediate node 16, the current flowing through the Schottky diode 14 By suppressing the current below the current flowing through the gate of the driver FET 4, the drop in the potential of the node 8 due to the addition of the Schottky diode 14 can be suppressed to a small level. The potential of node 16 is adjusted by the normally-on type MESFE of the load.
This can be done by changing the current driving force of 715, for example by changing its size. however,
Since the capacitance value added by the Schottky diode increases as the bias voltage between the anode and the cathode increases, it is necessary to select the optimum value of the potential of the intermediate node 16 from both the voltage amplitude of the storage node and the capacitance value added.

Note that write and read operations are also exactly the same as in the conventional example.

In this embodiment, by connecting the load FET 15 through the intermediate node 16, the potential of the intermediate node 16 can be made higher than the GND level, and the voltage amplitude of the storage node of the memory cell can be almost reduced. Therefore, the soft error resistance against α rays can be efficiently increased without reducing the noise margin.

In the above embodiment, a normally-on MESFET is used as a load element of a memory cell, but other load elements such as a resistance element may be used, and similar effects can be obtained.

Furthermore, in the above embodiment, a normally-on MESFET was used as the load element connected between the cathode of the added Schottky diode and GND. However, it produces the same effect.

[Effects of the Invention] As described above, according to the gallium arsenide semiconductor memory device according to the present invention, each storage node inside the memory cell,
A Schottky diode having each storage node as an anode and the intermediate node as a cathode is connected between an intermediate node having a potential higher than the source power supply of the driver FET, and further between the intermediate node and the driver FET.
Since I connected a load element between the ET source power supply,
Capacitance can be added to the storage node without reducing the voltage amplitude of the data in the memory cell, and as a result, the sost error resistance against alpha rays can be efficiently increased without reducing the noise margin. be.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a memory cell of a gallium arsenide semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a memory cell of a conventional gallium arsenide semiconductor memory device, and FIG. 3 is a diagram of a conventional gallium arsenide semiconductor memory device. FIG. 4 is a diagram showing the transfer characteristics of an E/D inverter in a memory cell of an arsenic semiconductor memory device, and is a circuit configuration diagram when a diode is added to a memory cell of a conventional gallium arsenide semiconductor memory device. In the figure, 1.2 and 15 are normally-on MESFETs, 3
~6 is a normally-off MESFET, 7 is a power supply, 8.9
is a storage node, 10.11 is a bit line, 12 is a word line, 13.14 is a Schottky diode, 16 is an intermediate node, 17 is a transfer characteristic of an E/D inverter, and 18 is a curve made by making 17 symmetrical with respect to y=x. , A, and B are stable points. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A first normally-off MESFET formed on a gallium arsenide semiconductor substrate, whose gate is a first input node, whose drain is a first output node, and whose source is connected to a first power supply; a first inverter circuit consisting of a first load element connected between a first output node and a second power supply; its gate is a second input node; its drain is a second output node; is connected to the first power source.
a normally-off MESFET; and a second load element connected between the second output node and the second power source, the first input node and In a memory circuit device having a flip-flop type memory cell to which the second output node, the first output node, and the second input node are respectively connected, the first output node is an anode, and the first output node is an anode; a first Schottky diode having the intermediate node of the first intermediate node as a cathode; a second Schottky diode having the second output node as the anode and the first intermediate node as the cathode; 1. A gallium arsenide semiconductor memory device, comprising: a third load element connected between a first power source and a third load element.