JPH03225839A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To enable increase in a source resistance and deterioration of high-frequency characteristic to be suppressed by forming a resist at a gate opening in an overhang shape and by forming a recess formation by a combination of dry etching and wet etching. CONSTITUTION:Recesses 9 and 10 and a gate electrode 11 are formed by forming a resist patterning for forming the gate electrode 11 by using two-layer resists 7 and 8 so that an overhand shape is formed, by forming the first recess 9 by dry etching, by forming a second recess 10 by wet etching, and then by forming the gate electrode 11 by using a resist. Thus, a gate length is determined by opening dimensions of the upper-layer resist 8 and an N<+>-GaAs layer 5 and a gate electrode 11 which mainly affect a gate leak current and a capacity Cgd between the gate and drain can be separated so that a source resistance Rs is not increased, thus enabling high-frequency characteristics to be improved due to reduction in a source resistance Rs and that in a gate leak current and a capacity Cgd between the gate and the drain.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method for manufacturing a field effect transistor, and in particular, to a method for manufacturing a field effect transistor.
The present invention relates to a recess and gate formation process for a field effect transistor having an As-based heterojunction.

[Conventional technology]

A field effect transistor (hereinafter referred to as HJ-FET) having a heterojunction of A1GaAs and GaAs is a conventional G
Compared to aAs FETs, it is rapidly being put into practical use due to its low noise characteristics. In order to improve noise characteristics, this HJ-FET usually has a recessed structure and a source resistance (
We are trying to reduce the cost of Rs.

As shown in FIGS. 3(a) and 3(b), the conventional HJ-FET has a GaAs buffer layer 2 containing no impurities on a semi-insulating GaAs substrate 1, and an N''AI !
By forming the GaAs layer 4, a two-dimensional electron gas layer 3 is formed thereunder. This N”-AI
The IGaAs layer 4 has a recess at the gate electrode ll, and this recess structure reduces the source resistance Rs.However, in the HJ-FET, the top layer has a 1 to 3X layer called a cap layer. 10”am’N”-GaAs
This N''-GaAs layer 5 has an ohmic electrode 6 as a source/drain electrode, and has disadvantages of deterioration of high frequency characteristics due to an increase in gate leakage current and an increase in gate-drain capacitance Cgd. There is also.Figure 3 (a)
This method is usually used for boat fishing, in which a recess is formed by wet etching using a resist layer as a mask, a gate metal is then deposited, and a gate electrode 11 is formed over the entire recessed portion by a lift-off method. There is.

In FIG. 3(b), the gate electrode 11 is formed on the source electrode side of the recessed portion using, for example, an oblique evaporation method so as to have an offset structure within the recess.

[Problem to be solved by the invention]

This conventional method has the following problems.

In FIG. 3(a), the recess width is suppressed and the source resistance R
Although it is most advantageous for reducing s and improving gm, since the gate electrode 11 and the n''-GaAs layer (cap layer) 5 are very close to or in contact with each other, gate leakage current increases and gate-drain capacitance Cgd increases. Due to decrease in gain, etc.
The high frequency performance is not necessarily improved to the extent that could be expected depending on the values of the source resistances Rs and gm. In addition, in terms of performance, by creating an offset structure inside the recess as shown in FIG. 3(b), very good characteristics can be expected as the source resistance Rs is reduced, gm is improved, and Cgd is reduced. For HJ-FETs, forming the gate electrode 11 by alignment using lithography within a lyse requires accuracy of ±0.1 μm or less, which is difficult in terms of manufacturing yield. Further, stable formation using the above-mentioned oblique vapor deposition method is also difficult.

[Means to solve the problem]

According to the method for manufacturing a field effect transistor according to the present invention, the recess formation and the gate electrode formation are performed by forming the gate [resist patterning for electrode formation using a two-layer resist so as to have an overhang shape, and then After a first recess is formed by dry etching and a second recess is formed by wet etching, a gate electrode is formed by a lift-off method using the resist.

〔Example〕

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a process sectional view for explaining one embodiment of the present invention. Figure 1 shows the semi-insulating GaAs obtained by MBE method.
A buffer layer 2 of GaAs on the base 1 and a N"-AfflGa
A 12 Ga for HJ-FET with As layer 4 grown
This is an As/GaAs type heterojunction crystal in which active regions are separated and source/drain ohmic electrodes 6 are formed. FIG. 1(b) shows the patterning of the resist 7.8 for forming the gate electrode. In this step, the register 8 is P
Using two MMA-based resists with different sensitivities and electron beam direct writing (EB direct writing), an opening in the shape of an opaque ring is formed as shown in FIG. 3(b). The formation of this resist shape depends on the exposure dose, development, resist sensitivity,
Although it is controlled by the optimum conditions of the resist film thickness, it is not so difficult with EB direct writing. Next, the first recess portion 9 is formed by dry etching using a CCl22-based gas. In this case, the n''-GaAs layer 5 of the cap layer and the n''-GaAs layer 5 of the cap layer
"A!! It is possible to give selectivity to the GaAs layer 4 so that the etching ends when the surface of the n"-AilGaAs layer 4 is exposed (the first
Figure (C)). Next, the second recess portion 10 is formed by wet etching using, for example, a sulfuric acid-based or phosphoric acid-based etchant. Then the gate metal (e.g. T
i-Al! .

(N1-An, etc.), and using resist layers 7 and 8,
A gate electrode 11 is formed by a lift-off method (FIG. 3(e)).

According to the method described above, the gate length is 8
Cap, which is determined by the opening size of the
The N''-GaAs layer 5 and the gate electrode 11 can be separated to such an extent that the source resistance Rs does not increase.
If X 10 "cm-3500 people, N"-GaAs layer 5 is 2
It is possible to control at 5 μm. Furthermore, performing the second recess etching by wet etching also serves to remove damage, contamination, etc. during the first recess etching, and the influence of dry etching on electrical characteristics can be ignored.

FIG. 2 is a process sectional view showing another embodiment of the present invention. FIG. 2(a) differs from the embodiment shown in FIG. 1 in that an insulating film 12 is provided between the source and drain. FIG. 2(b) is the same as the embodiment in FIG. 1, after forming an overhang resist shape by EB direct drawing,
2 has been removed. In this case, the insulating film 12 and 5
It is removed by wet etching using in2. All post-processes are the same as the embodiment shown in Fig. 1, and the effects are also the same.Using the insulating film 12 in the embodiment shown in Fig. 2 effectively reduces the thickness of the resist between ohmics. The feature is that it can be made thinner, and that control of the resist shape during direct EB writing is easier than in the embodiment shown in FIG.

〔Effect of the invention〕

As explained above, according to the method of manufacturing a field effect transistor according to the present invention, the resist shape of the gate opening can be
B Use direct drawing to form an overhang shape, and
By forming the recess by a combination of dry etching and wet etching, the controllability of the recess width is improved, the increase in source resistance Rs is suppressed, and the high frequency characteristics are improved by increasing the gate leakage current and the gate-drain capacitance Cgd. It is possible to provide a heterojunction field effect transistor that can suppress deterioration of

[Brief explanation of drawings]

FIGS. 1(a) to (e) are cross-sectional views showing one embodiment of the present invention in the order of steps, and FIGS. 2(a) and (b) show main steps of another embodiment of the present invention. Cross-sectional view, Figure 3(a),
(b) is a sectional view of each conventional HJ-FET. l...GaAs substrate, 2...buffer layer, 3...two-dimensional electron gas layer, 4...
n”-Aj?GaAs layer, 5...n”-GaA
S layer, 6... Ohmic electrode, 7, 8...
...Resist, 9...First recess area, 10
. . . second recess region, 11 . . . gate electrode, 12 . . . insulating film.

Claims (1)

[Claims] In a method of manufacturing a field effect transistor having an AlGaAs/GaAs heterojunction, a step of using a two-layer resist and providing an opening region of a gate portion having an overhang shape in the two-layer resist by direct writing with an electron beam; A step of selectively forming a first recess region by dry etching using the overhang-shaped resist layer as a mask, a step of forming a second recess region by wet etching, and then a step of forming the two-layer resist layer. 1. A method for manufacturing a field-effect transistor, comprising the step of forming a gate electrode using a lift-off method.