JPH03225696A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To more accelerate the read/write of data by three-dimensionally laminating plural plane-shaped memory arrays arranging plural memory cells, forming a memory part and parallelly inputting/outputting the data from the respective arrays. CONSTITUTION:Memory arrays 241-24n are formed by respectively arranging the plural memory cells in the shape of a matrix on on the plane-shaped surfaces. The plural memory arrays are multi layer laminated so as to form a memory part 24. Paired bit lines 22a and 22b are commonly provided to all the memory arrays and commonly connected to the memory cells at the prescribed positions of the respective memory arrays. All the paired bit lines are parallelly connected to a data output part 26. This semiconductor memory device can parallelly drive the plural memory arrays through the operations of another control part 29, signal amplifier part 21, word line decode part 28 and sense amplifier part 25, etc., and the data can be inputted/outputted at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device having a plurality of memory cells.

[Prior Art] In semiconductor memory devices, higher integration and higher speed have been achieved in the past. However, in recent years, there has been a demand for higher integration and higher speed due to the increase in the processing speed of CPUs (central processing units) and the application of storage devices to image processing.

In order to meet such demands, for example, in a DRAM (dynamic random access memory), a specific row is selected by inputting a row address, all memory cells in that row are connected to a bit line group, and then consecutive bit lines are connected to the bit line group. Various operating modes have been developed in which memory cells in the same row are accessed continuously and at high speed by accessing them. For example, fast page mode, static column mode, extended nibble mode, etc.

[Problems to be Solved by the Invention] However, all conventional semiconductor memory devices are configured so that each memory cell is serially accessed.
Even if the above-mentioned operation mode is adopted, there is a limit to speeding up the access operation.

Therefore, an object of the present invention is to provide a semiconductor memory device that can read and write data at higher speeds.

[Means for Solving the Problems] A feature of the present invention that achieves the above-mentioned object is that a storage unit configured by three-dimensionally stacking a plurality of planar memory arrays in which a plurality of memory cells are arranged; A plurality of word lines provided corresponding to each memory array and each commonly connected to a memory cell in the same memory array, and a plurality of word lines provided in common to a plurality of memory arrays and common to a predetermined memory cell of each memory array. The present invention is characterized in that it includes a plurality of bit line pairs connected to each other, and an input/output section that allows data to be input/output in parallel with respect to the plurality of bit line pairs.

[Action] When a word line is selected by the input decode signal, all memory cells of the memory array corresponding to the word line are connected to a plurality of bit line pairs, respectively. Since these plurality of bit line pairs are respectively connected to a plurality of data lines, parallel data input/output is performed.

[Example code] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a perspective view showing a schematic configuration of an embodiment of the semiconductor memory device of the present invention.

In the figure, reference numeral 10 denotes a storage section composed of a three-dimensional array in which a plurality of memory arrays are stacked as described later, and this storage section 10 has data input/output that can be accessed in parallel via a data amplification section 11. section 12 is connected. The storage unit 10 is further connected to a decoding unit 13 that selects word lines and a control unit 14. The control unit 14
storage section 10, data amplification section 11, data input/output section 12,
and controls the operation of the decoding section 13.

The data applied from the outside is passed through the data input/output section 12 and the data amplification section 11 to the decoding section 13 of the storage section 10.
is written in parallel to multiple memory cells of the memory array selected in .

Reading from the storage unit 10 is performed as follows.

The data stored in the plurality of memory cells of the memory array selected by the decoding section 13 is read out in parallel and amplified by the data amplifying section 11, and then sent to the data input/output section 12.
are output in parallel to the outside via.

FIG. 1 is a circuit diagram showing a part of the configuration of another embodiment of the semiconductor memory device of the present invention.

As shown in the figure, this embodiment receives optical image information and
It is configured to be stored directly in RAM.

In the figure, reference numeral 20 denotes an optical sensor array section formed by arranging a plurality of photodiodes that receive optical image information and perform photoelectric conversion, and 21 denotes a signal amplification section having an input connected to each photodiode of the optical sensor array section 20. It is. Although the optical sensor array section 20 is shown as being composed of two photodiodes in FIG. 1, in reality, a large number of photodiodes are arranged in a line or matrix. The signal amplification section 21 also has a large number of input and amplification circuits.

The bit line pair 2 is connected to the output of each amplifier circuit of the signal amplifying section 21.
2a and 22b, 23s and 23b are connected, respectively. Actually, as many bit line pairs as there are photodiodes are provided, but in the following explanation, only the above-mentioned two bit line pairs will be described.

The storage unit 24 includes a plurality of planar memory arrays 241.2.
It is composed of a three-dimensional array in which 4□, 243 to 241+ (n is an arbitrary integer) are piled up. Each memory array 24
1.24□, 24. ~24. ．． A plurality of dynamic memory cells are arranged in a matrix on the same plane.

Bit line pairs 22a and 22b, 23a and 23b are connected to all memory arrays 241.24□, 243-24.
, and each memory array 24
1.24□, 243-24. are commonly connected to memory cells at predetermined locations. Bit line pair 22a and 22b
, 232 and 23b are further connected to the sense amplifier section 25. The sense amplifier section 25 is connected to the bit line pair 2.
It has sense amplifiers 25a and 25b corresponding to sense amplifiers 2a and 22b, and 23a and 23b, respectively. Actually, the number of sense amplifiers is equal to the number of bit line pairs, and hence the number of photodiodes.

All bit line pairs 22a and 22b, 23a and 2
3b is further connected in parallel to the data output section 26.

Each memory array 24+, 24□, 243-24. , word lines are provided for each. That is, a word line 271 is provided for the memory array 24,
Word line 27. for memory array 24n. is provided. Each word line is connected to each memory array 24 . ．． 24□, 243-24. , are commonly connected to all memory cells of . For example, the word line 271 is
It is commonly connected to all memory cells of memory array 241. All word lines are processed by word line decoder 28
and is selected according to the decoded signal.

The control section 29 includes a signal amplification section 21 and a word line decoding section 2.
8, are connected to the sense amplifier section 25 and the data output section 26 by lines 30, 31, 32, and 33, respectively, and write control signals, decode signals, A sense amplifier control signal and an output section control signal are respectively sent.

Next, the operation of this embodiment will be explained.

Light incident on the optical sensor array section 2o in accordance with the original image is converted into an electrical signal by each photodiode and sent to each amplification circuit of the signal amplification section 21, respectively.

During writing, a write control signal is applied from the control section 29 to the signal amplification section 21, so the signals inputted by each amplification circuit of the signal amplification section 21 are amplified and output to the bit line pairs 22a and 22b, 23a and 23h. be done. On the other hand, at the time of writing, a decode signal is applied from the control section 29 to the word line decoding section 28, and the word line designated by this decode signal rises.

As a result, input data is written in parallel to all memory cells in the - plane of the memory array related to the word line that has risen, for example, the memory array 241 when the word line 271 has risen.

At the time of reading, the data stored in all the memory cells on one plane of the memory array related to the word line selected by the word line decoding section 28 is read out in parallel, and after being amplified by the sense amplifier section 25, Data output section 26
are output in parallel via .

As described above, according to this embodiment, data for a maximum of two planes can be input/output in parallel with respect to the storage unit 24 configured in a three-dimensional array. Alternatively, it can be used in a storage unit of a three-dimensional data analysis device, etc. to achieve higher speed.

[Effects of the Invention] As described in detail above, according to the present invention, there is provided a storage section configured by three-dimensionally stacking a plurality of planar memory arrays in which a plurality of memory cells are arranged, and each memory array. A plurality of word lines are provided correspondingly and each is commonly connected to a memory cell in the same memory array, and a plurality of word lines are provided in common to the plurality of memory arrays and are commonly connected to a predetermined memory cell of each memory array. Since the device includes a plurality of bit line pairs and an input/output section that enables data to be input and output in parallel with respect to the plurality of bit line pairs, reading and writing of data can be made faster. Furthermore, since the storage section is configured by three-dimensionally stacking a plurality of memory arrays, the storage capacity can be easily increased.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a part of the structure of one embodiment of the semiconductor memory device of the present invention, and FIG. 2 is a perspective view showing the schematic structure of another embodiment of the semiconductor memory device of the present invention. 10.24...Storage unit, 11...Data amplification unit, 12...Data input/output unit, 13...
...Decoding section, 14.29...Control section,
20... Optical sensor array section, 21...
・Signal amplification section, 22a, 22b, 23g,
23b--Bit line pair, 24. ．． 24□, 24
3.24n...Memory array, 25...
・Sense amplifier section, 25a125b...Sense amplifier, 26...Data output section, 271.27
fi...Word line, 28...Word line decoding section.

Claims (1)

[Claims] A flat memory array with multiple memory cells arranged in three
a memory section configured by stacking a plurality of them dimensionally; a plurality of word lines provided corresponding to each of the memory arrays and each commonly connected to a memory cell in the same memory array; a plurality of bit line pairs provided in common to the memory array and commonly connected to predetermined memory cells of each of the memory arrays; and an input/output section that enables data input/output in parallel with respect to the plurality of bit line pairs. A semiconductor memory device comprising: