JPH03225303A - Production of optical waveguide of semiconductor - Google Patents

Production of optical waveguide of semiconductor

Info

Publication number
JPH03225303A
JPH03225303A JP2078090A JP2078090A JPH03225303A JP H03225303 A JPH03225303 A JP H03225303A JP 2078090 A JP2078090 A JP 2078090A JP 2078090 A JP2078090 A JP 2078090A JP H03225303 A JPH03225303 A JP H03225303A
Authority
JP
Japan
Prior art keywords
etching
semiconductor
gas
flow rate
optical waveguide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2078090A
Other languages
Japanese (ja)
Other versions
JP2932441B2 (en
Inventor
Kiichi Hamamoto
貴一 濱本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2078090A priority Critical patent/JP2932441B2/en
Publication of JPH03225303A publication Critical patent/JPH03225303A/en
Application granted granted Critical
Publication of JP2932441B2 publication Critical patent/JP2932441B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To improve the controllability of etching depth by continuously carrying out etching at an increased exhaust speed and an increased flow rate of a gas and etching at a reduced exhaust speed and a reduced flow rate of the gas in an etching stage at the time of forming a rib part. CONSTITUTION:A first clad layer of Al0.5Ga0.5As, a waveguide layer of GaAs and a second clad layer of Al0.5Ga0.5As are successively grown on a GaAs substrate. A photoresist mask 11 having the shape of a waveguide to be formed is then formed on the resulting GaAs/AlGaAs wafer 10. First dry etching in a relatively high physical sputtering state attained by increasing exhaust speed and the flow rate of a gas and second dry etching in a relatively high reactive state attained by reducing exhaust speed and the flow rate of the gas are continuously carried out with the same gas. The controllability of etching depth can be improved independently of the surface state of the wafer.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体光導波路の製造方法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method for manufacturing a semiconductor optical waveguide.

(従来の技術) 光エレクトロニクスの進歩とともに、半導体光デバイス
の集積化の研究開発が近年盛んに進められている。特に
半導体光導波路は、半導体電子デバイスで培われた微細
加工技術を応用することによって半導体基板上に実現で
き、半導体光マトリクススイッチの各スイッチ間の接続
や、同一基板内での半導体光機能素子間の接続(例えば
、光源とスイ4ツチやアンプなどとの接続)に用いられ
、半導体光集積回路の重要なコンポーネントの一つと考
えられる。このような半導体光導波路の形成方法として
は、通常のフォトリソグラフィ法によって半導体基板上
に導波路形状のマスクを形成した後に、BCff3ガス
による反応性イオンビームエツチング法(RIBE法)
によってリブ型の光導波路を形成できることが性向らに
よってエレクトロニクス・レターズ第22巻1243頁
(ELCTRONIC8LETTER8Vol、22 
p、1243)に報告されている。
(Prior Art) Along with advances in optoelectronics, research and development into the integration of semiconductor optical devices has been actively progressing in recent years. In particular, semiconductor optical waveguides can be realized on semiconductor substrates by applying microfabrication technology cultivated in semiconductor electronic devices, and can be used for connections between each switch of a semiconductor optical matrix switch, and between semiconductor optical functional elements on the same substrate. It is used for connections between light sources and switches, amplifiers, etc., and is considered to be one of the important components of semiconductor optical integrated circuits. As a method for forming such a semiconductor optical waveguide, after forming a waveguide-shaped mask on a semiconductor substrate by a normal photolithography method, a reactive ion beam etching method (RIBE method) using BCff3 gas is used.
It has been found that a rib-type optical waveguide can be formed by using the following method.Electronics Letters Vol. 22, p. 1243
p, 1243).

(発明か解決しようとする課題) ところで、半導体光導波路を形成する際には、リブ部の
高さ、すなわちエツチング深さの制御性が重要である。
(Problem to be Solved by the Invention) Incidentally, when forming a semiconductor optical waveguide, controllability of the height of the rib portion, that is, the etching depth is important.

これは、エツチングの深さがそのまま半導体光導波路の
光の閉じ込めの強さを左右するからであり、例えば、方
向性結合器型半導体光スィッチを作製するときは、リブ
部形成時のエツチング深さをある程度精密に制御しなけ
れば、設計通りの動作は得られない。ところが、従来の
RIBE法によるドライエツチングでは、ウェハの表面
状態にエツチング深さの制御性が左右されてしまい、エ
ツチング深さの制御性が高々±5%程度である。このよ
うに、従来の半導体導波路の製造方法にはリブ型導波路
の深さの制御性に関し解決すべき課題があった。
This is because the depth of etching directly affects the strength of light confinement in the semiconductor optical waveguide. For example, when manufacturing a directional coupler type semiconductor optical switch, the etching depth when forming the rib portion is Unless it is controlled with some degree of precision, the designed operation cannot be obtained. However, in dry etching using the conventional RIBE method, the controllability of the etching depth is affected by the surface condition of the wafer, and the controllability of the etching depth is about ±5% at most. As described above, the conventional semiconductor waveguide manufacturing method has a problem to be solved regarding the controllability of the depth of the rib-type waveguide.

(課題を解決するための手段) 上述の課題を解決するために、本発明による半導体光導
波路の製造方法は、半導体基板上に少なくとも半導体第
1クラッド層、半導体導波層および半導体第2クラッド
層を積層して積層構造半導体ウェハを形成する工程と、
形成しようとする光導波路の形のエツチング用マスクを
前記積層構造半導体ウェハ上に設ける工程と、前記マス
クで覆われた部分以外の半導体第2クラッド層をエツチ
ングにより除去してリブ型光導波路を形成する工程とを
含み、前記マスクで覆われた部分以外の半導体第2クラ
ッド層をエツチングにより除去してリブ型光導波路を形
成する工程が、排気速度を速(しかつガス流量を増加さ
せることによって実現される比較的物理スパッタ性の強
い状態で行なう第1のエツチング工程と、排気速度を遅
くしかつガス流量を減少させることによって実現される
比較的反応性の高い状態で行なう第2のエツチング工程
とが、同一のガスを用いて連続して行なわれるドライエ
ツチグ工程であることを特徴とする。
(Means for Solving the Problems) In order to solve the above-mentioned problems, a method for manufacturing a semiconductor optical waveguide according to the present invention includes at least a semiconductor first cladding layer, a semiconductor waveguide layer, and a semiconductor second cladding layer on a semiconductor substrate. a step of stacking to form a stacked structure semiconductor wafer;
A step of providing an etching mask in the shape of an optical waveguide to be formed on the laminated structure semiconductor wafer, and removing the second semiconductor cladding layer other than the portion covered by the mask by etching to form a rib-type optical waveguide. The step of removing the semiconductor second cladding layer other than the portion covered by the mask by etching to form a rib-type optical waveguide is performed by increasing the pumping speed (and increasing the gas flow rate). The first etching step is carried out in a state with relatively strong physical sputtering properties, and the second etching step is carried out in a relatively highly reactive state, which is achieved by slowing down the pumping speed and reducing the gas flow rate. The dry etching process is characterized in that the steps are dry etching steps that are performed consecutively using the same gas.

(作用) 一般に、半導体光導波路のリブ部を形成する場合、エツ
チング深さの制御性は重要である。これは、エツチング
の深さがそのまま半導体光導波路の光の閉じ込めの強さ
を左右するからであり、例えば、方向性結合器型半導体
光スィッチを作製するときは、リブ部形成時のエツチン
グの深さをある程度精密に制御しなければ、設計通りの
動作は得られない。ところが、従来のRIBE法による
ドライエツチングでは、ウェハの表面状態にエツチング
深さの制御性が左右されてしまい、制御性のよいエツチ
ング深さが得られない。
(Function) Generally, when forming a rib portion of a semiconductor optical waveguide, controllability of etching depth is important. This is because the depth of etching directly affects the strength of light confinement in the semiconductor optical waveguide. For example, when manufacturing a directional coupler type semiconductor optical switch, the depth of etching when forming the rib portion is Unless the temperature is controlled with some degree of precision, the designed operation cannot be achieved. However, in dry etching using the conventional RIBE method, the controllability of the etching depth depends on the surface condition of the wafer, making it impossible to obtain an etching depth with good controllability.

これに対して、本発明においては、リブ部形成時のドラ
イエツチング工程において、排気速度を速くしかつガス
流量を増加させることによって実現される比較的物理ス
パッタ性の強い状態による第1のエツチング工程をまず
行うから、ウェハの表面状態によらず、エツチング深さ
の制御性が改善される。また、第1のエツチング工程の
直後に排気速度を遅くしかつガス流量を減少させること
によって実現される比較的反応性の高い状態による第2
のエツチング工程を行なうから、マスクとの選択比が確
保され、マスクの後退による垂直性の低下の心配が無い
うえに、エツチング面のダメージが少ない。このため、
終始反応性の強い状態で行なうエツチングに比べてエツ
チング深さの制御性がよく、かつ、垂直性は確保されエ
ツチング面のダメージも少ない。
In contrast, in the present invention, in the dry etching process when forming the rib portion, the first etching process is performed in a state with relatively strong physical sputtering properties, which is achieved by increasing the exhaust speed and increasing the gas flow rate. Since this is performed first, the controllability of the etching depth is improved regardless of the surface condition of the wafer. Also, a second etching step due to a relatively more reactive state achieved by slowing the pumping speed and reducing the gas flow rate immediately after the first etching step is also possible.
Since the etching process is performed, a selectivity with respect to the mask is ensured, there is no concern that the perpendicularity will deteriorate due to mask recession, and there is little damage to the etched surface. For this reason,
Compared to etching performed in a highly reactive state from beginning to end, the etching depth can be controlled better, verticality is ensured, and damage to the etched surface is less.

(実施例) 以下図面を参照して本発明をさらに詳しく説明する。(Example) The present invention will be explained in more detail below with reference to the drawings.

第1図は本発明の方法の一実施例により製造されたGa
As/A、1)GaAs半導体光導波路の構造を示す断
面図である。GaAs基板1上に、An)0.5 Ga
o、、As第1クラッド層2が成長され、Aff O,
5G a O,5A s第1クラッド層2のうえにGa
As導波層3が形成されている。前記GaAs導波層3
の上には、リブ部を有するAll O,5G a o5
A S第2クラッド層4が形成されている。
FIG. 1 shows Ga produced by an embodiment of the method of the present invention.
As/A, 1) is a cross-sectional view showing the structure of a GaAs semiconductor optical waveguide. An) 0.5 Ga on the GaAs substrate 1
o,, As first cladding layer 2 is grown, Aff O,
5G a O, 5A s Ga on the first cladding layer 2
An As waveguide layer 3 is formed. The GaAs waveguide layer 3
All O,5G ao5 with a rib part on top
A second cladding layer 4 is formed.

第1図に示した半導体光導波路の製造方法について以下
に述べる。GaAs基板1上に、分子線エピタキシャル
成長法(MBE法)もしくは有機金属気相成長法(MO
−CVD法)を用いて、Ag3.5 G a o、5 
A S第1クラッド層2、GaAs導波層3、A、C)
 o、s G a o、5A s第2クラッド層4を順
次に成長する。各層の厚さは、AN o、s G a 
o5A s第1クラッド層2が1〜2μ…程度、GaA
s導波層3が0.2μl程度、Ag3.5 G a o
、5 A s第2クラッド層4が1.2μm程度である
A method for manufacturing the semiconductor optical waveguide shown in FIG. 1 will be described below. On the GaAs substrate 1, a molecular beam epitaxial growth method (MBE method) or a metal organic chemical vapor phase epitaxy method (MO
-CVD method), Ag3.5 Ga o, 5
A S first cladding layer 2, GaAs waveguide layer 3, A, C)
The second cladding layer 4 is sequentially grown. The thickness of each layer is AN o, s Ga
o5A s The first cladding layer 2 is about 1 to 2 μ..., GaA
s waveguide layer 3 is about 0.2 μl, Ag3.5 Ga o
, 5 As, the second cladding layer 4 has a thickness of about 1.2 μm.

以上のように結晶を成長させた後、導波路リブ部をCΩ
2ガスを用いたR I B E (Reactive 
IonBeam Etching)法によって形成する
。この工程の概要を第2図に示す。まず第2図(a)の
ように、通常のフォトリソグラフィ法を用いて、GaA
s/AΩGaAsウェハ10上に形成すべき導波路形状
のフォトレジストマスク11を形成する。次に、第2図
(b)のように物理スパッタ性の強い状態の第1のエツ
チング工程によって前記フォトレジスト11で覆われて
いない部分を0.1μm程度エツチングする。ここでは
、物理スパッタ性の高い状態にするために、エツチング
・チャンバーの排気側のバルブの開度を60%程度、C
112ガスの流量を20secIm程度、エツチングチ
ャンバー内の圧力を1mTorr程度に設定する。この
とき、フォトレジストマスク11は高々Q、1μm程度
エツチングされる程度である。この直後に、今度は反応
性の高い状態の第2のエツチング工程によって前記フォ
トレジスト11に覆われていない部分をさらに0.9μ
■程度エツチングする。ここでは、反応性の高い状態に
するために、排気側のバルブの開度を30%程度、Cj
?2ガスの流量を5 secm程度、エツチングチャン
バー内の圧力を1mTorr程度に設定し、前述の第1
のエツチング工程に比べてCD2ガスの流量を少なくし
かつチャンバーの排気速度を遅くしている。この後、前
記フォトレジスト11を有機溶剤等で除去すると、第2
図(C)のような半導体光導波路が得られる。
After growing the crystal as described above, the waveguide rib part was
R I B E (Reactive
It is formed by the ion beam etching method. An outline of this process is shown in Figure 2. First, as shown in Figure 2(a), GaA
A photoresist mask 11 in the shape of a waveguide to be formed is formed on the s/AΩGaAs wafer 10. Next, as shown in FIG. 2(b), the portions not covered with the photoresist 11 are etched by about 0.1 μm by a first etching process with strong physical sputtering properties. Here, in order to achieve a state with high physical sputtering properties, the opening degree of the valve on the exhaust side of the etching chamber was set to about 60%, and C
The flow rate of the 112 gas is set to about 20 secIm, and the pressure inside the etching chamber is set to about 1 mTorr. At this time, the photoresist mask 11 is etched by at most Q, about 1 μm. Immediately after this, a second etching step, this time in a highly reactive state, etches the portion not covered by the photoresist 11 by an additional 0.9 μm.
■Approximately etching. Here, in order to achieve a highly reactive state, the opening degree of the exhaust side valve is set to about 30%, and Cj
? The flow rate of the two gases was set to about 5 sec, the pressure inside the etching chamber was set to about 1 mTorr, and the
Compared to the etching process described above, the flow rate of CD2 gas is lowered and the exhaust speed of the chamber is lowered. After that, when the photoresist 11 is removed using an organic solvent or the like, the second photoresist 11 is removed.
A semiconductor optical waveguide as shown in Figure (C) is obtained.

以上が本発明による半導体光導波路の製造方法の実施例
であり、上述の製造方法によるとエツチング深さの制御
性が改善される原理を以下に説明する。
The above is an embodiment of the method for manufacturing a semiconductor optical waveguide according to the present invention, and the principle by which the controllability of the etching depth is improved by the above-mentioned manufacturing method will be explained below.

従来、ドライエツチングによるエツチング深さの制御性
は、エツチングされるウェハの表面状態に依存しており
、はじめから反応性の高い状態でドライエツチングを行
なうとウェハの表面状態によってエツチング深さがバラ
ついてしまっていた。
Conventionally, the controllability of the etching depth by dry etching has depended on the surface condition of the wafer being etched, and if dry etching is performed in a highly reactive state from the beginning, the etching depth will vary depending on the surface condition of the wafer. It was put away.

これに対して本実施例は、はじめに物理スパッタ性の高
い状態の第1のエツチング工程によって0.1μI程度
ウェハ表面をエツチングしているので、エツチング深さ
はウェハの表面状態には依存せず、また、新たに真空中
に於て清浄なエツチング面を出すことができる。このた
め、第1のエツチング工程終了後は常に同一状態の清浄
なエツチング面が同一のエツチング工程 なる。この、物理スパッタ性の高い状態は、排気速度を
上昇すること、及び単位時間内に導入されるガス分子の
速度を上昇させることによって実現している。すなわち
、一般にガスの排気速度はガスの分子量の平方根に逆比
例するので、排気側のバルブ開度を大きくして排気速度
を上昇させるとCNラジカルよるもCD2ラジカルがチ
ャンバー内に於てより支配的になる。かつ、単位時間当
りに導入されるガス分子の量を上昇させると、CΩ2ガ
ス1分子当りに与えられる単位時間当りのエネルギーが
減少し、C,Q2からC,I7に解離するために必要な
エネルギーが減少するから、さらにCΩ2ラジカルが支
配的になる。従って、チャンバー内にはCΩラジカルよ
りも質量が大きく比較的反応性が低いCl72ラジカル
が支配的になるから物理バッタ性の高い状態が得られる
。そして、第1のエツチング工程の直後に、はじめて反
応性の高い状態による第2エツチング工程を行なってい
るので、エツチング深さの制御性が、はじめから反応性
の高い状態によるエツチングに比べて改善される。この
反応性の高い状態は、排気速度を減少させ、かつ、単位
時間当りに導入されるガス分子量を減少させることによ
って実現している。
On the other hand, in this example, the wafer surface is first etched by about 0.1 μI in the first etching step with high physical sputtering properties, so the etching depth does not depend on the wafer surface condition. In addition, a clean etched surface can be newly exposed in a vacuum. Therefore, after the first etching process is completed, a clean etching surface that is in the same state is always subjected to the same etching process. This state of high physical sputtering properties is achieved by increasing the pumping speed and increasing the speed of gas molecules introduced within a unit time. In other words, the gas exhaust speed is generally inversely proportional to the square root of the molecular weight of the gas, so if the exhaust speed is increased by increasing the valve opening on the exhaust side, CD2 radicals become more dominant in the chamber than CN radicals. become. Moreover, when the amount of gas molecules introduced per unit time is increased, the energy given per unit time per molecule of CΩ2 gas decreases, and the energy required to dissociate from C, Q2 to C, I7 decreases. decreases, so CΩ2 radicals become even more dominant. Therefore, in the chamber, Cl72 radicals, which have a larger mass than CΩ radicals and have relatively low reactivity, become dominant, so that a state of high physical battering property is obtained. Since the second etching step is performed in a highly reactive state immediately after the first etching step, the controllability of the etching depth is improved compared to etching in a highly reactive state from the beginning. Ru. This state of high reactivity is achieved by reducing the pumping speed and reducing the amount of gas molecules introduced per unit time.

また、第1のエツチング工程の直後に反応性の高い状態
による第2のエツチング工程を行なっているので、マス
クとの選択比は確保され、マスクの後退による垂直性の
低下の心配が無い上に、エツチング面のダメージが少な
い。さらに、Ar等の物理スパッタ性の高いガスを用い
た第1のエツチング工程を行なった後にCI?2等の反
応性の高いガスを用いた第2エツチング工程を行なうド
ライエツチング工程に比べ、ガスを切り替える工程が省
け、かつ、第1のエツチング工程と第2のエツチング工
程との間に於て真空排気をする必要が無い。
In addition, since the second etching process in a highly reactive state is performed immediately after the first etching process, the selectivity with the mask is ensured, and there is no worry of verticality deterioration due to mask regression. , less damage to the etched surface. Furthermore, after performing a first etching process using a gas with high physical sputtering properties such as Ar, CI? Compared to a dry etching process in which a second etching process is performed using a highly reactive gas such as No. No need to exhaust.

なお、本実施例においては、RIBE法を用いたが、こ
れに限るものではなく、例えば他のドライエツチング法
として反応性イオンエツチング(RI E)法であって
も本発明は適用できる。
Although the RIBE method was used in this embodiment, the present invention is not limited to this, and the present invention is also applicable to other dry etching methods such as reactive ion etching (RIE).

(発明の効果) 以上に述べたように、本発明によれば、リブ部形成時の
ドライエツチング工程において、ウェハの表面状態によ
らず、エツチング深さの制御性か改善される。さらに、
マスクとの選択比も確保され、マスクの後退による垂直
性の低下の心配が無いうえに、エツチング面のダメージ
が少ない。また、同一のガスを用いているので、ガス切
り替え工程が省け、ガス切り替えにともなう真空排気も
不要である。
(Effects of the Invention) As described above, according to the present invention, the controllability of the etching depth is improved in the dry etching step when forming the rib portion, regardless of the surface condition of the wafer. moreover,
The selectivity with respect to the mask is also ensured, there is no concern that the perpendicularity will deteriorate due to mask recession, and there is little damage to the etched surface. Furthermore, since the same gas is used, a gas switching process can be omitted, and vacuum evacuation accompanying gas switching is also unnecessary.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の方法で製造したGaAs/
Aj7GaAs半導体光導波路の構造を示す断面図、第
2図はその実施例におけるエツチング工程を示す概念図
である。 1−・−G a A s基板、2 ”” I) o、 
、G a o、 5 A s第1クラッド層、3・・・
GaAs導波路、4− All 0.5 G a o、
s A S第2クラッド層、1O−−0GaAs/A(
l GaAsウェハ、11−・・フォトレジストマスク
FIG. 1 shows GaAs/
FIG. 2 is a cross-sectional view showing the structure of an Aj7GaAs semiconductor optical waveguide, and a conceptual diagram showing the etching process in this embodiment. 1-・-G a As substrate, 2 "" I) o,
, Gao, 5A s first cladding layer, 3...
GaAs waveguide, 4-All 0.5 Gao,
s A S second cladding layer, 1O--0GaAs/A (
l GaAs wafer, 11-...photoresist mask.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に少なくとも半導体第1クラッド層、半導
体導波層および半導体第2クラッド層を積層して積層構
造半導体ウェハを形成する工程と、形成しようとする光
導波路の形のエッチング用マスクを前記積層構造半導体
ウェハ上に設ける工程と、前記マスクで覆われた部分以
外の半導体第2クラッド層をエッチングにより除去して
リブ型光導波路を形成する工程が、排気速度を速くしか
つガス流量を増加させることによって実現される比較的
物理スパッタ性の強い状態で行なう第1のエッチング工
程と、排気速度を遅くしかつガス流量を減少させること
によって実現される比較的反応性の高い状態で行なう第
2のエッチング工程とが、同一のガスを用いて連続して
行なわれるドライエッチング工程であることを特徴とす
る半導体光導波路の製造方法。
a step of laminating at least a first semiconductor cladding layer, a semiconductor waveguide layer, and a second semiconductor cladding layer on a semiconductor substrate to form a laminated semiconductor wafer; and a step of laminating an etching mask in the shape of an optical waveguide to be formed. The step of providing the structure on the semiconductor wafer and the step of removing the semiconductor second cladding layer other than the portion covered by the mask by etching to form the rib-type optical waveguide increase the pumping speed and the gas flow rate. The first etching step is carried out in a state with relatively strong physical sputtering properties, which is achieved by etching, and the second etching step is carried out in a state with relatively high reactivity, which is achieved by slowing the pumping speed and reducing the gas flow rate. 1. A method for manufacturing a semiconductor optical waveguide, characterized in that the etching step is a dry etching step performed successively using the same gas.
JP2078090A 1990-01-31 1990-01-31 Method for manufacturing semiconductor optical waveguide Expired - Fee Related JP2932441B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2078090A JP2932441B2 (en) 1990-01-31 1990-01-31 Method for manufacturing semiconductor optical waveguide

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2078090A JP2932441B2 (en) 1990-01-31 1990-01-31 Method for manufacturing semiconductor optical waveguide

Publications (2)

Publication Number Publication Date
JPH03225303A true JPH03225303A (en) 1991-10-04
JP2932441B2 JP2932441B2 (en) 1999-08-09

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Family Applications (1)

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Country Status (1)

Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5968845A (en) * 1996-02-13 1999-10-19 Matsushita Electric Industrial Co., Ltd. Method for etching a compound semiconductor, a semi-conductor laser device and method for producing the same
US7754999B2 (en) * 2003-05-13 2010-07-13 Hewlett-Packard Development Company, L.P. Laser micromachining and methods of same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5968845A (en) * 1996-02-13 1999-10-19 Matsushita Electric Industrial Co., Ltd. Method for etching a compound semiconductor, a semi-conductor laser device and method for producing the same
US6127201A (en) * 1996-02-13 2000-10-03 Matsushita Electric Industrial Co., Ltd. Method for etching a compound semiconductor, a semiconductor laser device and method for producing the same
US6266354B1 (en) 1996-02-13 2001-07-24 Matsushita Electric Industrial Co., Ltd. Semiconductor laser device with ridge structure
US7754999B2 (en) * 2003-05-13 2010-07-13 Hewlett-Packard Development Company, L.P. Laser micromachining and methods of same

Also Published As

Publication number Publication date
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