JPH03225302A - Production of optical waveguide of semiconductor - Google Patents

Production of optical waveguide of semiconductor

Info

Publication number
JPH03225302A
JPH03225302A JP2077690A JP2077690A JPH03225302A JP H03225302 A JPH03225302 A JP H03225302A JP 2077690 A JP2077690 A JP 2077690A JP 2077690 A JP2077690 A JP 2077690A JP H03225302 A JPH03225302 A JP H03225302A
Authority
JP
Japan
Prior art keywords
etching
semiconductor
layer
gas
optical waveguide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2077690A
Other languages
Japanese (ja)
Inventor
Kiichi Hamamoto
貴一 濱本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2077690A priority Critical patent/JPH03225302A/en
Publication of JPH03225302A publication Critical patent/JPH03225302A/en
Pending legal-status Critical Current

Links

Landscapes

  • Optical Integrated Circuits (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To improve the controllability of etching depth by continuously carrying out etching with a gas having relatively low reactivity and etching with a gas having relatively high reactivity in an etching stage at the time of forming a rib part. CONSTITUTION:First clad layer 2 of Al0.5Ga0.5As is grown on a GaAs substrate 1 and waveguide layer 3 of AlGaAs and a second clad layer 4 of Al0.5Ga0.5As are formed on the layer 2. A photoresist mask having the shape of a waveguide to be formed on the layer 3 is then formed on the layer 4 and the part of the layer 4 not covered with the mask is etched with a gas having low reactivity in a first etching stage. The etched part is further etched with a gas having high reactivity in a second etching stage. Since clean etched surfaces having the same state are always obtd. after the first etching stage and then second etching is carried out, the controllability of etching depth is improved.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体光集積回路等に用いられる半導体導波
路の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor waveguide used in semiconductor optical integrated circuits and the like.

(従来の技術) 光エレクトロニクスの進歩とともに、半導体光デバイス
の集積化の研究開発が近年盛んに進められている。特に
半導体光導波路は、半導体電子デバイスで培われた微細
加工技術を応用することによって半導体基板上に実現で
き、半導体光マトリクススイッチの各スイッチ間の接続
や、同一基板内での半導体光機能素子間の接続(例えば
、光源とスイッチやアンプなどとの接続)に用いられ、
半導体光集積回路の重要なコンポーネントの一つと考え
られる。このような半導体光導波路の形成方法としては
、通常のフォトリソグラフィ法によって半導体基板上に
導波路形状のマスクを形成した後に、BCΩ3ガスによ
る反応性イオンビームエツチング法(RIBE法)によ
ってリブ型の光導波路を形成できることが性向らによっ
てエレクトロニクス・レターズ第22巻1243頁(E
LCTRONIC3LETTER8Vol、22 p、
1243)に報告されている。
(Prior Art) Along with advances in optoelectronics, research and development into the integration of semiconductor optical devices has been actively progressing in recent years. In particular, semiconductor optical waveguides can be realized on semiconductor substrates by applying microfabrication technology cultivated in semiconductor electronic devices, and can be used for connections between each switch of a semiconductor optical matrix switch, and between semiconductor optical functional elements on the same substrate. (for example, connecting a light source to a switch or amplifier, etc.)
It is considered one of the important components of semiconductor optical integrated circuits. As a method for forming such a semiconductor optical waveguide, a waveguide-shaped mask is formed on a semiconductor substrate using a normal photolithography method, and then a rib-shaped optical guide is formed using a reactive ion beam etching method (RIBE method) using BCΩ3 gas. Electronics Letters Vol. 22, p. 1243 (E
LCTRONIC3LETTER8Vol, 22p,
1243).

(発明が解決しようとする課題) ところで、半導体光導波路を形成する際には、リブ部の
高さ、すなわちエツチング深さの制御性が重要である。
(Problems to be Solved by the Invention) Incidentally, when forming a semiconductor optical waveguide, controllability of the height of the rib portion, that is, the etching depth is important.

これは、エツチングの深さがそのまま半導体光導波路の
光の閉じ込めの強さを左右するからであり、例えば、方
向性結合器型半導体光スィッチを作製するときは、リブ
部形成時のエツチング深さをある程度精密に制御しなけ
れば、設計通りの動作は得られない。ところが、従来の
RIBE法によるドライエツチングでは、ウェハの表面
状態にエツチング深さの制御性が左右されてしまい、エ
ツチング深さの制御性が高々±5%程度である。このよ
うに、従来の半導体導波路の製造方法にはリブ型導波路
の深さの制御性に関し解決すべき課題があった。
This is because the depth of etching directly affects the strength of light confinement in the semiconductor optical waveguide. For example, when manufacturing a directional coupler type semiconductor optical switch, the etching depth when forming the rib portion is Unless it is controlled with some degree of precision, the designed operation cannot be obtained. However, in dry etching using the conventional RIBE method, the controllability of the etching depth is affected by the surface condition of the wafer, and the controllability of the etching depth is about ±5% at most. As described above, the conventional semiconductor waveguide manufacturing method has a problem to be solved regarding the controllability of the depth of the rib-type waveguide.

(課題を解決するための手段) 上述の課題を解決するために、本発明による半導体光導
波路の製造方法は、半導体基板上に少なくとも半導体第
1クラッド層、半導体導波層および半導体第2クラッド
層を積層して積層構造半導体ウェハを形成する工程と、
形成しようとする光導波路の形のエツチング用マスクを
前記積層構造半導体ウェハ上に設ける工程と、前記マス
クで覆われた部分以外の半導体第2クラッド層をエツチ
ングにより除去してリブ型光導波路を形成する工程とを
含み、前記マスクで覆われた部分以外の半導体第2クラ
ッド層をエツチングにより除去してリブ型光導波路を形
成する工程が、比較的反応性の低いガスによる第1のエ
ツチング工程と比較的反応性の高いガスによる第2のエ
ツチング工程とが連続して行なわれる工程であることを
特徴とする。
(Means for Solving the Problems) In order to solve the above-mentioned problems, a method for manufacturing a semiconductor optical waveguide according to the present invention includes at least a semiconductor first cladding layer, a semiconductor waveguide layer, and a semiconductor second cladding layer on a semiconductor substrate. a step of stacking to form a stacked structure semiconductor wafer;
A step of providing an etching mask in the shape of an optical waveguide to be formed on the laminated structure semiconductor wafer, and removing the second semiconductor cladding layer other than the portion covered by the mask by etching to form a rib-type optical waveguide. The step of removing the semiconductor second cladding layer other than the portion covered by the mask by etching to form a rib-type optical waveguide is a first etching step using a relatively low-reactivity gas. It is characterized in that the second etching step using a relatively highly reactive gas is performed continuously.

(作用) 一般に、半導体光導波路のリブ部を形成する場合、エツ
チング深さの制御性は重要である。これは、エツチング
の深さがそのまま半導体光導波路の光の閉じ込めの強さ
を左右するからであり、例えば、方向性結合器型半導体
光スィッチを作製するときは、リブ部形成時のエツチン
グ深さをある程度精密に制御しなければ、設計通りの動
作は得られない。ところが、従来のRIBE法によるド
ライエツチングでは、ウェハの表面状態にエツチング深
さの制御性が左右されてしまい、制御性のよいエツチン
グ深さが得られない。
(Function) Generally, when forming a rib portion of a semiconductor optical waveguide, controllability of etching depth is important. This is because the depth of etching directly affects the strength of light confinement in the semiconductor optical waveguide. For example, when manufacturing a directional coupler type semiconductor optical switch, the etching depth when forming the rib portion is Unless it is controlled with some degree of precision, the designed operation cannot be obtained. However, in dry etching using the conventional RIBE method, the controllability of the etching depth depends on the surface condition of the wafer, making it impossible to obtain an etching depth with good controllability.

これに対して、本発明においては、リブ部形成時のドラ
イエツチング工程において、まず比較的反応性の低いガ
スによる第1のエツチング工程をを行うから、ウェハの
表面状態によらず、エツチング深さの制御性が改善され
る。さらに、この後に比較的反応性の高いガスによる第
2のエツチング工程を行うから、マスクとの選択比が確
保され、マスクの後退による垂直性の低下の心配が無い
うえに、エツチング面のダメージが少ない。このため、
終始反応性の高いガスのみで行うエツチングに比べてエ
ツチング深さの制御性がよく、がっ、終始反応性の低い
ガスのみで行なうエツチングに比べて垂直性がよくエツ
チング面のダメージが少ない。
On the other hand, in the present invention, in the dry etching process when forming the rib portion, the first etching process is performed using a gas with relatively low reactivity. controllability is improved. Furthermore, since a second etching process using a relatively highly reactive gas is performed after this, a selectivity with the mask is ensured, and there is no concern that the perpendicularity will decrease due to mask recession, and damage to the etched surface is avoided. few. For this reason,
The etching depth is more controllable than etching using only a highly reactive gas from beginning to end, and the etching surface is more perpendicular and less damaged than etching using only a less reactive gas from beginning to end.

(実施例) 以下図面を参照して本発明をさらに詳しく説明する。(Example) The present invention will be explained in more detail below with reference to the drawings.

第1図は本発明の方法の一実施例により製造されたGa
As/A、l/GaAs半導体光導波路の構造を示す断
面図である。GaAs基板1上に、AΩ。5 G a 
O,5A S第1クラッド層2が成長され、AΩo 5
Gao 、 5 A S第1クラッド層2の上にGaA
s導波層3が成長されている。前記GaAs導波層3の
上には、リブ部を有するAΩo、G a 0.5 A 
S第2クラッド層4が形成されている。
FIG. 1 shows Ga produced by an embodiment of the method of the present invention.
FIG. 2 is a cross-sectional view showing the structure of an As/A, l/GaAs semiconductor optical waveguide. AΩ on the GaAs substrate 1. 5 Ga
O,5A S first cladding layer 2 is grown, AΩo 5
Gao, 5A GaA on the first cladding layer 2
An s-waveguide layer 3 is grown. On the GaAs waveguide layer 3, there is a rib portion AΩo, Ga 0.5 A
An S second cladding layer 4 is formed.

第1図に示した半導体光導波路の製造方法について以下
に述べる。GaAs子基板1上に、分子線エピタキシャ
ル成長法(MBE法)もしくは有機金属気相成長法(M
O−CVD法)を用いて、A41’ o、G a o、
5 A s第1クラッド層2、GaAs導波層3、Aj
? 0.5 G a o、s A S第2クラッド層4
を成長する。各層の厚さは、AgO,5G a o、5
 A s第1クラッド層2が1〜2μm程度、GaAs
導波層3が0.2μn+程度、AΩo5G a o、5
 A s第2クラッド層4が1.2μm程度である。
A method for manufacturing the semiconductor optical waveguide shown in FIG. 1 will be described below. A molecular beam epitaxial growth method (MBE method) or a metal organic vapor phase epitaxy method (M
O-CVD method), A41' o, G a o,
5 As first cladding layer 2, GaAs waveguide layer 3, Aj
? 0.5 Gao, s A S second cladding layer 4
grow. The thickness of each layer is AgO,5G ao,5
As the first cladding layer 2 has a thickness of about 1 to 2 μm and is made of GaAs.
Waveguide layer 3 is about 0.2 μn+, AΩo5G a o, 5
The second cladding layer 4 has a thickness of about 1.2 μm.

以上のように結晶を成長させた後、導波路リブ部をRI
BE法によって形成する。この工程の概要を第2図に示
す。まず第2図(a)のように、通常のフォトリソグラ
フィ法を用いて、GaAs/AjJGaAsウェハ10
上に形成すべき導波路形状のフォトレジストマスク11
を形成する。次に、第2図(b)のように反応性の低い
Arガスを用いた第1のエツチング工程によって前記フ
ォトレジスト11で覆われていない部分を0.1μm程
度エツチングする。このとき、フォトレジストマスク1
1は高々0.1μm程度エツチングされる程度である。
After growing the crystal as described above, the waveguide rib portion is RI
Formed by BE method. An outline of this process is shown in Figure 2. First, as shown in FIG.
Waveguide-shaped photoresist mask 11 to be formed on
form. Next, as shown in FIG. 2(b), the portion not covered with the photoresist 11 is etched by about 0.1 μm by a first etching process using Ar gas with low reactivity. At this time, photoresist mask 1
1 is etched by about 0.1 μm at most.

この後に、1度エツチングチャンバーを真空引きした後
に、今度は反応性の高いC(12ガスを用いた第2のエ
ツチング工程によって前記フォトレジスト11に覆われ
ていない部分をさらに0.9μm程度エツチングする。
After this, the etching chamber is evacuated once, and then a second etching step using highly reactive C (12 gas) is performed to further etch the portion not covered by the photoresist 11 by about 0.9 μm. .

この後、前記フォトレジスト11を有機溶剤等で除去す
ると、第2図(c)のような半導体光導波路が得られる
Thereafter, when the photoresist 11 is removed using an organic solvent or the like, a semiconductor optical waveguide as shown in FIG. 2(c) is obtained.

以上が本発明による半導体光導波路の製造方法の実施例
であり、上述の製造方法によるとエツチング深さの制御
性が改善される原理を以下に説明する。
The above is an embodiment of the method for manufacturing a semiconductor optical waveguide according to the present invention, and the principle by which the controllability of the etching depth is improved by the above-mentioned manufacturing method will be explained below.

従来、ドライエツチングによるエツチング深さの制御性
は、エツチングされるウエノ1の表面状態に依存してお
り、はじめから反応性の高いガスを用いたドライエツチ
ングを行なうとウエノ\の表面状態によってエツチング
深さがバラついてしまっていた。これに対して本実施例
は、はじめに反応性の低いArガスを用いた第1のエツ
チング工程によって0.1μm程度ウエノ1表面をスノ
々・ソタエ、ソチングしているので、エツチング深さは
ウエノ\の表面状態には依存せず、また、新たに真空中
におて清浄なエツチング面を出すことができる。さらに
、反応性の低いガスであるから、このエツチング界面に
おいて分子が結合に関与することは少ない。このため、
第1のエツチング工程終了後は常に同一状態の清浄なエ
ツチング面が得られることになる。この後に、はじめて
反応性の高いCΩ2ガスを用いた第2のエツチング工程
を行なっているので、エツチング深さの制御性が、はじ
めからCΩ2ガスでのみ行なわれるエツチングに比べて
改善される。さらに、第1のエツチング工程の後に反応
性の高いCD2ガスによる第2のエツチング工程を行な
っているので、終始Arガスでエツチングする場合に比
ベマスクとの選択比が確保され、マスクの後退による垂
直性の低下の心配が無い上に、エツチング面のダメージ
が少なくなる。
Conventionally, the controllability of the etching depth by dry etching depends on the surface condition of the wafer 1 to be etched, and if dry etching is performed using a highly reactive gas from the beginning, the etching depth will vary depending on the surface condition of the wafer. Things were falling apart. On the other hand, in this embodiment, the surface of the wafer 1 is soothed by about 0.1 μm in the first etching process using Ar gas with low reactivity, so the etching depth is as low as 0.1 μm. It does not depend on the surface condition of the etched surface, and a clean etched surface can be newly exposed in a vacuum. Furthermore, since it is a gas with low reactivity, molecules are less likely to participate in bonding at this etching interface. For this reason,
After the first etching step is completed, a clean etched surface in the same state is always obtained. After this, the second etching step using the highly reactive CΩ2 gas is performed, so that the controllability of the etching depth is improved compared to etching performed only with the CΩ2 gas from the beginning. Furthermore, since the second etching process using highly reactive CD2 gas is performed after the first etching process, a selectivity with respect to the comparison mask is ensured when etching is performed with Ar gas from beginning to end, and vertical etching due to mask recession is ensured. There is no need to worry about deterioration in quality, and there is less damage to the etched surface.

なお、本実施例においては、RIBE法を用いたが、こ
れに限るものではなく、例えば他のドライエツチング法
として反応性イオンエツチング(RIE)法であっても
本発明は適用できる。また、第2のエツチング工程にお
いてCΩ2を用いたか、反応性が高ければこれに限るも
のではなく、例えば、BC,Q3であってもよいし、B
r2てあってもよい。
Although the RIBE method was used in this embodiment, the present invention is not limited to this, and the present invention can also be applied to other dry etching methods such as reactive ion etching (RIE). In addition, CΩ2 was used in the second etching step, or it is not limited to this as long as it has high reactivity; for example, BC, Q3 may be used, or B
It may be r2.

(発明の効果) 以上に述べたように、本発明によれば、リブ部形成時の
ドライエツチング工程において、ウェハの表面状態によ
らず、エツチング深さの制御性が改善される。さらに、
マスクとの選択比も確保され、マスクの後退による垂直
性の低下の心配が無いうえに、エツチング面のプラズマ
ダメージが少ない。
(Effects of the Invention) As described above, according to the present invention, the controllability of the etching depth is improved in the dry etching step when forming the rib portion, regardless of the surface condition of the wafer. moreover,
The etching selectivity with respect to the mask is ensured, there is no concern that the perpendicularity will deteriorate due to mask recession, and there is little plasma damage to the etched surface.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の方法で製造したG a A
 s / AΩGaAs半導体光導波路の構造を示す断
面図、第2図はその実施例におけるエツチング工程を示
す概念図である。 1−G a A s基板、2−AΩo、G a o、5
 A s第1クラッド層、3・・・GaAs導波層、4
−AΩ。、 5 G a o、 5 A S第2クラッ
ド層、10・・・G a A s / AΩGaAsウ
ェハ、11・・・フォトレジストマスク。 第 1 図 第 図 (a) 第 図 (b) 第 図 (c)
FIG. 1 shows G a A produced by the method of one embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the structure of the s/AΩGaAs semiconductor optical waveguide, and a conceptual diagram showing the etching process in the embodiment. 1-GaAs substrate, 2-AΩo, Gao, 5
As first cladding layer, 3...GaAs waveguide layer, 4
-AΩ. , 5 Gao, 5 A S second cladding layer, 10... Ga As/AΩGaAs wafer, 11... Photoresist mask. Figure 1 Figure (a) Figure (b) Figure (c)

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に少なくとも半導体第1クラッド層、半導
体導波層および半導体第2クラッド層を積層して積層構
造半導体ウェハを形成する工程と形成しようとする光導
波路の形のエッチング用マスクを前記積層構造半導体ウ
ェハ上に設ける工程と、前記マスクで覆われた部分以外
の半導体第2クラッド層をエッチングにより除去してリ
ブ型光導波路を形成する工程とを含む半導体光導波路の
製造方法において、前記マスクで覆われた部分以外の半
導体第2クラッド層をエッチングにより除去してリブ形
光導波路を形成する工程が、比較的反応性の低いガスに
よる第1のエッチング工程と比較的反応性の高いガスに
よる第2のエッチング工程とが連続して行なわれる工程
であることを特徴とする半導体光導波路の製造方法。
A step of laminating at least a semiconductor first cladding layer, a semiconductor waveguide layer, and a semiconductor second cladding layer on a semiconductor substrate to form a laminated semiconductor wafer, and applying an etching mask in the form of an optical waveguide to be formed to the laminated structure. In the method for manufacturing a semiconductor optical waveguide, the method includes a step of providing the second cladding layer on a semiconductor wafer, and a step of removing the semiconductor second cladding layer other than the portion covered by the mask by etching to form a rib-type optical waveguide. The process of removing the semiconductor second cladding layer other than the covered portion by etching to form a rib-shaped optical waveguide consists of a first etching process using a gas with relatively low reactivity and a second etching process using a gas with relatively high reactivity. 1. A method for manufacturing a semiconductor optical waveguide, characterized in that the second etching step and the second etching step are successively performed.
JP2077690A 1990-01-31 1990-01-31 Production of optical waveguide of semiconductor Pending JPH03225302A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2077690A JPH03225302A (en) 1990-01-31 1990-01-31 Production of optical waveguide of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2077690A JPH03225302A (en) 1990-01-31 1990-01-31 Production of optical waveguide of semiconductor

Publications (1)

Publication Number Publication Date
JPH03225302A true JPH03225302A (en) 1991-10-04

Family

ID=12036555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2077690A Pending JPH03225302A (en) 1990-01-31 1990-01-31 Production of optical waveguide of semiconductor

Country Status (1)

Country Link
JP (1) JPH03225302A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610606B2 (en) 2001-03-27 2003-08-26 Shiro Sakai Method for manufacturing nitride compound based semiconductor device using an RIE to clean a GaN-based layer
JP2007081115A (en) * 2005-09-14 2007-03-29 Sony Corp Method for manufacturing semiconductor light emitting element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610606B2 (en) 2001-03-27 2003-08-26 Shiro Sakai Method for manufacturing nitride compound based semiconductor device using an RIE to clean a GaN-based layer
JP2007081115A (en) * 2005-09-14 2007-03-29 Sony Corp Method for manufacturing semiconductor light emitting element

Similar Documents

Publication Publication Date Title
CN100546135C (en) The manufacture method of semiconductor laser with tunable and semiconductor laser with tunable
US4932032A (en) Tapered semiconductor waveguides
US6252725B1 (en) Semiconductor micro epi-optical components
US4944838A (en) Method of making tapered semiconductor waveguides
JPH0677205A (en) Microscopic structure forming method for compound semiconductor
US3883219A (en) Dielectric optical waveguide
JP2752851B2 (en) Manufacturing method of optical waveguide
JPH03225302A (en) Production of optical waveguide of semiconductor
EP0363547B1 (en) Method for etching mirror facets of III-V semiconductor structures
JP2015156440A (en) Dissimilar semiconductor substrate and manufacturing method therefor
JP2932441B2 (en) Method for manufacturing semiconductor optical waveguide
EP0411816B1 (en) Tapered semiconductor waveguides and method of making same
JP2827376B2 (en) Method for manufacturing semiconductor optical waveguide
JP3019271B2 (en) Optical waveguide formation method
JPH06109934A (en) Semiconductor optical waveguide
JP3175688B2 (en) Optical connection device and method of manufacturing the same
JPS62128586A (en) Manufacture of optoelectronic integrated circuit
JPS6223191A (en) Manufacture of ridge type semiconductor laser device
JPH04229679A (en) Semiconductor laser
JPH063541A (en) Waveguide type grating and its production
JP2002319739A (en) Method for manufacturing rib-shape optical waveguide distributed reflection type semiconductor laser
JPH03243904A (en) Semiconductor optical waveguide
JPH09293926A (en) Semiconductor device and its manufacture
JPH05157919A (en) Semiconductor optical waveguide and its production
CN118311723A (en) Method for realizing efficient optical coupling of laser and waveguide on silicon