JPH03224371A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To attain high speed horizontal transfer by outputting picture information from two horizontal transfer registers transferring each half of photo charges at the left and right sides of a pickup section in opposite directions horizontally respectively as 2-bit parallel serial data. CONSTITUTION:When horizontal transfer registers 12A, 12B complete the transfer by 1H, a picture memory 21 outputs all row information sets of a memory array 22 corresponding to a reserved row address sequentially from an address (00000) from an output port 25 serially. The signal is D/A converted as required to be a video signal. Through the constitution of a solid-state image pickup element above, since picture information is outputted from two output sections 13A, 13B as 2-bit parallel serial data, the horizontal transfer is finished in a half time in comparison with the solid-state image pickup element of single horizontal transfer register constitution. Moreover, since the transfer function of the horizontal transfer registers 12A, 12B is made identical entirely, longitudinal stripe of a reproduced picture having been inevitable in the solid-state image pickup element of a conventional multi horizontal transfer register constitution is not caused.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a solid-state image sensor capable of high-speed horizontal transfer operation.

(b) Prior Art A conventional solid-state image sensing device will be explained with reference to FIG. The figure shows an interline type solid-state image sensor (40), which is an example of a solid-state image sensor, in which the outputs of a plurality of light receiving sections (41) arranged in a matrix and the light receiving sections (4] in each column are input in parallel. Vertical transfer registers (42+) to (42□), horizontal transfer registers (43) to which the outputs of vertical transfer registers (421) to (42Y) are input in parallel, and output charges of horizontal transfer registers (43) to voltage or It is shown with an output (44) which converts it into a current.

The light receiving section (41) is arranged in a matrix of, for example, 400 x 500 pixels, and the two-dimensional image information photoelectrically converted by the light receiving section (41) is first transferred by the vertical transfer registers (42+) to (42ffi). Converted to m-focus parallel/serial image information. Next, the outputs of these vertical transfer registers (421) to (42°) are input in parallel to the horizontal transfer register (43), where each row is converted into serial image information by the transfer operation, and then sent to the output section (44).
Serial output via .

The high definition of the solid-state image sensor (40) configured as described above is achieved by increasing the density of pixels in the vertical and horizontal directions of the light receiving section (41). Vertical transfer register (
42,) to (42,,), if the transfer speed of the horizontal transfer register (43) is made faster, an incomplete transfer failure occurs in which the photocharges are not completely transferred.

In order to solve this problem, a solid-state imaging device having a multi-horizontal transfer register configuration as shown in a conceptual diagram in FIG. 4 has been proposed. In this solid-state image sensor (50), the image information of the imaged area (51) is stored in horizontal transfer registers (52) (53) every other column.
) is entered. Since the horizontal transfer registers (52) and (53) horizontally transfer half of the image information of the imaging section (51), a relatively low-speed transfer operation is allowed. However, since the channel lengths between the horizontal transfer registers (52) (53) formed in parallel and the imaging section (51) are different, the charge transfer level between the horizontal transfer registers (52) (53) is different.
There is a problem that vertical stripes occur in the reproduced image. Furthermore, in order to realize a solid-state image sensor having such a structure, a three-layer polysilicon gate process is required, which poses a problem of complicating the process.

(...) Problems to be Solved by the Invention The present invention aims to solve the problems existing in conventional solid-state image sensors, and provides a device that can be manufactured using a two-layer polysilicon gate process and has a high-speed horizontal transfer operation. The purpose of the present invention is to provide a solid-state image sensor capable of

(d) Means for Solving the Problems The above-mentioned problems are such that the imaging section is formed symmetrically with the imaging section that captures an optical image to obtain two-dimensional photocharges and transfers the photocharges in the vertical direction. two horizontal transfer registers that transfer the photocharges of each half of the left and right sides in opposite left and right directions;
The solid-state imaging device of the present invention is comprised of two output sections that convert the output charge of each horizontal transfer register into voltage or current, and the data of the output section is converted into a video signal via an image memory. 12 solved by the element.

(Wed) Effect Image information is output as 2-bit parallel serial data from two horizontal transfer registers that transfer photocharges from each half of the left and right halves of the imaging section in opposite directions, so a single horizontal transfer register configuration is used. Horizontal transfer is completed in half the time compared to the solid-state one-zoom element. Further, since the two horizontal transfer registers are formed symmetrically, the transfer functions of the two horizontal transfer registers are completely the same. Furthermore, manufacturing using a relatively easy two-layer polysilicon gate process becomes possible.

(F) Embodiment FIG. 1 is a block diagram illustrating the concept of the solid-state image sensor and its peripheral signal processing circuit of the present invention, in which the solid-state image sensor (10) includes an image sensor (11), an image sensor (11), and an image sensor (10). Horizontal transfer register (to 12) (12B) into which 1/'2 image information of 11) is input on each side and transferred in the opposite direction.
and an output section (to 13) (13B), and the peripheral signal processing circuits include an A/D converter (20A) (20B), a memo array (22), a row address decoder (23),
It is shown as an image memory (21) consisting of column address decoders (24A) (24B) and an output port (25).

The solid-state image sensor (10) can be used as a solid-state image sensor using either the interline transfer method or the frame transfer method. It also corresponds to the light receiving section and storage section of a frame transfer type solid-state image sensor. The imaging section (11) has the same structure as the conventional one.

The two-dimensional image information converted into photocharges in the imaging section (11) is simultaneously transferred to the horizontal transfer registers (12A) (12B) for each row of the imaging section (11) by a transfer operation in the vertical direction of the drawing. As shown by the broken line in the figure, the image information of the left half of the imaging section (11) is input to the horizontal transfer register (12A), and is horizontally transferred to the left through the horizontal transfer register (12A). Further, image information of the right half of the imaging section (11) is input to the horizontal transfer register (12B), and horizontally transferred to the right through the horizontal transfer register (12B). Therefore, the image information on the left half of the imaging section (11) is output from the output section (13A) sequentially from the left side of the drawing, and at the same time, the image information on the right half is output from the output section (13B) sequentially from the right side of the drawing. The output of these output parts (13A) (13B) is A/
A'D conversion is performed by the 'D converter (2OA) (2 ('IB)) and the image is temporarily stored in the image memo IJ (21).

The row address decoder (23) of the image memory (21) operates in synchronization with the vertical transfer operation of the imaging section (11), and
11), one of the word lines of the memory array (22) whose size is the number of horizontal pixels x the number of vertical pixels x one word is periodically selected. The column address decoders (24A) and (24B) each have a scale to address 1/2 of the number of horizontal pixels of the imaging unit (11), and the column address decoders (24A
) is specified in order from address (00000>), and the A/
Parallel data from the D converter (20A) is output to a plurality of corresponding bit lines. In addition, the column address decoder (
The address specified by column address decoder (24B) has a true complement relationship with that of column address decoder (24A), and is (00000).
'= Addresses are specified in order starting from address (11111), and parallel data from the A/D converter (20B) input to the column address decoder (24B) is output to the corresponding plural bit lines. These column address decoders (24
A) (24B) is the horizontal transfer register (12A) (12B
) operates in synchronization with the transfer operation.

When the vertical transfer operation of the imaging section (11) is started, the row address decoder (23) specifies an address (OOOOOO), for example. And horizontal transfer register (12A) (12
In synchronization with the transfer operation of B), the column address decoder (
24A) and (24B) are address (00000) and (
11111) If you specify an address, A/D conversion! (20A
) is stored at address (OO000) of the memory array (22) specified by the row address decoder (23) and column address decoder (24A),
Parallel data from the A/D converter (20B) is stored at address (11111) of the memory array (22). In addition,
For convenience of explanation, only column addresses will be used as addresses of the memory array.

By the subsequent transfer operation of the horizontal transfer registers (12A) (12B), the parallel data of the A/'D converter (20A) is specified by the column address decoder (24A) (OO
A/'D converter (20B
) parallel data is sent to the column address decoder (24B
) is stored at the address specified by (oooool)"=(zzo). In the same manner, the image information of the imaging unit (11) is stored in the memory array (22), and
2), image information is stored in correspondence with the imaging unit (11).

Then, the horizontal transfer registers (12A) (12B)
When the image memory (21) completes the transfer operation, the image memory (21) transfers all row information of the memory array (22) corresponding to the saved row address to the output port (21) in order from address (OOOOOO).
5) Serial output. This signal is
/A conversion and then converted into a video signal. Note that the two column address decoders of the image memory (21) are essential, but other than these, any system and configuration of the image memory can be used.

According to the solid-state image sensor having the above configuration, two output sections (13
A) Since the image information is output from (13B) as 2-bit parallel serial data, horizontal transfer is completed in half the time compared to a solid-state image sensor having a single horizontal transfer register configuration. In addition, horizontal transfer registers (12A) (12B
), it is possible to make the transfer functions exactly the same.
Vertical stripes do not occur in the reproduced image, which is inevitable in conventional solid-state image sensing devices having a multi-horizontal transfer register configuration.

Referring to FIGS. 2(A), (B) and (C), horizontal transfer registers (12A) (12B) perform horizontal transfer in opposite directions, respectively.
) structure and operation will be explained.

Figure 2 (A) shows horizontal transfer registers (12A) (12B)
Although not shown, a buried channel is formed in the surface layer of the 81 substrate (30) by means such as ion implantation, and a horizontal transfer register (12A) ( 12B), the first layer silicon gate (31Al + ) (31Bl + ) (31Al
! )(3181l) and second layer polysilicon gates (31A, )(318!1)(3L42.n(31B++)) are formed.

First, when transfer lock φ1 is set to high level and φ is set to low level, the potential profile becomes as shown in FIG. 2(B), and the first layer polysilicon gate (31, A11 ) (A deep potential well is formed below 31B, and photocharges are simultaneously transferred to this potential well from a vertical transfer register or storage section (not shown).

Subsequently, when the transfer length φ, is set to a low level and φ, is set to a high level, as shown in FIG. A deep potential well is formed below. Figure 2 (B) (C)
As is clear from the comparison of transfer locks φ1, φ,
The potential well is formed to move away from the boundary of the horizontal transfer registers (12A) (12B) to the left and right each time the level of the potential well changes. In this way, the photocharges previously accumulated in the potential wells under the first layer polysilicon gates (31A+) (31B) are sequentially transferred to the horizontal transfer register (31A+) (31B).
13A), the data is transferred to the left, and the horizontal transfer register (13B) is transferred to the right.

The horizontal transfer registers (13A) and (13B) having the above structure are formed symmetrically, and can be formed to have exactly the same functions except for the transfer direction. Therefore, the horizontal transfer register (
13) The levels of the photocharges output from (13B) are completely equal, and there is no difference in brightness between the right half and the left half of the reproduced image.

(G) Effects of the Invention As stated above, the solid-state image sensor of the present invention requires half the time required for horizontal transfer as compared to a solid-state image sensor with a single horizontal transfer register configuration, and therefore is a high-definition solid-state image sensor. It is also relatively slow and can therefore be operated in full transfer mode.

Further, since the transfer functions of the symmetrically formed horizontal transfer registers are exactly the same, variations in brightness etc. do not occur in the reproduced image.

Furthermore, it can be manufactured using a relatively easy two-layer polysilicon gate process.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, and FIG. 2 (
A) is a partial sectional view of the horizontal transfer register of the present invention, FIGS. 2(B) and 4(C) are potential profiles of the horizontal transfer register at different timings, and FIGS. 3 and 4.
The figure is a block diagram of a conventional solid-state image sensor. 10...Solid-state imaging device, 11...Imaging unit, 1
2A, 12B...Horizontal transfer register, 13A, 1
3B... Output section, 20A, 20B-=A/D converter, 21 - Image memory, 22A, 22B... Memory array, 23... Row address decoder,
24A24B Column address decoder, 25
...Output hoard. Dejunjin Sanyo Electric Co., Ltd.

Claims (3)

[Claims] (1) An imaging section that captures an optical image to obtain two-dimensional photocharges and transfers the photocharges in a vertical direction; It consists of two horizontal transfer registers, and two output sections that convert the output charge of each horizontal transfer register into voltage or current, and the data in the output section is converted into a video signal via an image memory. A solid-state image sensor characterized by: (2) The solid-state image pickup device according to claim 1, wherein the image pickup section includes a light receiving section and a storage section. (3) The image memory includes two column address decoders that output addresses in a true complement relationship, and data from the two output sections is simultaneously stored at addresses designated by each column address decoder. Solid-state image sensor.