JP3501693B2 - Color imaging device and imaging system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color image pickup device and an image pickup system, and more particularly to a color image pickup device and an image pickup system for reading out signals of a plurality of colors from a plurality of pixels.

[0002]

2. Description of the Related Art Solid-state image pickup devices having color filters are used in various video equipment such as video cameras for taking moving images and electronic still cameras for taking still images.

In recent years, due to the progress of semiconductor technology, an image pickup device having several million pixels has been developed and put into practical use in an electronic still camera or the like which requires high resolution. Even a camera with a higher resolution than that may be required to be able to shoot a moving image (not necessarily having a high resolution). However, such a high-resolution camera is for still images, and it is difficult to capture a moving image. This is because as the number of pixels increases, the time required to read out the signal from the image sensor increases in proportion to the increase in the number of pixels.

In order to solve this problem, conventionally, when shooting a moving image, the number of pixels is substantially increased by setting the read-out frequency of the signal of the image pickup device higher than that in the case of a still image or by thinning out the signal of the image pickup device. A technique for reading with a reduced number of times has been proposed.

[0005]

However, the above-mentioned image pickup apparatus has the following problems.

Since a temporary storage capacity is required for each color signal, the area of the storage capacity becomes large and the chip cost increases. Further, it is difficult to design many capacitors with the same shape for each column, and there is a problem that the capacitance value of each storage capacitor varies. In particular, when the variation is removed from the signal in order to remove the variation of the pixel amplifier, the variation in capacitance causes deterioration of SN.

When outputting for each color signal, variations in signal processing circuits in the subsequent stages deteriorate image quality. For example, A /
Non-linearity of the D converter and variations in accuracy cause color changes.

When reading an image pickup device with a high pixel count in the low pixel count mode, moire occurs in the thinning mode, and there is a drawback that the photographing field angle changes when a part of the device is used.

It is an object of the present invention to provide a low-cost image pickup apparatus by reducing the chip area by reducing the temporary storage capacity, and to make the signal paths after reading each color signal the same so that the color signals are Is to improve the image quality.

[0010]

A color image pickup device according to the present invention comprises a plurality of pixels arranged in a horizontal direction and a vertical direction,
First and one provided for each of a plurality of pixels in the vertical direction
A second vertical output line, first and second memories, and
The signals from the first memory and the second memory are output.
Is provided commonly to the first and second memories.
The signal from the horizontal output line and the first vertical output line
A first transfer transistor for transferring to the first memory;
The signal from the first vertical output line is sent to the second memory.
A second transfer transistor for transferring and the second vertical output
A third transfer for transferring the signal from the force line to the first memory.
The signal from the transmission transistor and the second vertical output line
Fourth transfer transistor for transferring to the second memory
And reading out signals of a plurality of colors from the plurality of pixels
Means and the signals of the plurality of colors are added for each color, and line-sequentially
Drive means for outputting from the horizontal output line.
And are characterized.

An image pickup system of the present invention comprises the color image pickup device of the present invention, an optical system for forming light on the color image pickup device, and signal processing means for processing an output signal from the color image pickup device. It is characterized by

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is an explanatory view of a signal output method by the color image pickup apparatus of the present invention, showing a general Bayer array in which Gs are arranged in a checkered pattern between R and B and an output signal thereof. . 2A shows an example in which a pixel row signal is read out line by line in a dot-sequential manner, and FIG. 2B shows an example in which a pixel row signal is read out line by line (sequentially) in the same color, in FIG. (C)
Color signal is read line-sequentially, G signal is added diagonally from two pixel rows, and R and B signals are added horizontally and read. In FIG. 2D, R and B signals are read. In this example, the signals are added in the horizontal and vertical directions, G signals between R and B are selected, and diagonally added and read.

FIG. 1 is a circuit configuration diagram showing an embodiment of a color image pickup apparatus of the present invention for performing the signal output method of FIG. In the pixel portion, two vertical pixels are connected to a common amplifier.

The vertical output lines VS1, VS2, ... Are connected to memories (capacitances) CT1, CT2, ... As signal holding means via transfer transistors TS11, TS21 ,. Here, the number of memories corresponding to each vertical signal line is as small as one.
That is, in FIGS. 2C and 2D, addition is performed for each color, but when signals for R, G, and B three colors are added simultaneously, three systems of memory are required, but in this embodiment, By controlling the transfer transistors TS11, TS21, ..., Signals from two vertical output lines can be transferred to one memory (or signals from one vertical output line can be transferred to either or both of the two memories). Therefore, it is only necessary to provide one system of memory, and addition can be performed with a small number of memories. As described above, there are many memories when a plurality of colors are added at the same time, but the addition can be performed with a small number of memories by sequentially adding each color. Here, the memory corresponding to each vertical output line is 1
Although it is provided one by one, when reading the noise signal to remove the noise component of the signal read from the pixel, a separate memory for noise is provided, so the number of memories corresponding to the vertical output line is the same as the signal memory and the noise. Two memory are provided.

Therefore, the memory area can be very small. Further, since the number of memories is small, it is easy to design the signal memory and the noise memory similar to each other.
Therefore, the accuracy of removing noise from the signal is improved and the SN is improved. As described above, two vertical output lines are connected to the memory of one system via the transfer switch (transfer transistor). By this connection, signals of a plurality of lines can be transferred to the memory.

The correspondence between each means according to the present invention and this embodiment will be described. The reading means corresponds to the vertical shift register V-SR11 of FIG. 10 described later, and the driving means corresponds to the horizontal shift register of FIG. 10 described later. The shift register H-SR13 and the transfer transistors TS11 to TS42 of FIG.
Is applicable. A horizontal output line corresponds to the output means.

FIG. 7 is a diagram showing a configuration of two pixels using a common amplifier. As shown in FIG. 7, a11 and a21 are photodiodes that serve as photoelectric conversion units of each pixel, MSF is an amplifying transistor that serves as a common amplifier, and MTX1 and MTX2 represent signal charges accumulated in the photodiodes as input units of the common amplifier. Floating diffusion area (FD area)
, MRES is a reset transistor for resetting the FD region, and MSEL is a selection transistor for selecting a common amplifier pixel. The transistors MSF and MSEL form a source follower circuit. In the two pixels of the common amplifier, signals from two photodiodes are output through the common amplifier, and the two pixels form one unit cell. One pixel includes a photodiode, a transfer transistor, and a part of a common circuit including a common amplifier, a reset transistor, and a selection transistor.

FIG. 3 is a timing chart of the signal output method of FIG. In FIG. 3, the memory for noise accumulation of the common amplifier and the transfer means for transferring noise to the memory are omitted.

First, the signal φMRES is set to the H level to reset the gate of the common pixel amplifier to remove the residual charge in the gate portion. After that, noise transfer is performed.

Next, the signals φMTX1, φMTX2, φSEL are set to H level to turn on the transfer transistors MTX1, MTX2 and the selection transistor MSEL, and the signals φTS1, φTS4 are set to H level to set the transfer transistors TS11, TS12, TS41,
.. are turned on, and pixels G11, G13, ..
, And the R signals from the pixels R12, R14, ... Are transferred to the memories CT1, CT2 ,. A dot-sequential signal is output from the horizontal output line by sequentially setting the output pulse hmn (h11, h12, h13, ...) To the H level for the memory signal. The V2 line and the subsequent lines are similarly driven.

FIG. 4 is a timing chart of the signal output method of FIG. In FIG. 4, the G signal of the V1 line is first transferred to the memory and then output from the horizontal output line, and then the R signal is transferred to the memory and then output from the horizontal output line.

First, the signal φMRES is set to H level to reset the gate of the common pixel amplifier to remove the residual charge in the gate portion. After that, noise transfer is performed.

Next, the signals φMTX1 and φSEL are set to H level to turn on the transfer transistor MTX1 and the selection transistor MSEL, and the signals φTS1 and φTS3 are set to H level to turn on the transfer transistors TS11, TS12, TS31, TS32, .... , V1 lines transfer the G signals from the pixels G11, G13, ... To the memories CT1 and CT2, CT3 and CT4 ,. In this case, since the G pixel signal is transferred to and stored in two memories, the output pulses are h11, h12, and h during output.
13 and h14, ... are in phase. By transferring to two memories, the read gain from the memory to the horizontal output line is twice as large in this embodiment as in the embodiment shown in FIG. When the read method shown in FIG. 3 and the read method shown in FIG. 4 are switched and used depending on the system, the read gain is adjusted by a PGA (programmable gain amplifier) described later.

FIG. 5 is a timing chart of the signal output method of FIG. 2 (C). In FIG. 5, G signals are first transferred on the V1 line and the V2 line, respectively, and when the horizontal output lines are output from the memory, the G signals in the diagonal direction are added. Then V1
The R signal on the line is transferred, and the horizontal R signal is similarly added on the horizontal output line. Similarly, the B signal is transferred on the V2 line and the horizontal B signal is added on the horizontal output line. In this case, the read gain is the same as in the embodiment of FIG.

In reading the G signal, first, the signal .phi.MRES is set to the H level to reset the gate of the common pixel amplifier to remove the residual charge in the gate portion. After that, noise transfer is performed.

Next, the signals φMTX1 and φSEL are set to H level to turn on the transfer transistor MTX1 and the selection transistor MSEL, and the signal φTS1 is set to H level to turn on the transfer transistors TS11, TS12, ...
G signals from 11, G13, ... Are stored in memories CT1 and C, respectively.
Transfer to T3, ...

Next, the signal φMRES is set to the H level to reset the gate of the common pixel amplifier to remove the residual charge in the gate portion. After that, noise transfer is performed.

Further, the signals φMTX2 and φSEL are set to the H level, and the transfer transistor MTX2 and the selection transistor MSEL are set.
Is turned on, the signal φTS4 is set to the H level, the transfer transistors TS41, TS42, ... Are turned on, and the G signals from the pixels G22, G24 ,.
Transfer to CT4, ... When outputting, the output pulse is h11 and h1
2, h13 and h14, ... are in phase. Therefore, G11 + G2
The addition signal of 2, G13 + G24, ... Is output from the horizontal output line.

To read the R signal, first, the signal .phi.MRES is set to the H level to reset the gate of the common pixel amplifier to remove the residual charge in the gate portion. After that, noise transfer is performed.

Next, the signals φMTX2 and φSEL are set to the H level to turn on the transfer transistor MTX2 and the selection transistor MSEL, and the signals φTS2 and φTS4 are set to the H level to set the transfer transistors TS21, TS22, ..., TS41, TS42 ,. When turned on, the R signal from the pixel R12 is stored in the memory CT on the V1 line.
1 and CT2, R signals from pixel R14 are stored in memories CT3 and CT
4, transfer to ... When outputting, the output pulse is h11, h12,
By setting h13, h14, ... to H level, R12 + R14,
The addition signal of ... Is output from the horizontal output line.

Although not shown in FIG. 5, the read operation of the B signal is similar to the read operation of the R signal except that the V signal is transferred to the memory by setting φTS1 and φTS3 to H level. , B21 + B23, ... Addition signals are output from the horizontal output line.

FIG. 6 is a timing chart of the signal output method of FIG. In FIG. 6, first, with respect to the V1 line, the signal φMRES is set to the H level to reset the gate of the common pixel amplifier to remove the residual charge in the gate portion. After that, noise transfer is performed.

Further, the signals φMTX2 and φSEL are set to the H level, and the transfer transistor MTX2 and the selection transistor MSEL are set.
Is turned on, the signal φTS4 is set to H level, the transfer transistors TS41, TS42, ... Are turned on, and the R signals from the pixels R12, R14 ,.
Transfer to CT4, ...

Similarly, for the V3 line, after the residual charges are removed and noise is transferred, the signals φMTX2 and φSE are similarly extracted.
The L level is set to the H level to turn on the transfer transistor MTX2 and the selection transistor MSEL, and the signal φTS2 is set to the H level to turn on the transfer transistors TS21, TS22 ,.
The R signals from the pixels R32, R34, ... Are transferred to the memories CT1, CT3 ,.

When transferring signals from the memory to the horizontal output lines, each of the four signals stored in the memories CT1 to CT4, ... (R pixels arranged in the vertical and horizontal directions (for example, R pixels).
12, R14, R32, R34) signals are added. Therefore, the output pulse from the horizontal shift register is in-phase (h11, h12, h13, h14, h15, h16,
h17, h18, ... Are in phase with each other.

Next, after the signals of the pixels G22, G24, ... Of the V2 line are transferred to the memories CT2, CT4, ..., The signals of the pixels G31, G33 ,.
.. are transferred, and the output pulse from the horizontal shift register is in-phase (h11 and h12, h13 and h14, h15) every two pulses.
, And h16, ... Have the same phase), the G signals of the pixels G22 and G31, the pixels G24, and the pixels G33, ... In the diagonal direction from the V2 line and the V3 line are added and read.
In this example, G on the V1 and V4 lines is not used.

Next, four signals (signals from B pixels (for example, B21, B23, B41, B43) arranged in the vertical and horizontal directions) are added by the V2 line and the V4 line, respectively. Although this timing is omitted in FIG. 6, addition reading can be performed in the same manner as addition reading of the R signal.

In FIG. 6, the horizontal resolution can be improved by using G of 2 lines. In this case, the read gain is twice R and B compared with the embodiment shown in FIG.
Are the same. The SN ratio of R and B is √2 by addition.
Doubled and G is the same.

Although the embodiment of the present invention has been described above with reference to FIGS. 2C and 2D, the addition of each color signal is not limited to this. For example, G signals may be added in the horizontal direction or the vertical direction, or a complementary color filter may be used.

In addition, for example, in a pixel section in which color filters having the first, second, third, and fourth colors are arranged, the first timing is set at the first timing in reading a signal from a predetermined block in the pixel section. Add the color signal and the second color signal,
The third color signal and the fourth color signal may be added at the next timing.

FIG. 8 shows an example in which the number of pixels connected to the common pixel amplifier is horizontal and vertical. By doing so, the vertical output lines and transfer switches can be reduced, and the aperture ratio of the pixel can be increased and the chip area can be further reduced.

The present invention does not need to use a common amplifier as shown in FIGS. 7 and 8, and a single amplifier may be provided for each pixel, and addition of color signals is performed by three pixels instead of two pixels. Of course, the above may be sufficient.

FIG. 10 is a block diagram showing an embodiment of an image pickup system using a color image pickup device.

The image pickup device 1 includes a pixel region 10 and a vertical shift register (V-SR) 11 for controlling pixels line by line.
A memory 12 that temporarily stores (or adds) a signal and noise from a pixel, a horizontal shift register (H-SR) 13 that outputs (or adds) a signal of the memory 12 to a horizontal output line, from the memory 12 , A programmable gain amplifier PGA15 capable of changing the signal gain from the AMP14 for removing the noise of the pixel amplifier from the signal of A, the A / D converter 16 for converting the output signal of the PGA15 into a digital signal, V-SR11, H- SR
13, a memory 12, a PGA 15, and a timing generator / control circuit 17 for controlling the A / D converter 16
Is built in. Light is imaged on the image sensor 1 by an optical system 6 having a diaphragm.

The DSP 3 performs image processing of a moving image or a still image. Further, the CPU 4 sets parameters used in this image processing in the DSP 3, and controls the image sensor 1, the diaphragm of the optical system 6, and the like.

The storage device 2 is an image recording medium such as a DRAM, a smart medium, a magnetic tape, an optical disk or the like as a temporary storage area for image processing. Further, an I / F circuit 5 for transferring signals to a display device such as a CRT for displaying after image processing and a recording device such as a printer is provided.

When the image pickup device 1 switches between the addition read mode and the all-pixel read mode, and dot-sequential scanning and line-sequential scanning, the CPU 4 judges the mode and the image pickup device 1 and the DSP 3 correspond to the respective modes. It takes the configuration to send the signal. Here, the timing generator / control circuit 17 switches the timing as shown in FIGS. 3 to 6 depending on the moving image / still image.

FIG. 9 is an explanatory diagram of the adjustment gain for each output signal method. With reference to the gain of the embodiment shown in FIG. 3, -6 dB is adjusted in the embodiments of FIGS. 4 and 5, R and B signals are adjusted to -12 dB, and G signal is adjusted to -6 dB in the embodiment of FIG.

Next, a specific structure of the unit cell that can be preferably used in the image pickup apparatus of the present invention will be described.

In the arrangement shown in FIG. 18, since the arrangement of the photoelectric conversion units 173 does not have an equal pitch (a1 ≠ a2), the intervals of the regions (light receiving units) that sense light in each pixel are not equal. The following problems occur. That is, an array having the same color and not having a uniform pitch causes a decrease in resolution and defects such as moire fringes because the spatial frequency and the resolution are partially not equal. Further, the generation of moire fringes is a very serious problem, and such an image pickup device cannot be practically used as a product. This also holds true when the number of pixels forming the unit cell is other than four.

In the CMOS sensor having the amplifying means dispersed in a plurality of pixels, the inventors of the present invention make the intervals of the respective light receiving parts equal by making the pitch of the photoelectric conversion parts constant, resulting in a decrease in resolution. We have found an imaging device that can prevent moire fringes, improve the aperture ratio, and obtain good performance. Such an imaging device can be preferably used in the present invention.

In FIG. 11, the pixels in the 2nd row and the 2nd column are the common amplifier section 2
It is a figure which shows the example which shares 2. In FIG. 11, the shared common amplifier section 22 is arranged at the center of the four pixels, and the four photoelectric conversion sections (a11, a12, a21, a22) are arranged so as to surround the common amplifier section 22. Here, in the common amplifier section 22, the amplification means MSF and the reset means MSE of FIG.
In addition to L and selection means MSEL, transfer means MTX1 to MTX4 are included.

In addition, the light shielding portion 25 is present at a position centrally symmetrical to the area of each pixel occupied by the common amplifier portion 22. Therefore, the center of gravity of the photoelectric conversion unit 21 in each pixel exists at the center of each pixel. As a result, the four photoelectric conversion units (a11 to a22) can be arranged at equal intervals a in the vertical and horizontal directions.

Further, in FIG. 12, the shared common amplifier section 3 is shared.
2 is arranged in the center of the four pixels in the horizontal direction, and the four photoelectric conversion units 31 (a11, a12, a21, a22) are arranged so as to sandwich the common amplifier unit 32.

Moreover, the light-shielding portion 35 is present at a position centrally symmetrical to the area of each pixel occupied by the common amplifier portion 32. Therefore, the center of gravity of the photoelectric conversion unit 31 in each pixel exists at the center of each pixel. As a result, the four photoelectric conversion units (a11 to a22) can be arranged at equal intervals a in the vertical and horizontal directions.

The above-described embodiment shown in FIG. 12 is completely the same even if the horizontal direction and the vertical direction are interchanged.

FIG. 13 shows a specific pattern layout diagram of the first configuration example of the pixel array section of the CMOS sensor.

The CMOS sensor shown in FIG. 13 is formed on a single crystal substrate by a layout rule of 0.4 μm, the size of a pixel is 8 μm square, and the source follower amplifier which is an amplifying means is a 2 × 2 4 matrix. It is shared by pixels. Therefore, the repeating unit cell 8 shown in the dotted line area in the figure
The size of 1 is 16 μm × 16 μm square, and a two-dimensional array is formed.

Photodiode 82a, which is a photoelectric converter,
82b, 82c, and 82d are formed obliquely at the center of each pixel, and their shapes are substantially rotationally symmetrical and mirror-image symmetrical in the vertical and horizontal directions. In addition, these photodiodes 82a, 82a
The centers of gravity g of b, 82c and 82d are designed to be the same for each pixel. Reference numeral 95 is a light shielding portion.

88-a is a scanning line for controlling the upper left transfer gate 83-a, 90 is a row selection line, and 92 is a MOS gate 9.
3 is a reset line for controlling 3.

The signal charges accumulated in the photodiodes 82a to 82d pass through the transfer gates 83a to 83d and become FD.
Guided to 85. The MOS size of the gates 83a to 83d is L = 0.4 μm, W = 1.0 μm (L is the channel length,
W indicates the channel width. ).

The FD 85 is connected to the input gate 86 of the source follower by an Al wiring having a width of 0.4 μm,
The signal charge transferred to the FD 85 modulates the voltage of the input gate 86. The size of the MOS of the input gate 86 is L =
0.8 μm, W = 1.0 μm, and the sum of the capacitances of the FD 85 and the input gate 86 is about 5 fF. Since Q = CV, the input gate 86 is obtained by accumulating 10 ⁵ electrons.
Will change by 3.2V.

The current flowing from the VDD terminal 91 is modulated by the input gate 86 and flows out to the vertical output line 87.
The current flowing out to the vertical output line 87 is signal-processed by a signal processing circuit (not shown), and finally becomes image information.

After that, the photodiodes 82a to 82d,
The MOS gate 9 connected to the reset line 92 in order to set the potentials of the FD 85 and the input gate 86 to VDD of a predetermined value.
3 is opened (the transfer gates 83a to 83d are also opened at this time), the photodiodes 82a to 82d, the FD 85, and the input gate 86 are short-circuited to the VDD terminal.

After that, the transfer gates 83a to 83d are closed, and the charge accumulation in the photodiodes 82a to 82d starts again.

It should be noted that all of the wirings 88a to 88d, 90, 92 penetrating in the horizontal direction are formed of ITO (Indium Tin Oxide) having a thickness of 1500Å which is a transparent conductor. Light is transmitted through the photodiodes 82a to 82d in the wiring portion, so that the center of gravity g of the photodiode coincides with the center of gravity of the light sensing area (light receiving portion).

According to the present configuration example, it is possible to provide a CMOS sensor having a relatively high area ratio and a high aperture ratio with the same pixel pitch.

FIG. 1 is a specific pattern layout diagram of the second configuration example of the pixel array section of the CMOS sensor of the present invention.
4 shows.

In FIG. 14, 102a to 102d are photodiodes, 103a to 103d are transfer gates, 10
5 is an FD, 106 is an input gate of a source follower, 10
7 is a vertical output line, 108a to 108d are scanning lines, 110
Is a row selection line, and 112 is a reset line for controlling the MOS gate 113.

In this configuration example, the wiring 1 running in the horizontal direction
Since three 08a to 108d, 110, and 112 run so as to cross the center of each pixel, even if the metal wiring that blocks the light incident on the photodiodes 102a to 102d, it is possible to detect The center of gravity g does not move and therefore coincides with the center of the pixel.

According to this configuration example, since a normal (opaque) metal having a small electric resistance can be used, the time constant of the wiring in the lateral direction can be improved, and a higher speed image pickup device can be provided.

In the above configuration example, since the portion under the light shielding film is effectively used, as shown in FIG. 15, the photodiode which is the photoelectric conversion portion is formed up to the portion under the light shielding film, and the charge storage portion is formed. It is also possible to function as.

In the above-mentioned second configuration example, since the center of the pixel having the highest light converging efficiency is crossed, there is a concern that the sensitivity of the image pickup device may be lowered. Therefore, a further improved third configuration example is shown in FIG.

In this configuration example, the transfer gates 123a ...
123d, FD125, source follower input gate 1
26, wirings in which all the reset MOS gates 133 run in the horizontal direction (scanning lines 128a to 128d, row selection line 13)
0, the reset line 132), the photodiodes 122a to 122d and their openings can be maximized. Moreover, the opening exists continuously at the center of each pixel. Further, the light shielding portion is formed in the horizontal and vertical wiring portions.

Further, in the present configuration example, since the source follower which is the amplifying means and the reset MOS transistor are divided and arranged in the horizontal direction around each pixel, it can be arranged compactly under the horizontal wiring. ing.

Further, since there is still an unused space under the wiring of the pixel on the upper right, for example, a smart sensor,
It is also possible to add a new configuration.

According to the present configuration example, since the area of the photodiode and the aperture ratio can be made large, it is possible to provide an image pickup device having a wide dynamic range and high sensitivity.
Further, as miniaturization progresses in the future, even if the size of the opening portion of the photodiode becomes about the wavelength of light, it is unlikely that light will not enter and the performance can be exhibited for a long time.

Further, in the above configuration example, the amplifying means is arranged in the central portion of the unit cell, and the center of gravity of the light sensing area and the center of the pixel coincide with each other, but not limited to these.
A configuration in which the openings are translationally symmetrical as shown in FIG. 17 may be used.

That is, since the openings are translationally symmetric, the light sensing areas have an equal pitch.

[0081]

As described above, according to the present invention, the chip area can be reduced and the color image pickup device can be provided at a low cost.

Since each signal is passed through the same signal processing system, there is little variation between signals and high image quality can be achieved.

Furthermore, high-definition readout for reading out all of each pixel provides high image quality, and addition signal readout for pixel signals can reduce the drive frequency to improve the SN ratio, thus achieving low power consumption. At that time, there is also a great effect that the angle of view of the photographing optical system is the same in the high definition mode and the addition reading mode.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a color imaging device of the present invention.

FIG. 2 is an explanatory diagram of a signal output method by the color imaging device of the present invention.

FIG. 3 is a timing diagram of the signal output method of FIG.

FIG. 4 is a timing diagram of the signal output method of FIG.

5 is a timing diagram of the signal output method of FIG. 2 (C).

FIG. 6 is a timing diagram of the signal output method of FIG.

FIG. 7 is a diagram showing a configuration of two pixels using a common amplifier.

FIG. 8 is a diagram showing a configuration of four pixels using a common amplifier.

FIG. 9 is an explanatory diagram of an adjustment gain for each output signal method.

FIG. 10 is a block diagram showing an embodiment of an image pickup system using a color image pickup device.

FIG. 11 is a diagram showing a layout of a unit cell of the present invention.

FIG. 12 is a diagram showing a layout of a unit cell of the present invention.

FIG. 13 is a pattern layout diagram of a configuration example of the present invention.

FIG. 14 is a pattern layout diagram of a configuration example of the present invention.

FIG. 15 is a diagram illustrating a configuration example of the present invention.

FIG. 16 is a pattern layout diagram of a configuration example of the present invention.

FIG. 17 is a diagram showing a configuration example of the present invention.

FIG. 18 is a layout diagram of a unit cell of an example of an imaging device.

[Explanation of symbols]

MTX1, MTX2 transfer transistor MSEL selection transistor TS11 to TS42 transfer transistor CT1-CT4 memory VS1 to VS4 Vertical output line

Claims (8)

(57) [Claims] 1. A plurality of units arranged horizontally and vertically
Pixel, and the first and second pixels provided for each of the plurality of pixels in the vertical direction.
A signal is output from the second vertical output line, the first and second memories, and the first memory and the second memory.
Shared by the first and second memories.
The horizontal output line and the signal from the first vertical output line to the first memory.
A first transfer transistor for transferring and a signal from the first vertical output line to the second memory.
A second transfer transistor for transferring and a signal from the second vertical output line to the first memory.
A third transfer transistor for transferring and a signal from the second vertical output line to the second memory
A fourth transfer transistor for transferring and a read-out device for reading out signals of plural colors from the plural pixels
And the signals of the plurality of colors are added for each color, and the horizontal output is performed line-sequentially.
A driving device for outputting the force line, and a color imaging device. 2. The color image pickup apparatus according to claim 1 , wherein the addition of at least one color signal among the additions of the signals of the plurality of colors is addition in the horizontal direction and / or the vertical direction and / or the diagonal direction. A color imaging device characterized in that there is. 3. The color image pickup device according to claim 1 , wherein unit cells in which a plurality of photoelectric conversion units and a common circuit to which signals from the plurality of photoelectric conversion units are input are arranged are arranged. One of the pixels includes one of the photoelectric conversion units in the unit cell and a part of the common circuit, and at least two color signals of the plurality of color signals are output through the common circuit. And a color imaging device. 4. The color image pickup device according to claim 3 , wherein the common circuit has an amplifier that amplifies a signal from the photoelectric conversion unit. In the color imaging device according to any one of claims 5. The method of claim 1-4, color imaging, characterized in that it comprises means for switching said plurality of colors signals sequentially or output or line sequential output point apparatus. 6. The color image pickup device according to claim 1 , wherein a line-sequential read-out gain is controlled by the same amplifier. 7. The color image pickup apparatus according to claim 3 or 4, to connect the signal holding means that is shared for the photoelectric conversion units in the unit cell to the vertical output line, the common circuit from the photoelectric conversion portion An image pickup apparatus, wherein a signal is read out to the signal holding means via a. 8. A color image pickup device according to claim 1 , an optical system for forming an image of light on the color image pickup device, and a signal processing means for processing an output signal from the color image pickup device. An imaging system comprising: