JPH03222517A - Semiconductor logic circuit device - Google Patents

Abstract

PURPOSE:To eliminate the need for matching the logic threshold voltage of an input circuit with a TTL level in varying a ratio of a CMOS gate even for the input signal of the TTL level by providing a circuit shifting the voltage of an input signal. CONSTITUTION:An input buffer section has a level shift circuit comprising a PNP transistor(TR) 3 and diodes 4, 5, its base input is connected to the output of an input protection circuit 2 and the output is connected to the gate of a PMOSFET 9 of the input circuit. On the other hand, the gate of an NMOSFET 8 is connected directly to the output of an input protection circuit 2. Thus, a signal inputted from an input signal pad 1 is inputted to the gate of the PMOSFET 9, then the signal is shifted positively by a voltage depending on the level shift circuit. Thus, even when an external input signal is the input signal of a TTL level, it is not required to match a logic threshold voltage of the input circuit with the TTL level by varying a ratio of the CMOS gate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor logic circuit device, and particularly to a circuit configuration of an input buffer when realizing a TTL level interface.

[Conventional technology]

Figure 6 shows the conventional complementary MO8 (hereinafter referred to as 0MO8)
It is a diagram showing an input buffer circuit of a logic circuit device, for example, as shown in Tokusushi Publication No. 62-244149. In this circuit, the input signal is passed through the input protection circuit.
It is directly input to the CMOS gate. In this case, the matching of the interface level with the outside is determined by the ratio of the CMOS gate, that is, the ratio of the P-channel MO5 field effect transistor (hereinafter referred to as PMO5FET) to the he-channel type IVI (JSt field effect transistor (hereinafter referred to as NfViO
This was done by changing the ratio of current drive capability with respect to the 8FET (referred to as 8FET) and changing the logical threshold voltage. For example, ]
When realizing a level interfnis (under stor Logiclt, referred to as TTL), NMUSFET and PMO
5FET have the same channel length, NMU
This was achieved by making the channel width of the SFET considerably larger than that of the PMO8FET.

[Problem to be solved by the invention]

However, in the above-mentioned CMO5 input buffer, if an 'I゛TL level interface is realized, the channel width of NMUSFET is larger, so NMO5
Since the current drive capability of the FET is much larger than that of the PMO3FET, the balance between the rise and fall of the output waveform becomes unbalanced. In particular, when the load capacitance of the output becomes large, the propagation delay time of the rising edge becomes longer than that of the falling edge, so there is a drawback that it is difficult to secure a duty for a high-speed input signal. Furthermore, the input is 2
．． In the case of 4V (TTL large input logic e (minimum voltage of Hll)), a current path is created from the positive gap to the ground, which has the disadvantage of increasing current consumption.

This invention was made to solve the above problems, and even if the external input signal is a TTL level input signal, the logic threshold voltage of the input circuit can be changed by changing the ratio of the CMOS gate. It is an object of the present invention to obtain a semiconductor logic circuit device that does not require adjustment to the '11'L level.

[Means for Solving the Problems] A semiconductor logic circuit device according to the present invention has an input buffer section that adjusts the voltage of an input signal to a level. The output of the level shift circuit is applied to the gate of a field effect transistor of one conductivity type, and the input signal that is not level shifted is applied to the gate of a field effect transistor of another conductivity type. It was made to be done.

[Effect]

In the semiconductor logic circuit device of the present invention, even if the external input signal is a TTL level input signal, the PIVIO5
The signal applied to the gate of the FET becomes higher by the level-shifted voltage, and the signal applied to the gate of the 1MO5FET in the input circuit
can be completely switched. Therefore, the logic threshold voltage of the input circuit can be changed to T by changing the ratio of the CMOS gate.
Since it is not necessary to adjust to the TL level and a 1MO5FET with sufficient driving force can be used, the duty of a high-speed input signal can be maintained. Furthermore, since PMO5FE'I' can be completely turned off even when the input is 2.4■, power consumption is reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a bipolar complementary MO8 (
1 is a diagram showing a logic circuit device (hereinafter referred to as BiCMO3). This logic circuit device has a level shift circuit using an emitter follower circuit consisting of a PNP transistor (3), a diode (4), and (5J) in the input buffer section, and its base input is connected to the output of the input protection circuit (2). and its output is connected to the gate of 1MO5FET (9) of the input circuit.On the other hand, the gate of NMOSFEi' (3) is directly connected to the output of the input protection circuit (2).This allows the input signal pad ( The input signal from 1) is PIV
When input to the gate of lo 5 FET (9), the voltage is shifted in the positive potential direction by a voltage determined by a level shift circuit using an emitter follower circuit consisting of a PNP bipolar transistor (3) and diodes (4) and (5). shift to

Next, the operation of the BiCMO5 logic circuit device shown in FIG. 1 will be explained using FIG. 2. External input signal is 'l' T
When at L level, the input current is O, OV according to the standard.
When the voltage is 0.8V from the logic 11o"c' ant, 2.4■
From 5. When OV, logic is “-”. Then, NMO5
The voltage of the signal applied to the gate of FET (s) is the same as that of the input signal, so when the input signal is logic II Oll, NMO8FET(s) is OFF, and when the input signal is logic "1", NMO5FET(s) is OFF. ) is ON. Also, the signal applied to the gate of 1MO5FET (9) is the level shift circuit (3), (4), (
5), the minimum voltage 2.4V of the logic degree 11'' at the L level of '1''I' increases by the level-shifted voltage, that is, 2.1■, and becomes 4.5■.

Similarly, when the logic of the input signal is "'O", 1MO
The gate voltage of 5FET (9) is from 2.1■ to 2.9V
It is. When the logic of the input signal is 1'', PM (JSFE
The gate voltage of T(9) will be 4.5v. and PIV
I (JSFET (9) turns ON when the input signal logic is ゛O'', and turns OFF when the input signal logic is ゛11''.
Therefore, the input circuit PIQiOS FET (9) can be completely switched.

FIG. 3 is a diagram showing a second embodiment of the invention.

In this second embodiment, the configuration of the first embodiment described above is used, but resistors (6) (7) and capacitors PMO3FETQ51.
gtl, a circuit consisting of NMO8FETαη, and a configuration for cutting off the power supply using a power down signal (g) is added. With the above configuration, when the power down signal (g) is H (high level), the power to the level shift circuit is cut off during standby, so current consumption is reduced. At this time, a level shift circuit (3) using an emitter follower
, (4).

Since no power is applied to (5), the base current of the PNP bipolar transistor (3) becomes zero, and no input current flows.

FIG. 4 is a diagram showing a third embodiment of the present invention.

In this third embodiment, a CMOS buffer circuit is used as one input buffer circuit after the level shift circuit in the configuration of the first embodiment described above. In this third embodiment, Bi
Although a CM (JSS buffer circuit) was used in place of the CMUS buffer circuit, similar effects can be expected in this case as well.

FIG. 5 is a diagram showing a fourth embodiment of the present invention.

In this fourth embodiment, two PNs are used as the level shift circuit.
Emitter followers with Darlington connections of P bipolar transistors (3), (11) are used.

In this fourth embodiment, by using the Darlington-connected PNP bipolar transistor (3) and Q'l, the current amplification factor is increased, so that the input current flowing to the input pad can be further reduced.

As mentioned above, there are two diodes (4) in the level shift circuit using PNP bipolar transistors.

(Although the present invention is not limited to the above embodiment, a PNP bipolar transistor (3) and two In order to make the shift voltage of the level shift circuit composed of diodes (4) and (5) different from that in this embodiment, the number of these diodes may be changed as appropriate, and the same effect as above is expected. can.

〔Effect of the invention〕

As described above, according to the present invention, the PMO of the input buffer
Since the gate voltage of the 8FET is configured to apply a voltage shifted in a positive direction from the 1'T L level, the current consumption of the input buffer circuit is reduced, and the number of stages in the cascade connection of the input buffer circuits is reduced. This has the advantage of being fast.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a logic circuit device according to a first embodiment of the invention, FIG. 2 is a diagram explaining the operation of the logic circuit device shown in FIG. 1, and FIG. 3 is a diagram showing a second embodiment of the invention. A diagram showing
FIG. 4 is a diagram showing a third embodiment of the invention, FIG. 5 is a diagram showing a fourth embodiment of the invention, and FIG. 6 is a diagram showing a conventional single logic circuit device. In the figure, (1) is an input signal pad, (2) is an input protection circuit, (3), Ql is a PNP bipolar transistor, (4) and (5) are diodes, (6), (1.
ILl is a resistor, (7) is a power supply, (3), q7! is NM(
JSFhT, (9), Ql, 4 is PfVl (JSFET
% (6), a4 is an NPN bipolar transistor,
α is the output signal pad, and Bi is the power down signal. In each figure, the same reference numerals indicate the same or equivalent parts. 1 Input 17 Nomatsu 2 N force protection case 3: PNP transistor or evening hand, 5 diode A, /θ, IIl force (or Figure 1 7: electric row, &: NI-jO5FET 7 P gate 05FE diode/ 2 13:NPN transistor l+ Ewabutsudo

Claims (1)

[Claims] In a semiconductor logic circuit device in which an input buffer section includes field effect transistors of two different conductivity types, the semiconductor logic circuit device has a circuit for level shifting the voltage of an input signal, and the output of the level shift circuit is shifted by field effect transistors of one conductivity type. 1. A semiconductor logic circuit device, wherein an input signal is applied to a gate of a field-effect transistor of a conductivity type, and an input signal whose level is not shifted is applied to a gate of a field-effect transistor of another conductivity type.