JP2562831B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION [Overview] A level conversion circuit for converting a level from an ECL level to a DCFL level, with the object of obtaining a stable output level against fluctuations in threshold voltage without using a reference voltage. , A logic inverting unit including a Darlington-connected enhancement type field effect transistor supplied with an ECL level input voltage, and a level shift unit for level shifting the output voltage of the logic inverting unit by a source follower circuit including an enhancement type field effect transistor. Becomes
A DCFL level voltage is taken out from the level shift unit.

[Industrial applications]

The present invention relates to a level conversion circuit, and more particularly to ECL level to D
The present invention relates to a level conversion circuit that converts a level to a CFL level.

When an integrated circuit is constructed using FETs such as high electron mobility transistors (HEMTs) that use Schottky junctions, selectively doped double hetero (SD-DH) FETs, and GaAs MES FETs, a direct coupling type FET
Logic (direct coupling FET logic: DCFL) circuits are widely used. In this DCFL circuit, when the power supply voltage is −2V, the high level is about −1.2V and the low level is about −1.9V.

On the other hand, among integrated circuits using bipolar transistors, an emitter-coupled logic (emitter coup
led logic (ECL) circuits are widely used. In this ECL circuit, the high level is regulated to about -0.8V and the low level is regulated to about -1.8V.

Therefore, when transmitting a logic signal from the ECL circuit to the DCFL circuit, a level conversion circuit for converting the ECL level to the DCFL level is required. It is important that this level conversion circuit can perform level conversion stably even with respect to fluctuations in threshold value.

[Conventional technology]

FIG. 3 shows a circuit diagram of an example of a conventional level conversion circuit. In the figure, D ₁₀ , D ₁₁ and D ₁₂ are depletion type N-channel field effect transistors (FET), and E ₁₀ is an enhancement type N-channel field effect transistor (FE).
T) is shown. Hereinafter, in the present specification, the depletion type FET is indicated by adding the alphabet D to the suffix, and the enhancement type FET is indicated by adding the alphabet E to the suffix.

Transistor D ₁₀ has a source connected to the drain of the transistor D _11, also between the gate and source of the transistor D ₁₁ are connected, these D ₁₀ and D ₁₁ constitute a level shift unit. The transistor D ₁₁ constitutes a constant current source. Further, a gate connected to the common connection point of the transistors D ₁₀ and D _11, transistors E ₁₀ whose gate and source are respectively connected transistor D ₁₂ to its drain constitutes the logic inverting unit together with the transistor D _12. A power supply voltage of -3.6 V is applied to the gate and source of the transistor D ₁₁ , while -2 V is applied to the source of the transistor E _10.
The power supply voltage of V is applied.

The operation of the conventional level conversion circuit having such a configuration will be described. ECL from input terminal 1 to the gate of transistor D ₁₀
When the high level voltage of −0.8V is input,
The source of the transistor D ₁₀ is level-shifted by the gate-source threshold voltage of D ₁₀ (for example, about −0.2 V) and applied to the gate of the transistor E ₁₀ , which is turned on.

Therefore, the drain current of the transistor E ₁₀ flows,
Since the drain current also flows through the transistor D ₁₂ , the output terminal 2 has a power supply voltage of −1.9V which is approximately equal to −1.9V, that is, DC.
The low level of FL level is taken out.

On the other hand, input terminal 1 has a low-level voltage of ECL level −
When 1.8V is input, this input voltage is
It is level-shifted by D ₁₀ and applied to the gate of transistor E ₁₀ . At this time, the gate voltage of the transistor E ₁₀ is approximately equal to its source voltage −2 V, so
₁₀ is off.

Here, although the output terminal 2 is not shown in the drawing, the DCFL of the next stage
The gate of the input transistor of the circuit is connected, and the source of the input transistor is applied with a power supply voltage of -2V.

Therefore, when the transistor E ₁₀ is turned off as described above, about 0 V is about to be output to the output terminal 2,
The transistor is a FET using a Schottky junction, and when a voltage of 0.8 V or more is applied between its gate and source, the junction is forward biased and a large current starts to flow between the gate electrode and the channel. Therefore, the transistor
When E ₁₀ is turned off as described above, the output voltage of the output terminal 2 becomes about -1.2V, which is 0.8V higher than the -2V of the source voltage of the input transistor, and the high level of DCFL level is taken out.

The conventional level conversion circuit shown in FIG. 3 has a circuit configuration in which logic inversion is performed after performing level shift.
As another conventional level conversion circuit, there is also a circuit configuration in which the level shift is performed after the logic inversion as shown in FIG.

In FIG. 4, D _{13 to} D ₁₉ are depletion type N, respectively.
The channel FETs, E ₁₁ and E _12, are enhancement type N-channel FETs, respectively. Transistors D _{13 to} D ₁₅ and
E ₁₁ and E ₁₂ form a logic inversion unit by a differential amplifier, and the input terminal 1 is connected to the gate of the transistor E ₁₁ and the reference voltage V _REF input terminal 3 is connected to the gate of the transistor E ₁₂ . .

Further, the transistors D ₁₆ and D _{17 form} a first level shift section, the transistors D ₁₈ and D _{19 form} a second level shift section, and the source follower circuit of D ₁₆ and D ₁₈ forms an output terminal 2a, Outputs voltages of different logical values to 2b. The power supply voltage is -3.6V.

In the level conversion circuit having such a configuration, the input reference voltage V _REF of the input terminal 3 is the ECL high level (−0.8 V).
And low level (-1.8V) intermediate voltage.
Therefore, when a high ECL level is input to the input terminal 1, the transistor E ₁₁ turns on and E ₁₂ turns off, and the DCFL from the common connection point of the source of the transistor D ₁₆ and the drain of D _{17 to} the output terminal 2a. Low level about -1.
9V is taken out and the source of transistor D ₁₈ and D
_For the same reason as above, the output voltage at the common connection point of the ₁₉ drains (output terminal 2b) is about −1.
It becomes 2V.

On the other hand, when the ECL low level is input to the input terminal 1, the transistor E ₁₁ turns off and E ₁₂ turns on. Therefore, the output voltage of the output terminal 2a is the DCFL level high level, contrary to the above case. And the output voltage of output terminal 2b is DCFL.
It becomes the low level of the level.

[Problems to be Solved by the Invention]

The conventional level conversion circuit shown in FIG. 3 has the feature that the number of elements is small and the circuit configuration is simple, but on the other hand, in the source follower circuit by the transistor D ₁₀ which performs the level shift function, the depletion type is relatively poor in controllability Since the characteristic of the FETD ₁₀ is dominant, it is weak against the characteristic variation of the FET and the input logic threshold value largely varies.

FIG. 5 shows the transistors D ₁₀ and D of the conventional circuit shown in FIG.
₁₁ threshold V _TD from −0.3 V to −0.8 V in units of −0.1 V, and transistor E ₁₀ threshold V _TE
Shows the input / output voltage characteristics when it is kept constant with V. As can be seen from FIG. 5, in the conventional circuit shown in FIG. 3, the input logic threshold value fluctuates more than the threshold fluctuations of the transistors D ₁₀ and D ₁₁ .

On the other hand, since the conventional level conversion circuit shown in FIG. 4 performs logic inversion first, it has the advantage that it is strong against input voltage fluctuations, but on the other hand, a separate reference voltage V _REF generation circuit is required, and the number of elements is increased. There is a drawback that it increases. Further, there is a drawback that the reference voltage generation circuit requires high accuracy because it is greatly affected by the fluctuation of the reference voltage V _REF .

Furthermore, since the conventional level conversion circuits shown in FIGS. 3 and 4 both need to use a negative voltage (-3.6V) from the power supply voltage used for the DCFL circuit, a plurality of power supplies and power supply Need a source.

The present invention has been made in view of the above points, and an object of the present invention is to provide a level conversion circuit that can obtain a stable output level with respect to a change in threshold voltage without using a reference voltage. .

[Means for solving the problem]

In order to achieve the above object, the present invention comprises a logic inversion unit using an enhancement type field effect transistor and a level shift unit of a source follower circuit using the enhancement type field effect transistor.

[Action]

The logic inverting unit to which the ECL level input voltage is supplied performs logic inversion by connecting enhancement type field effect transistors with good controllability in a Darlington connection.

The level shifter is supplied with the output voltage of the logic inversion unit described above, and the source follower circuit of the enhancement type field effect transistor outputs the DCFL level voltage by sufficiently lowering the low level without lowering the high level too much. .

In the present invention, since the logic inversion section first performs the logic inversion of the ECL level input voltage, the output voltage of the logic inversion section can be set to a high-level or low-level circuit-specific value even if the input voltage varies. Moreover, since the logic inversion unit uses the enhancement-type field effect transistor having good controllability, the influence of the characteristic variation is small.

Further, since the logic inversion unit uses field effect transistors connected in Darlington, the reference voltage can be eliminated.

Further, when the output voltage of the logic inverting unit is low level, the level shift unit can level shift to a low level of a predetermined DCFL level by the same enhancement type field effect transistor as the Darlington-connected field effect transistor.

On the other hand, when the output voltage of the logic inversion unit is high level,
High enough even if the level is shifted by the level shift section.
Since it is determined by the clamp voltage of the input diode of the connected DCFL circuit, if its value is a certain value or more, its variation does not matter. That is, the level shifter need only pay attention to the low level value, the same power supply voltage as that of the DCFL circuit can be used, and the influence of characteristic variation is small.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the level conversion circuit of the present invention. In the figure, 4 is a logic inverting section, which is a series of drain-gate enhancement-type N-channel field-effect transistors E ₁ and E ₂ connected in Darlington and transistors D ₁ and E ₂ connected in series. It comprises three depletion-type N-channel field effect transistors D ₁ , D ₂ and D ₃ . Transistor D ₁ above
~ D ₃ constitutes a load element section.

Since between the transistor D ₁ to D ₃ and its gate and drain are short-circuited, the transistor D ₁ to D ₃ operates in its linear region, it is to the drain current even threshold varies does not fluctuate There is. Also, the transistors D _{1 to} D ₃ are FETs using a Schottky junction, and between the gate and source
If a voltage of 0.8 V or more is applied, a large current will flow between the gate and channel.Therefore, in order to prevent this large gate current from flowing when the power supply voltage is −2 V, the transistors are set as shown by D _{1 to} D _3. 3 are used (in this case,
If it is more than 2.4V, a large gate current will not flow. ).

Reference numeral 5 denotes a level shift section, which comprises an enhancement-type N-channel field effect transistor E ₃ and a depletion-type N-channel field effect transistor D ₄ having a source follower circuit configuration. The transistor D ₄ is connected from the drain thereof to the source of the transistor E ₃ and the output terminal 2, and the gate and source thereof are short-circuited to form a constant current source. The drains of the transistors E ₁ and E ₂ are connected to the gate of the transistor E ₃ , respectively. Further, both the logic inversion unit 4 and the level shift unit 5 have a power supply voltage of −2V.

Next, the operation of this embodiment will be described. Now, when -0.8 V, which is a high level of the ECL level, is input to the input terminal 1, the transistors E ₁ and E ₂ are turned on. Here, assuming that the voltage between the drain of the transistor E ₁ and the source of E ₂ connected in Darlington is about 0.3 V, the gate input voltage of the transistor E _{3 in} the next stage (that is, the output voltage of the logic inverting unit 4) Vm is about -1.7V (= -2V + 0.3V).

Since the voltage Vm at this time is higher than the low level of the DCFL level by the threshold voltage of the transistor E ₂ ,
By using the same enhancement type as E ₂ for the level shift transistor E ₃ of the next stage, the above threshold voltage is compensated.

Transistor E ₃ applies this voltage Vm to its threshold voltage of 0.
Level-shift to the lower side by about 2V, and output terminal 2 is about -1.
Outputs low level of 9V DCFL level.

On the other hand, the input terminal 1 has a low ECL level −
When 1.8V is input, the transistors E ₁ and E ₂ are turned off. Therefore, the voltage Vm becomes about 0V. Therefore,
If nothing is connected to output terminal 2, output terminal 2
Is about -0.2V.

However, the gate of the input transistor (or input diode) of the DCFL circuit (not shown) is connected to the output terminal 2, and if the Schottky junction of this input transistor adds 0.8V or more to the gate-source voltage as described above, the shot The key junction is forward biased and a large gate current flows. That is, if the output voltage of the output terminal 2 is Vm equal to or higher than a constant voltage (about −1 V), the transistor E ₃
In spite of the level shift caused by, the large gate current flows in the input transistor of the DCFL circuit, and the output voltage of the output terminal 2 is 0.8V higher than the source voltage of the input transistor -2V
It is clamped to the gate voltage of 1.2V (this is the high level of DCFL level).

In this embodiment, when the input voltage to the input terminal 1 is at the low level of the ECL level, the voltage Vm is about 0V, which is sufficiently higher than the constant voltage as described above, and therefore the output voltage of the output terminal 2 is at the DCFL level. High level of about -1.2V. That is, in the present embodiment, it is not necessary to consider the influence of the level shift when the DCFL level is output at the high level, and only the low level need be considered. Therefore, the transistor D ₄ does not require a constant current characteristic so much, the same power supply voltage as that of the DCFL circuit can be used, and the influence of the characteristic variation of the transistor D ₄ is small.

FIG. 2 shows the threshold values of the transistors D _{1 to} D ₄ of this embodiment.
The input / output voltage characteristics are shown when V _TD is changed from -0.3 V to -0.8 V in units of -0.1 V, and the threshold voltage V _TE of the transistors E _{1 to} E ₃ is kept constant at 0.25 V. As can be seen from FIG. 2, the circuit of this embodiment shown in FIG.
Be varied threshold is D ₁ to D _4, enables a very stable level variation operation.

〔The invention's effect〕

As described above, according to the present invention, the depletion type FET
It is possible to perform a stable level change operation even with respect to the change of the threshold value of, and since the reference voltage is not required in the logic inversion unit, the reference voltage generation circuit can be eliminated, so that the number of components is shown in FIG. Compared to the conventional circuit shown, it can be reduced, and since the same power supply voltage can be shared by the logic inversion unit and the level shift unit, the power supply system can be simplified. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an input / output voltage characteristic diagram of FIG. 1, FIG. 3 is a circuit diagram of a conventional example, and FIG. 4 is a circuit of another conventional example. 5 and 5 are input / output voltage characteristic diagrams of FIG. In the figure, 1 is an input terminal, 2 is an output terminal, 4 is a logic inversion section, 5 is a level shift section, E ₁ , E ₂ , and E ₃ are enhancement type N-channel field effect transistors, and D _{1 to} D ₄ are depletion type. 3 shows an N-channel field effect transistor.

Claims (1)

(57) [Claims] 1. A logic inverting section (4) comprising enhancement type field effect transistors (E ₁ and E ₂ ) connected in Darlington connection to which an ECL level input voltage is supplied, and a source comprising enhancement type field effect transistor (E ₃ ). A level shift section (5) for level-shifting the output voltage of the logic inversion section (4) by a follower circuit, and a DCFL level voltage is taken out from the level shift section (5). Conversion circuit.