JPH03219738A - Pcm terminal station equipment - Google Patents

Abstract

PURPOSE:To identify to which order bit a data in a prescribed timing of a clock corresponds by inserting a marker to a designated bit of a data signal. CONSTITUTION:A PCM signal inputted to a PCM signal input terminal 1 is converted into an 8-bit 1.544MHz burst signal by an AND gate 5 with a clock at a channel designation clock terminal 2 and converted into a digital signal by a serial/parallel shift register 6. The signal is converted into a 64kb/s data signal at a parallel/serial shift register 7. In this case, a designation switch 11-2 designates a test bit to, e.g. 1st bit and when a test switch 11-1 is closed, an output of a bit selection one-shot trigger 10 enters a differentiating circuit 13 through an AND gate 12 and a differentiating signal is fed to an AND gate 14, in which a marker is inserted to a designation bit of a 64kb/s data signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PCM terminal station device having a function of measuring the timing of data signals and clocks of the PCM terminal station device.

C. Prior Art] In a PCM 6 station device, data on a predetermined communication path is converted into a 64 Kb/s data signal using multiplexed PCM signals, and the data signal is sent to a transmission path at a predetermined timing. FIG. 6 is a diagram for explaining this PCM terminal equipment, in which 1 is a PCM signal input terminal, 2 is a communication path designation clock terminal, 3 is a 1,544 MHz clock signal input terminal, and 4 is a diagram for explaining this PCM terminal equipment. is a 64Kz clock input terminal, 5 is an AND gate, 6 is a serial-parallel shift register, 7 is a parallel-serial shift register, 8 is an interface, and 9 is a data output terminal.

In this configuration, the PCM signal input to the PCM signal input terminal 1 is input to the AND gate 5 by the communication path designation clock.
The signal is converted into an 8-bit 1.544 MHz burst signal by the serial-parallel shift register 6, and converted into a digital signal by the serial-parallel shift register 6. This signal is converted into a data signal at a speed of 64 Kb/s by the parallel-serial shift register 7, and then sent to the transmission line from the data output terminal 9 via the interface 8. FIG. 7 is a waveform time chart showing the timing of the output data signal and clock.

[Problem to be solved by the invention]

By the way, if the PCM terminal device and the clock supply device are different, or if a phase difference occurs due to wiring, etc.
It is necessary to measure whether the timing of the data and the clock satisfy a predetermined relationship, but even if you try to easily measure this with a synchroscope, etc., the data signal at the start of the clock octet will not reach the 8th bit. It was inconvenient that it was not possible to determine whether it was the first bit or the first bit, and a special test pattern had to be given to decipher it.

This invention was made to solve the above problem.
It is an object of the present invention to provide a PCM terminal device that can easily know the relationship between a predetermined timing of a clock and a data signal focus.

[Means to solve the problem]

In order to achieve the above object, the present invention has a one-shot trigger that introduces a clock of a predetermined frequency that is applied from a clock supply device and drives a circuit that converts a PCM input into a data signal, and a differential trigger that differentiates the output of this one-shot/seven-shot trigger. The one-shot trigger is configured to have a designated bit selection function.

[Effect]

In this invention, a marker is inserted into a specific bit of a data signal by specifying the bit, so the bit number of the data signal at a predetermined timing of the clock can be easily identified.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, 10 is a 2π shift one-shot trigger with a designated bit selection function, and the bit is designated by a test bit/node selection switch 11-2.

Reference numeral 11-1 indicates a test switch 12 which is closed only during a test, an AND gate, 13 a differentiation circuit, and 14 a marker insertion circuit (in this example, an AND gate).

As mentioned above, the P input to the PCM signal input terminal 1
The CM signal is converted into an 8-bit 1.544MHz bust signal by the AND gate 5 using the channel designation clock.
It is converted into a digital signal by a serial-parallel shift register 6. This signal is replaced by a 64K b/s data signal in the parallel-serial shift register 7.

At this time, by using the test bit designation switch 11-2, for example,
When the first bit is specified and the test switch 11-1 is turned on, the output of the one-shot trigger 10 selected by the bit enters the differentiation circuit 13 through the AND gate 12, and the differential signal enters the AND gate 14. As shown in FIG. 3, a marker M is inserted into a designated bit (1st bit/node) of the 64 Kb/s data signal.

If this marker M is too large and the marker insertion data changes greatly from the original 64 Kb/s data, and there is a risk of a code error, the marker insertion circuit should be replaced with a circuit as shown in Figure 4. As a configuration, the amplitude of the marker M may be limited. In FIG. 4, 15 is a DC cut capacitor, 16 is a resistor 17 is a switch, and this switch 17 is turned ON by the output of the differentiating circuit 13. At this time,
The output level changes depending on the ratio between the output impedance of the shift register 7 and the resistor 16. For this reason, the marker M can have a small amplitude as shown in FIG. 6, and can be set to be above the error detection threshold level as shown in FIG. 7, resulting in a code error. There is no fear, and with this configuration, the marker M can be inserted not only during testing but also during normal times.

Note that if a marker is inserted in the same way not only in a 64 K b/s data signal but also in a frame synchronization signal and bit scale method signal bit in a 1.544 M b/s PCM signal, 1. 544
Even in the code sequence of the PCM signal, pig errors, omissions, etc. can be easily identified.

〔Effect of the invention〕

As described above, in this invention, a marker is inserted into a specified bit of a data signal, so it is possible to easily identify which bit the data is on a predetermined ramming of the clock.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform time chart showing the relationship between the data signal, marker, and clock in the above embodiment, and FIG. 3 is a main part of another embodiment of the invention. FIG. 4 is a waveform time chart showing the relationship between the data signal, marker and clock in the other embodiment described above, FIG. 5 is a partially enlarged view of FIG. 4, and FIG. 6 is a conventional PCM terminal equipment. FIG. 7 is a waveform time chart showing the relationship between the data signal and the clock in the conventional example. In the figure, 1-P CM signal input terminal, 2-Call channel designation clock terminal, 3.4-.-Clock input terminal, 7-
・-Parallel-serial shift register, 8・-Interface, 10...-One-shot trigger ii-+-
--Test switch, 11-2...-Test bit selection switch, 13 is a differentiation circuit, 14 is an AND gate serving as a marker insertion circuit, 15.--Capacitor, 1-inch. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] In a PCM terminal device, a one-shot trigger that introduces a clock of a predetermined frequency that is applied from a clock supply device and drives a circuit that converts a PCM input into a data signal, and a differentiation circuit that differentiates the output of this one-shot trigger;
A PCM terminal device comprising a circuit for inserting a marker into the data signal based on the output of the differentiating circuit, and wherein the one-shot trigger has a specified bit selection function.