JPH03218638A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to obtain impurity layers, which are good in evenness and are shallow, by a method wherein an impurity adsorption method is used for forming the source and drain regions of an LDD(Lightly Doped Drain) type or DDD(Double Doped Drain) type MISFET. CONSTITUTION:High-concentration and low-concentration impurity regions of an LDD structure are both formed using an impurity adsorption method. When boron compound gas 11 is introduced in the surface of an N-type silicon substrate 1, a boron adsorption layer 12 is formed. After that, when a heat treatment is performed, shallow P<-> source and drain regions 6 are formed. Then, when an insulating film is deposited from over this structure and it is removed by anisotropic etching, spacers 4 are formed along a gate electrode 3. After this, when a high-concentration boron layer is formed using the electrode 3 and the spacers 4 as masks, a P MISFET of an LDD structure having P<+> source and drain regions 7 and 8 is obtained. Thereby, impurity regions, which are shallow and are good in evenness, are obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to MISFET (Metal-1n) which is widely used in electronic equipment such as computers.
sulator-Sel1eOnduetOrFie
The present invention relates to a method for manufacturing a semiconductor device (LD-Ef'fect-Transistor).

[Summary of the invention]

This invention is based on LDD (Lightly Dope).
d Drain) structure or D D D (Double
MISFET with Doped Drain) structure
In the process of forming the source and drain regions, very shallow impurity regions are obtained by forming the impurity regions that will become the source and drain regions by an impurity adsorption method, resulting in a short signal propagation time and extremely fine impurity regions. This is a method of manufacturing a semiconductor device that allows a semiconductor device to be obtained.

[Conventional technology]

In the conventional LDDH 4 structure, P type M I S F E
Taking T as an example, as shown in FIG. 9, after forming a gate oxide film 102 and a gate electrode 103 on the surface of an N-type silicon substrate 101, boron 113, which is a P-type impurity, is ionized using the gate electrode 103 as a mask. After implanting near the surface of the N-type silicon substrate 101 to form a thin P'' type source region 105 and drain region 106, and further forming a spacer 104 along the sidewall of the gate electrode 103, the gate electrode 103 and the spacer A manufacturing method is known in which boron, which is a P-type impurity, is ion-implanted again using 104 as a mask to form a dense P+ type source region 107 and drain region 108, thereby producing a MISFET having an LDD structure. An advantage of this ion implantation method is that the amount of impurities introduced can be accurately controlled, or that impurities can be doped through an insulating film.

Furthermore, in the conventional DDD structure, taking a P-type MISFET as an example, as shown in FIG.
After forming 03, using the gate electrode 203 as a mask, boron 213, which is a P-type impurity, is ion-implanted into the vicinity of the surface of the N-type silicon substrate 201 to form a thin P-type source region 205 and drain region 206, and then to form a gate electrode 203. A known method is to ion-implant boron 215, which is a P-type impurity, using the electrode 203 as a mask to form a dense P-type source region 207 and drain region 208.

[Problem to be solved by the invention]

However, in the conventional semiconductor device manufacturing method described above, since the source and drain regions are formed by ion implantation, (1) impurity distribution or ion implantation results in a Gaussian distribution depending on the acceleration energy of ions during ion implantation. It spreads, making it impossible to form a shallow impurity region.

(2) The gate insulating film is damaged because charged ions are implanted.

(3) MISFE on the (100) plane of silicon crystal
When forming a T, a phenomenon called channeling is likely to occur during ion implantation, making it difficult to form a shallow impurity region necessary for manufacturing a fine MISFET.

(4) In order to prevent the above-mentioned channeling, it has been proposed to tilt the incident angle of ion implantation by about 7 degrees. However, when this method is used, a shadow effect causes asymmetry in the impurity distribution in the source and drain regions near the gate electrode, resulting in a disadvantage that the current characteristics of Pvl I S F E T differ depending on the orientation of the gate electrode.

(5) In order to form contacts between wiring electrodes and source and drain regions with as low a resistance as possible, it is necessary to increase the impurity concentration at the surface portions of the source and drain regions. It is difficult to intensively increase only the impurity concentration.

Due to the above-mentioned drawbacks, it has been difficult to manufacture fine semiconductor devices with uniform characteristics.

In order to solve the above-mentioned drawbacks, the present invention forms source and drain regions with a thin impurity concentration of the MI SFET that connects the LDD structure by an impurity adsorption method, and forms very shallow and highly uniform impurity regions. The purpose is to gain territory. Furthermore, another object of the present invention is to form extremely shallow and highly impurity-concentrated source and drain regions of a MI SFET having an LDD structure or a DDD structure using an impurity adsorption method.

[Means to solve the problem]

According to the present invention, after the first step of forming a gate insulating film on the surface of a semiconductor region of a first conductivity type and a gate electrode on this gate insulating film is performed, the gate electrode is separated two-dimensionally by the gate electrode. A second step is performed to expose the active surfaces of the pair of semiconductor regions. Next, a gas containing an impurity component of the second conductivity type is supplied to the active surface, and the impurity component element or at least a compound containing the impurity component element is adsorbed, and this impurity adsorption layer is used as a diffusion source to form the first conductivity type. A third step is performed in which an impurity is introduced into the semiconductor region of the gate electrode and a low concentration first impurity layer is formed below the surface of the pair of semiconductor regions separated by the gate electrode. Finally, a fourth step is performed in which a second impurity layer having a higher impurity concentration than the first impurity layer is formed adjacent to the first impurity layer, and a semiconductor device is manufactured.

Preferably, the fourth step is a step of introducing a second conductivity type impurity by ion implantation to form a second impurity layer. Alternatively, in the fourth step, a gas having an impurity component of the second conductivity type is supplied to adsorb the impurity component element or at least a compound containing the impurity component element, and the impurity is added to the first impurity layer using this impurity adsorption layer as a diffusion source. In this step, a highly concentrated second impurity layer is formed.

A step of forming a spacer on the side wall of the gate electrode may be added between the third step and the fourth step.

More preferably, in the third step, a gas having a semiconductor component and a gas having a second conductivity type impurity component are supplied to the active surface to form an adsorption layer containing the semiconductor component and the impurity component element; This is a step of introducing impurities into a semiconductor region of a first conductivity type using the layer as a diffusion source to form a first impurity layer with a low concentration. Alternatively, in the third step, an adsorption layer having at least one impurity adsorption layer consisting of an impurity layer having an impurity component of the second conductivity type and a semiconductor epitaxial layer is formed, and this adsorption layer is used as a diffusion source to conduct the first conductivity. This is a step of introducing impurities into the semiconductor region of the mold to form a low concentration first impurity layer.

According to another aspect of the present invention, after performing the first step of forming a gate insulating film on the surface of the semiconductor region of the first conductivity type and a gate electrode on the gate insulating film, A second step is performed in which impurities are introduced into the separated semiconductor regions by ion implantation to form a first impurity layer. Subsequently, a third step is performed to expose the active surface of the surface of the semiconductor region into which ions have been implanted. Finally, a gas containing an impurity component of the second conductivity type is supplied to the active surface to adsorb the impurity component element or at least a compound containing the impurity component element, and the first impurity is absorbed using this impurity adsorption layer as a diffusion source. By introducing impurities into the layer, a highly concentrated second
A fourth step of forming a source region and a drain region made of an impurity layer is performed to manufacture a semiconductor device.

A step of forming a spacer on the side wall of the gate electrode may be added between the third step and the fourth step.

In the fourth step, for example, a gas containing a semiconductor component and a gas containing an impurity component of the second conductivity type are supplied to the active surface to form an adsorption layer containing the semiconductor component and impurity component elements, and this adsorption layer is diffused. This is a step of introducing impurities into the first impurity layer as a source to form a highly concentrated second impurity layer. Alternatively, the fourth step is to form an adsorption layer having at least one impurity adsorption layer consisting of an impurity layer having an impurity component of the second conductivity type and a semiconductor epitaxial layer, and use this adsorption layer as a diffusion source to absorb the first impurity. This is a step of introducing impurities into the layer to form a highly concentrated second impurity layer.

[For production]

The impurity adsorption method described above utilizes the principle that when a gas containing an impurity element or an impurity compound gas is supplied to the surface of an activated semiconductor, the impurity element or a compound containing the impurity element is chemically adsorbed onto the semiconductor surface. Therefore, the amount of impurities adsorbed can be controlled by the temperature of the semiconductor substrate and the amount of gas containing the impurity element introduced. Further, since the impurity regions are formed by diffusion using the impurity adsorption layer formed on the semiconductor surface as a diffusion source, uniform and shallow source and drain regions can be easily obtained.

〔Example〕

(First Example) Below, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. FIG. 1 shows a first embodiment of the present invention in which an N-type silicon substrate 1 is used as a semiconductor substrate.
This is an example. Both the high concentration and low concentration impurity regions of the LDD structure are formed using an impurity adsorption method. First, as shown in FIG. 1(a), a gate oxide film 2 is formed on an N-type silicon substrate 1. In the manufacture of general integrated circuits, there are steps such as forming an element isolation region before this step, but the explanation thereof will be omitted here. Next, as shown in FIG. 1(b), a gate electrode 3 is formed, and the gate electrode 3 is
Using as a mask or the photoresist used to form gate electrode 3 as a mask, gate oxide film 2 is removed by etching to expose the surface of N-type silicon substrate 1. Next, as shown in FIG. 1(C), a boron compound gas 11 is introduced into the exposed surface of the N-type silicon substrate 1 to form a boron adsorption layer l2. After that, 7
When heat treatment is carried out at 00 DEG C. to 900 DEG C., a shallow P-type source region 5 and a P-type drain region 6 are formed as shown in FIG. 1(d). Next, an insulating film is deposited over this structure and removed by anisotropic etching, as shown in Figure 1 (e).
), spacers 4 are formed along the gate electrode 3. After that, a highly concentrated boron layer is formed using the gate electrode 3 and spacer 4 as a mask, as shown in FIG.
P-type MI SFE of LDD structure having double-type source region 7 and p-type drain region 8 as shown in ``).
You can make T. Although these source regions and drain regions can be formed using an ion implantation method, in this example, they are formed using the impurity adsorption method used when forming the P1 type source region and the P1 type drain region. are doing. Using this impurity absorption method makes it possible to form source and drain regions containing P-type impurities that are shallow and have excellent symmetry, rather than using ion implantation.

Hereinafter, the characteristics of the P-type impurity layer made by the impurity adsorption method will be explained using FIGS. 2 to 4. FIG. 2 shows a process flowchart in the step of forming a P-type impurity region. First, the degree of vacuum is lowered to several II Pa or less at 700°C, and then the semiconductor substrate is exposed to an atmosphere at about 800°C.

After stabilizing the atmosphere for several minutes, hydrogen is introduced at a pressure of about 10 mPa. This hydrogen causes about 30% of the silicon substrate to be formed on the exposed surface after the etching process that exposed the silicon substrate.
The natural oxide film below A is removed and the surface is cleaned. As a result, activated silicon atoms are exposed on the surface. Next, the temperature is lowered to a temperature for forming an adsorption layer, and a boron-containing compound gas such as diborane gas (B2H6) is introduced to form a boron adsorption layer on the exposed surface of the silicon substrate 1. This boron adsorption layer is mainly formed on the exposed surface of the silicon substrate and the gate electrode made of polysilicon or the like, and is not formed on an insulating film such as an oxide film. FIG. 3 is an example of the distribution of boron impurity concentration from the surface formed by the process flow of FIG. 2.

It can be seen that a shallow impurity region of 700 A or less can be easily formed at an extremely high surface impurity concentration. FIG. 4 shows the dependence of the peak boron loading on the diborane introduction time when the diborane introduction pressure is used as a parameter in the process shown in FIG. It has been shown that the impurity adsorption method can produce impurity regions from low to high concentrations with good controllability by changing the introduction pressure and introduction time of diborane.

However, if it is desired to form an impurity region with an even higher concentration, it is better to repeat the diborane introduction and annealing shown in FIG. 2 several times. Diborane gas, dichlorosilane (S iH 2 CD 2 ) gas containing a semiconductor component, and hydrogen gas may be introduced simultaneously to provide a continuous adsorption layer of boron and silicon. Furthermore, in the embodiments shown in FIGS. 1 and 2, an annealing step is performed immediately after the formation of the boron adsorption layer, but this annealing step may be performed at any time after the formation of the boron adsorption layer. Needless to say. Therefore, the annealing for forming the P1 type source and drain regions shown in FIG. 1(d) can also be used as the annealing for forming the P+ source and drain regions in FIG. 1m. Further, as the annealing method, it is preferable to use lamp annealing or beam annealing.

As a first embodiment of the present invention, a P-type MISFET in which boron is introduced as an impurity has been described. In the case of boron, since its diffusion coefficient is larger than that of N-type arsenic and phosphorus, the present invention is particularly advantageous. However, it goes without saying that the present invention can be applied to an N-type MISFET using an N-type impurity such as antimony in the source and drain regions. Furthermore, the method for manufacturing a semiconductor device of the present invention is applicable not only to the formation of MISFET on a semiconductor substrate but also to the formation of MISFET in a well region provided near the surface of a semiconductor substrate, and the formation of MISFET on a semiconductor substrate formed on an insulating film. Needless to say, this method is also effective when forming an MISFET on a film. Alternatively, an impurity region may be formed by forming an adsorption layer having at least one impurity adsorption layer composed of an impurity layer and a semiconductor epitaxial layer, and performing solid phase diffusion using this adsorption layer as a diffusion source.

For example, a boron adsorption layer is formed on the surface of an N-type silicon substrate by introducing diborane gas at a pressure of approximately IxlO'Pa for 100 seconds while maintaining the substrate surface temperature at 825°C. Next, while maintaining the substrate surface temperature at 700° C. to 900° C., a silicon-containing compound gas such as SiH2C12 or SiH4 is introduced to form a silicon epitaxial layer on the boron adsorption layer. Note that if a chlorine gas such as dichlorosilane or a mixture of S iH 4 and HC1 is used, a silicon epitaxial layer can be selectively formed only on silicon. While maintaining the silicon substrate surface temperature at 825°C, dichlorosilane gas (S IH 2 C
I 2 ) was introduced for 13 minutes at a pressure of 1.3×1O'Pa to form a silicon epitaxial layer with a thickness of about 50 nm. Note that the thickness of the silicon epitaxial layer must be such that it does not electrically short-circuit with the silicon epitaxial layer or the gate electrode, and is preferably thinner than at least the gate oxide film. When the boron adsorption layer and the silicon epitaxial layer are stacked as described above, boron is easily incorporated into the epitaxial layer and activated.

(Second Embodiment) FIGS. 5(a) to 5(g) show a second embodiment of the present invention in which an N-type silicon base material is used as the semiconductor region. In the LDD structure, a low concentration impurity region is formed by impurity adsorption, and a high concentration impurity region is formed by ion implantation. According to this method, it is possible to form the low-concentration regions of the source and drain to be very shallow and to minimize the extent to which they extend directly under the gate electrode. First, as shown in FIG. 5(a), a gate oxide film 22 is formed on an N-type silicon substrate 2l. Next, a gate electrode 23 is formed on the gate oxide film 22 as shown in FIG. 5(b).

Next, as shown in FIG. 5C, the gate oxide film 22 is removed using the gate electrode 23 as a mask to expose the surface portion of the N-type silicon substrate 2l that will become the surface of the source formation region and the drain formation region. . Next, as shown in FIG. 5(d), a boron adsorption layer is formed on the surface of the exposed N-type silicon substrate 2l, and heat treatment is performed at 700°C to 950°C, as shown in FIG. 5(e). Source and drain low concentration regions 25. Form 24. Next, an S 10 2 film 26 is provided around the gate electrode 23 as shown in FIG. 5(f). Next, using the gate electrode 23 around which the SiO 2 film 26 is provided as a mask, ions are implanted into the high concentration regions 28. of the source and drain. 27 as shown in FIG. 5(g). :! MOS (Met
Al-Oxide-Ses+iconductor) transistors can be made.

FIG. 6 shows a process flow in the step of forming impurity doped layers to form low concentration regions of the source and drain. First, at 850℃ with a degree of vacuum of 1 x lO'Pa or less.
The semiconductor substrate is exposed to a moderate atmosphere.

Next, after several minutes of atmosphere stabilization, hydrogen is introduced.

This hydrogen moves less than about 30 natural oxide films formed on the silicon base 1i21, thereby cleaning the surface. As a result, activated silicon atoms are exposed on the surface. Next, a boron-containing compound such as diborane gas (B2H6) is introduced at about I x 10'Pa to form a boron adsorption layer on the surface of the silicon substrate 2l. Next, by diffusing and activating boron into the substrate through heat treatment, low concentration regions of the source and drain can be formed.

According to the method for manufacturing an LDD structure MOS transistor according to the second embodiment of the present invention, the low concentration regions of the source and drain are shallow from the surface of the silicon substrate 2l and do not go under the gate electrode. Compared to ion implantation with the same gate length, the effective distance between the source and drain does not become narrower.

That is, a fine LDD structure MOS transistor can be manufactured.

As a second embodiment of the present invention, the case of a P-channel MOS transistor into which boron is introduced as an impurity has been described. In the case of boron, the diffusion coefficient is larger than that of N-type arsenic, so the present invention has a particularly large advantage. However, it goes without saying that the present invention can be applied to an N-channel MOS transistor in which source and drain regions are formed with N-type impurities such as antimony. Further, the semiconductor substrate may be not only silicon but also germanium.

Further, the gate insulating film does not need to be limited to a gate oxide film.

(Third Example) Next, a third example of the method for manufacturing a semiconductor device of the present invention will be described based on FIG. 7. In this embodiment, in the LDD structure, the source region and drain region of the MISFET with high impurity concentration are formed by an impurity adsorption method, and the purpose is to obtain extremely high concentration and shallow impurity regions. The impurity adsorption method described above utilizes the principle that when a gas or compound gas containing an impurity element is supplied to the surface of an activated semiconductor, the impurity element or a compound containing the impurity element is chemically adsorbed onto the semiconductor surface.

Therefore, the amount of impurities adsorbed can be controlled by the temperature of the semiconductor substrate and the amount of gas containing the impurity element introduced. or,
Since impurity regions are formed by diffusion using an impurity adsorption layer formed on the semiconductor surface as a diffusion source, source and drain regions with high impurity concentration can be easily obtained very close to the semiconductor surface.

First, as shown in FIG. 7(a), a gate oxide film 32 is formed on an N-type silicon substrate 31. In the manufacture of general integrated circuits, there are steps such as forming an element isolation region before this step, but the explanation thereof will be omitted here. Next, a gate electrode 33 is formed on the gate oxide film 32 as shown in FIG. 7(b). Next, as shown in FIG. 7(C), boron ions are implanted using the gate electrode 33 as a mask or the photoresist used to form the gate 74 and the pole 33 as a mask. A boron implantation layer 44 is then formed. Next, an insulating film is deposited over this structure and removed by anisotropic etching to form spacers 34 along the side walls of the gate electrode 33, as shown in FIG. 7(d). At this time, a low concentration source region 35 and drain region 36 are formed. The process up to this point is exactly the same as the manufacturing method of a conventional MISFET having an LDD structure. Next, as shown in FIG. 7(e), the exposed surface of the N-type silicon substrate 3l is heated with a boron compound gas 41.
When exposed to the inside, boron adsorbed Nt42 is formed. The details of this process are the same as in FIG.

After that, heat treatment at 700℃ to 900℃ results in the seventh
As shown in the figure ('), the P-type source region 37 and drain region 38 are shallow and have a high boron concentration at the surface.
is formed.

(Fourth Example) Finally, a fourth example of the method for manufacturing a semiconductor device of the present invention will be described based on FIG. 8. The purpose of this embodiment is to form a source region and a drain region with a high impurity concentration of a MISFET by an impurity adsorption method in a DDD structure, and to obtain a very high concentration and shallow impurity region. First, as shown in FIG. 8(a), an N-type silicon substrate 5
A gate oxide film 52 is formed on 1. In the manufacture of general integrated circuits, there are steps such as forming an element isolation region before this step, but the explanation thereof will be omitted here.

Next, a gate electrode 53 is formed on the gate oxide film 52 as shown in FIG.
Form as in b). Next, as shown in FIG. 8(C), using the gate electrode 53 as a mask or using the photoresist used to form the gate electrode 53 as a mask, boron 63 is ion-implanted into the vicinity of the surface of the N-type silicon substrate. A boron implant layer 64 is formed.

Thereafter, a heat treatment is performed to activate and diffuse the boron implanted layer 64, thereby forming a P-type source region 55 and drain region 56 as shown in FIG. 8(d).

The process up to this point is the same as the manufacturing method of a conventional MI SFET having a DDD structure. Next, as shown in FIG. 8(e), the insulating film remaining on the source region 55 and drain region 5B is removed by etching to expose the silicon substrate surface.
When this is exposed to boron compound gas 61, a boron adsorption layer is formed on the exposed silicon MIi2 surface. The details of this process are similar to those shown in FIG. After that, heat treatment at 700°C to 900°C is shown in Fig. 8 (f'
), a shallow P+ type source region 57 and a drain region 58 having a high boron concentration near the surface are formed.

〔Effect of the invention〕

As explained above, the present invention uses an impurity adsorption method to form a source region and a drain region of an LDD type or DDD type MISFET, thereby obtaining a shallow impurity layer with good uniformity. I can do it. Therefore,
According to the method of manufacturing a semiconductor device of the present invention, there is an effect that a high-speed and fine semiconductor device can be manufactured.

[Brief explanation of drawings]

1(a) to (r) are process cross-sectional views showing a first embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a process sectional view of an impurity adsorption step in the first embodiment. 3 is a flow chart showing the impurity concentration profile from the temporary surface of the semiconductor substrate formed according to the process flow shown in FIG. 2, and FIG. 4 shows the profile of the B, H6 introduction pressure in the process flow shown in FIG. FIG. 2 is a characteristic diagram of the B 2 He introduction time dependence of the boron peak concentration when is taken as a parameter. 5(a) to 5(g) are step-by-step cross-sectional views showing a second embodiment of the method for manufacturing an LDD structure MISFET of the present invention, and FIG. 6 is a diagram illustrating the formation of an impurity doped layer in the second embodiment. It is a process flow diagram of a process. FIGS. 7(a) to 7(') are process cross-sectional views showing a third embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS. 8(a) to 8(') are step-by-step cross-sectional views showing a fourth embodiment of the method for manufacturing a semiconductor device of the present invention. Figure 9(a)-('
) is a step-by-step cross-sectional view showing a conventional method for manufacturing a semiconductor device, and FIGS. 10(a) to (f) are step-by-step cross-sectional views showing another conventional method for manufacturing a semiconductor device. 1...N-type silicon substrate 2...Gate oxide film 3.
...Gate electrode 4...Spacer 5...P
type source region 6...P type drain region 7...P
+ type source region 8...P+ type drain region l1...
・Boron compound gas (B2 He) l2...Boron adsorption layer Applicant Seiko Electronics Co., Ltd. Agent

Claims (12)

[Claims] (1) A gate insulating film on the surface of the first conductivity type semiconductor region,
a first step of forming a gate electrode on the gate insulating film; a second step of exposing an active surface of the surface of the pair of semiconductor regions separated in a plane by the gate electrode; A gas containing an impurity component of the second conductivity type is supplied, the impurity component element or at least a compound containing the impurity component element is adsorbed, and the impurity is introduced into the semiconductor region of the first conductivity type using this impurity adsorption layer as a diffusion source. a third step of forming a first impurity layer with a higher concentration under the surface of a pair of semiconductor regions separated by a gate electrode; and a second step of forming a second impurity layer with a higher concentration than the first impurity layer. A method for manufacturing a semiconductor device comprising a fourth step of forming the impurity layer adjacent to the impurity layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the fourth step is a step of introducing a second conductivity type impurity by ion implantation to form a second impurity layer. (3) The fourth step is to supply a gas having an impurity component of the second conductivity type to adsorb the impurity component element or at least a compound containing the impurity component element, and use this impurity adsorption layer as a diffusion source to form the first impurity layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step includes introducing an impurity into the semiconductor layer to form a highly concentrated second impurity layer. (4) The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a spacer on the side wall of the gate electrode between the third step and the fourth step. (5) The third step is to supply a gas containing a semiconductor component and a gas containing an impurity component of the second conductivity type to the active surface to form an adsorption layer containing the semiconductor component and impurity component elements, and this adsorption layer 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step is to introduce an impurity into the semiconductor region of the first conductivity type using the impurity as a diffusion source to form a low concentration first impurity layer. (6) The third step is to form an adsorption layer having at least one impurity adsorption layer consisting of an impurity layer having an impurity component of the second conductivity type and a semiconductor epitaxial layer, and use this adsorption layer as a diffusion source for the first impurity adsorption layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step includes introducing an impurity into a conductive type semiconductor region to form a low concentration first impurity layer. (7) a gate insulating film on the surface of the first conductivity type semiconductor region;
and a first step of forming a gate electrode on this gate insulating film; and a second step of introducing impurities by ion implantation into the semiconductor region separated in a plane by the gate electrode to form a first impurity layer. , a third step of exposing the active surface of the surface of the ion-implanted semiconductor region, and supplying a gas having a second conductivity type impurity component to the active surface to form an impurity component element or a compound containing at least an impurity component element. and a fourth step of introducing an impurity into the first impurity layer using this impurity adsorption layer as a diffusion source to form a source region and a drain region consisting of a highly concentrated second impurity layer. Production method. (8) The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming a spacer on the side wall of the gate electrode between the third step and the fourth step. (9) The fourth step is to supply a gas containing a semiconductor component and a gas containing an impurity component of the second conductivity type to the active surface to form an adsorption layer containing the semiconductor component and impurity component elements, and this adsorption layer 8. The method of manufacturing a semiconductor device according to claim 7, wherein the step is to introduce an impurity into the first impurity layer using as a diffusion source to form a highly concentrated second impurity layer. (10) The fourth step is to form an adsorption layer having at least one impurity adsorption layer consisting of an impurity layer having an impurity component of the second conductivity type and a semiconductor epitaxial layer, and use this adsorption layer as a diffusion source to form the first impurity adsorption layer. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the step includes introducing an impurity into the impurity layer of the second impurity layer to form a highly concentrated second impurity layer. (11) The method of manufacturing a semiconductor device according to claim 7, wherein the fourth step is a step of forming an LDD structure. (12) The method for manufacturing a semiconductor device according to claim 7, wherein the fourth step is a step of forming a DDD structure.