JPH03218008A - Growing method of compound semiconductor - Google Patents

Growing method of compound semiconductor

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Publication number
JPH03218008A
JPH03218008A JP1312590A JP1312590A JPH03218008A JP H03218008 A JPH03218008 A JP H03218008A JP 1312590 A JP1312590 A JP 1312590A JP 1312590 A JP1312590 A JP 1312590A JP H03218008 A JPH03218008 A JP H03218008A
Authority
JP
Japan
Prior art keywords
compound semiconductor
layer
doping
impurity
undoped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1312590A
Other languages
Japanese (ja)
Other versions
JP3057503B2 (en
Inventor
Hideto Ishikawa
石川 秀人
Mikio Kamata
幹夫 鎌田
Hiromasa Shibata
柴田 浩正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Filing date
Publication date
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Priority to JP2013125A priority Critical patent/JP3057503B2/en
Publication of JPH03218008A publication Critical patent/JPH03218008A/en
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Publication of JP3057503B2 publication Critical patent/JP3057503B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To accurately control impurities doping by a method wherein undoped compound is vapor-grown, impurity gas is supplied in the state that growth is interrupted, and doping process is repeated until the surface density of carrier is nearly saturated. CONSTITUTION:Undoped compound is vapor-grown on a substrate 1, and an undoped compound semiconductor layer 12A having a specified thickness is formed. Next, in the state that the growth is interrupted, impurity material gas is supplied to the layer 12A, and doping is performed until the carrier surface density is nearly saturated, thereby forming an impurities doped layer 12B. By repeating this process several times, a compound semiconductor layer 12 is formed. Althorough, in this method, the impurity concentrations of all of the compound semiconductor layers take discrete values, each of the values is uniform, and uniform concentration can be realized all over the region of a wafer independently of wafer position. Hence impurities doping can be accurately controlled, and a device having specified characteristics can be surely obtained with superior reproducibility.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えばA 1 1nAs系等の化合物半導体
の成長方法、特に例えば高電子移動度トランジスタHE
MT等におけるように、不純物ドーピングがなされた化
合物半導体層と不純物ドーピングがなされないいわゆる
アンドープの化合物半導体層とを積層成長する場合にお
いて、その不純物ドーピング層の成長に用いて好適な化
合物半導体の成長方法に係わる。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for growing compound semiconductors such as A 1 1nAs-based compound semiconductors, and in particular to methods for growing compound semiconductors such as high electron mobility transistors HE
A compound semiconductor growth method suitable for use in growing an impurity-doped layer when a compound semiconductor layer doped with impurities and a so-called undoped compound semiconductor layer that is not doped with impurities are layered and grown as in MT etc. related to.

〔発明の概要〕[Summary of the invention]

本発明は、化合物半導体の成長方法に係わり、アンドー
プ化合物半導体層を気相成長させる工程と、この気相成
長を停止させた状態で不純物原料ガスを供給してキャリ
アの面密度がほぼ飽和する量までドーピングする工程と
をとって不純物ドーピングの制御を正確にかつ選択的ド
ーピングの制御を正確に行うことができるようにする.
〔従来の技術〕 化合物半導体例えばA I TnAs系化合物半導体層
の結晶成長方法としては、主として分子線エピタキシ(
MBE)法、有機金属気相成長(MOCVD)法等で行
われる方法の開発研究が目覚ましい。
The present invention relates to a method for growing a compound semiconductor, including a step of growing an undoped compound semiconductor layer in a vapor phase, and supplying an amount of impurity raw material gas with the vapor phase growth stopped so that the areal density of carriers is almost saturated. In order to accurately control impurity doping and selective doping, it is possible to precisely control impurity doping and selective doping.
[Prior Art] Molecular beam epitaxy (
There has been remarkable research and development into methods such as MBE (MBE) and metal organic chemical vapor deposition (MOCVD).

この場合n型のA IlInAsを得るためにはMOC
VD法を例にとると、n型不純物としては主にSiが用
いられ、このSiのドーピングの原料ガスとしてはSi
J*が主として用いられている.このSiがA II 
InAsにのみ選択ドーブされたn−A I InAs
は、これとGalnAsの積層構造として、ヘテロ界面
電界効果トランジスタいわゆるHIFETに応用されて
いる。この選沢ドープn−A I InAsは、良く知
られているA I GaAs系における高電子移動度電
界効果トランジスタいわゆるHEMTのn−A I G
aAsと同様に電子供給層としての役割をはたしている
In this case, to obtain n-type A IlInAs, MOC
Taking the VD method as an example, Si is mainly used as the n-type impurity, and Si is used as the raw material gas for doping this Si.
J* is mainly used. This Si is A II
InAs selectively doped n-A I InAs
A laminated structure of this and GalnAs is applied to a heterointerface field effect transistor, so-called HIFET. This selectively doped n-A I InAs is used in the n-A I G of the well-known high electron mobility field effect transistor in the A I GaAs system, so-called HEMT.
Like aAs, it plays a role as an electron supply layer.

この種のHEMTへの適用における一例の断面図を、第
5図に示す。この場合例えばInPよりなる化合物半導
体基体(1)上にアンドーブのGalnAsよりなるハ
リア層(2)と、さらにこれの上に電子供給層(3)と
してn− A2■nAsが順次例えばMOCVDによっ
て形成され、n− Aj! InAs/GalnAs構
造の、GalnAs層すなわちバリア層(2)側におい
て高電子移動度の2次元電子ガスチャンネル(4)が形
成される。
A cross-sectional view of an example of application to this type of HEMT is shown in FIG. In this case, a halia layer (2) made of undoped GalnAs is formed on a compound semiconductor substrate (1) made of, for example, InP, and n-A2nAs is formed on this as an electron supply layer (3) in sequence by, for example, MOCVD. ,n-Aj! A two-dimensional electron gas channel (4) with high electron mobility is formed on the side of the GalnAs layer, that is, the barrier layer (2) of the InAs/GalnAs structure.

(5)はゲート電極で、電子供給層(3)に対してショ
ットキ接合を形成し得るンヨノトキ金属によって形成さ
れる。(6)及び(7)はそれぞれソース及びドレイン
各電極を示す.このような電子供給層(3)としてのn
− A I InAs層を例えばMOCVD法によって
成長させる場合、まずスペーサ層としてアンドーブのA
 1 1nAsを気相成長させて後、Al,In,As
の原料ガスの供給と共にn型不純物の例えばSiを含む
原料ガスSiJiを供給してn− A I InAs層
を成長させるという方法がとられる.この場合、アンド
ーブのA I InAsがn− A I InAs層に
移り変わる時点で種々の要因によってSiの供給がお《
れ実質的にアンドープAlInAs層の厚さが大となり
設計値通りの不純物ドーピングプロファイルが得られな
いことになる。またドーピング分布の急峻性も良好でな
い。更にまた実際上各種半導体装置を得る場合、1枚の
ウェファ上に多数の例えばHEMTを同時に配列形成す
るという方法がとられる.ところがこの共通のウェファ
上において均一なキャリア濃度分布が得がたい.これは
、MOCVD,MBHにおけるその成長作業がなされる
反応器の形状、キャリアの流速、ウェファ支持体すなわ
ちサセプタの位置構造等の要因によるものであって、こ
のキャリア濃度の不均一化は得られる半導体装置、例え
ばHEMTにおけるしきい値電圧vthの変動に直接関
係するなど重要な問題である.またキャリア濃度の最大
の値に関しても、例えばMOCVD法においては、5 
〜6 XIO−”cm−’程度で飽和する傾向にあるこ
とから、これより高濃度なキャリア濃度は望みがたい. 〔発明が解決しようとする課題〕 本発明は、上述したように例えば^It InAs化合
物半導体に不純物をドーピングするに当って、その実質
的濃度を充分大にまた宅、峻な分布に良好な制御性をも
って形成することができるようにした化合物半導体の成
長方法を提供する. 〔課題を解決するための手段〕 本発明は、アンドープ化合物半導体層を気相成長させる
工程と、この気相成長を停止させた状態でこのアンドー
プ化合物半導体層自体に不純物原料ガスを供給してキャ
リアの面密度がほぼ飽和する量までドーピングする工程
とをとって目的とする化合物半導体の気相成長を行う. 〔作 用〕 上述したように本発明においては、アンドープ化合物半
導体層を気相成長させてこの気相成長を停止した状態で
、これに対して不純物原料ガスを飽和する量まで供給す
るのでその不純物ドーピング量すなわちキャリア濃度は
、この飽和量によって規制される所定の量に規定される
Reference numeral (5) denotes a gate electrode, which is made of a metal that can form a Schottky junction with the electron supply layer (3). (6) and (7) indicate the source and drain electrodes, respectively. n as such an electron supply layer (3)
- When growing an A I InAs layer by MOCVD, for example, an undoped A is first grown as a spacer layer.
1 After vapor phase growth of 1nAs, Al, In, As
A method is used in which a source gas SiJi containing n-type impurities such as Si is supplied together with the source gas SiJi to grow an n-AI InAs layer. In this case, the supply of Si is limited due to various factors at the time when the undoped AI InAs changes to the n-AI InAs layer.
This substantially increases the thickness of the undoped AlInAs layer, making it impossible to obtain the impurity doping profile as designed. Furthermore, the steepness of the doping distribution is also not good. Furthermore, in order to actually obtain various semiconductor devices, a method is used in which a large number of HEMTs, for example, are simultaneously formed in an array on a single wafer. However, it is difficult to obtain a uniform carrier concentration distribution on this common wafer. This is due to factors such as the shape of the reactor in which the growth process is performed in MOCVD and MBH, the flow rate of carriers, and the positional structure of the wafer support, that is, the susceptor. This is an important problem as it is directly related to fluctuations in threshold voltage vth in devices such as HEMTs. Also, regarding the maximum value of carrier concentration, for example, in MOCVD method, 5
Since the carrier concentration tends to be saturated at about ~6 Provided is a method for growing an InAs compound semiconductor, which allows doping of impurities to a sufficiently large and steeply distributed impurity concentration with good controllability. Means for Solving the Problems] The present invention includes a step of growing an undoped compound semiconductor layer in a vapor phase, and supplying an impurity raw material gas to the undoped compound semiconductor layer itself while the vapor growth is stopped to remove carriers. The target compound semiconductor is grown in vapor phase by doping the layer to an amount that substantially saturates the areal density. [Function] As described above, in the present invention, an undoped compound semiconductor layer is grown in vapor phase. With this vapor phase growth stopped, the impurity raw material gas is supplied in an amount that saturates it, so that the impurity doping amount, that is, the carrier concentration is regulated to a predetermined amount regulated by this saturation amount.

したがって気相成長による化合物半導体層中のキャリア
濃度を高める場合、上述したアンドーブ化合物半導体層
の気相成長と、これを停止した状態での不純物原料ガス
の供給による不純物のドーピングを飽和する量をもって
ドーピングする工程とを所要回数、例えばn回数繰返え
し行えば、ドーピングの飽和量のn倍の不純物ドーピン
グが全体としての量すなわち総量の濃度として得ること
ができるので、気相成長と同時に不純物のドーピングを
行う場合に比してその飽和量の整数倍の濃度という高い
濃度がいわゆるとびとびの値の制限された濃度ではある
ものの、このとびとびの値の濃度において正確な濃度に
かつ飽和濃度以上すなわちその整数倍の濃度の不純物ド
ーピングを行うことができ、さらにその界面における濃
度は急峻な分布を有するように形成することができる。
Therefore, when increasing the carrier concentration in a compound semiconductor layer by vapor phase growth, doping is carried out in an amount that saturates the above-mentioned vapor phase growth of the undoped compound semiconductor layer and the impurity doping by supplying the impurity source gas with this stopped. If this step is repeated the required number of times, for example, n times, it is possible to obtain impurity doping that is n times the saturation amount of doping as a total amount, that is, as a total concentration. Compared to the case of doping, the high concentration of an integer multiple of the saturation amount is a so-called limited concentration with discrete values, but it is possible to achieve an accurate concentration at the discrete values and to reach a concentration higher than the saturation concentration, that is, the concentration Impurity doping can be performed at an integral multiple of the concentration, and the concentration at the interface can be formed to have a steep distribution.

〔実施例〕〔Example〕

第1図を参照して本発明による化合物半導体の成長方法
を、n−Aj21nAs化合物半導体の成長に適用する
場合をMOCVDによって成長させる場合の一例を説明
する。この場合まず第1図Aに示すように、例えば単結
晶の半絶縁性1nP基体(1)例えばウェファをMOC
VDのなされる反応器内の所定位置に配置し、成長温度
すなわち基体温度を640゜Cとした状態で反応器内に
A I InAs成長原料ガスすなわち例えばトリメチ
ルアルミニウム(TMA)、トリメチルインジウム(T
M I ) 、アルシン(AsH2 )を供給してTn
P基体(1)、例えばウェファ上にA I InAsよ
りなるアンドーブ化合物半導体(12八)約1500人
成長させる.その後、基体温度を640゜Cに保持した
まま、■属原料ガスのTMA及びTMrの供給を停止し
て、すなわちA I InAsの成長を停止させた状態
で、不純物ドーピングすなわち例えばn型の不純物Si
の原料ガスSiJ6を反応器中に供給してアンドープ化
合物半導体層(12A)の表面にそのドーピングが飽和
する量の濃度をもって不純物ドーピングを行って第2図
Bに模式的に示す不純物ドーピング層(12B)を形成
する。
An example of the case where the method for growing a compound semiconductor according to the present invention is applied to the growth of an n-Aj21nAs compound semiconductor by MOCVD will be described with reference to FIG. In this case, first, as shown in FIG. 1A, a single crystal semi-insulating 1nP substrate (1), for example a wafer, is
It is placed at a predetermined position in the reactor where VD is performed, and with the growth temperature, that is, the substrate temperature, set at 640°C, A I InAs growth source gas, such as trimethylaluminum (TMA), trimethylindium (T
M I ), Tn by supplying arsine (AsH2)
Approximately 1,500 undoped compound semiconductors (128) made of AI InAs are grown on a P substrate (1), for example, a wafer. Thereafter, while maintaining the substrate temperature at 640°C, the supply of the group material gases TMA and TMr is stopped, that is, the growth of AI InAs is stopped, and impurity doping, for example, n-type impurity Si
The raw material gas SiJ6 is supplied into the reactor, and the surface of the undoped compound semiconductor layer (12A) is doped with impurities at a concentration that saturates the doping. ) to form.

さらに第1図Aで説明したと同様に再び不純物原料ガス
を停止して第1図Cに示すようにアンドープ化合物半導
体層(12A)を■−V属原料ガスの例えばTMA.T
MI及びアルシンを供給して例えばA I InAs層
によるアンドープ化合物半導体層(12A)を再び気相
成長する。
Furthermore, the impurity source gas is stopped again in the same manner as explained with reference to FIG. 1A, and as shown in FIG. T
MI and arsine are supplied to form an undoped compound semiconductor layer (12A), for example, an A I InAs layer, by vapor phase growth again.

さらに次に第2図Dに示すように■属原料ガスの供給を
停止してA I InAsの気相成長を停止した状態で
、不純物原料ガスSitHbを供給してそのドープ量が
飽和するまで不純物ドーピングを行って不純物ドーピン
グ層(12B)を表面に形成する。このようにしていわ
ゆるプレナードーピング層(12B)を例えば2層形成
する。そしてさらにこれの上に?様に不純物原料ガスの
81■H6の供給を停止してアンドーブのA 1 [n
As層(12A)を成長させる。
Further, as shown in FIG. 2D, while the supply of the group III source gas is stopped and the vapor phase growth of AI InAs is stopped, the impurity source gas SitHb is supplied and the impurity is added until the doping amount is saturated. Doping is performed to form an impurity doped layer (12B) on the surface. In this way, for example, two so-called planar doping layers (12B) are formed. And on top of this? Similarly, the supply of impurity raw material gas 81■H6 was stopped and Andove's A 1 [n
An As layer (12A) is grown.

今このようにして得た試料について、その化合物半導体
層(12)におけるキャリアの面密度Nsを不純物原料
ガスS1■H6の供給流量(供給流量比SCCMX供給
時間)を変えてホール測定によって得られた結果を第2
図に示す。これより明らかなようにsi2}1.ガスの
供給量をある値以上に設定すればその面密度が飽和して
これが一定になることがわかる。したがって面密度が飽
和を示すSiJ6のガス供給量をもってプレナー不純物
ドーピング層の形成を行えば各層(12B)についてそ
れぞれ同一の不純物濃度すなわちキャリア濃度が得られ
ることになる。したがってこのようにして得た化合物半
導体層(l2)の全体のキャリア濃度はこの層(12E
)の層数の和に相当する所定の値となる。
For the sample thus obtained, the areal density Ns of carriers in the compound semiconductor layer (12) was obtained by Hall measurement by varying the supply flow rate (supply flow rate ratio SCCMX supply time) of impurity source gas S1H6. Second result
As shown in the figure. As is clear from this, si2}1. It can be seen that if the gas supply amount is set above a certain value, the areal density becomes saturated and becomes constant. Therefore, if the planar impurity doped layer is formed with the SiJ6 gas supply amount at which the areal density is saturated, the same impurity concentration, that is, the carrier concentration will be obtained for each layer (12B). Therefore, the overall carrier concentration of the compound semiconductor layer (12) obtained in this way is
) is a predetermined value corresponding to the sum of the number of layers.

一方、しきい値電圧vthは、 2  ε5 ・ ε。On the other hand, the threshold voltage vth is 2 ε5 ・ ε.

で表わされる。ここにψ9はショノトキハリアの高さ、
ΔECは伝導帯不連続部のポテンシャル差、dは電流供
給層の厚さである。そして、結晶成長の面から問題にな
るのは、キャリア濃度とハリア層の厚さであるが、厚さ
については、ウェファ(基体(l))上で充分均一であ
るとするとvthの分布はNdの分布が反映しているも
のと考えることができる。今上述した2層のブレナー不
純物ドープ層の形成によって得た化合物半導体層(12
)を第5図で説明したHEMTにおける電子供給層(3
)として形成した試料についてみる。すなわちこの場合
第5図に示すように例えば基体(1)としてInPサブ
ストレイトを用い、これの上にMOCVDによってアン
ドーブのGalnAsのハリア層(2)を形成しこれの
上に電子供給層(3)として第1図で説明した化合物半
導体層(12)すなわちアンドープ化合物半導体層とそ
の成長を停止した状態でこれに対するプレナー不純物ド
ーピングを行う繰り返し作業によって2層のブレナー不
純物ドーピング層(12B)を形成してHEMTを構成
した。この共通の基体(1)すなわちウエファ上の各位
置にすなわちその中心からの距離が異なる点で得たHE
MTについてそれぞれその中心からの距離に対してそれ
ぞれそのしきい値電圧vthを測定した結果を第3図に
ブロン卜して示す。
It is expressed as Here, ψ9 is the height of Shonotokiharia,
ΔEC is the potential difference at the conduction band discontinuity, and d is the thickness of the current supply layer. In terms of crystal growth, the carrier concentration and the thickness of the Harrier layer are issues, but if the thickness is sufficiently uniform on the wafer (substrate (l)), the distribution of vth is Nd This can be considered to reflect the distribution of The compound semiconductor layer (12
) is the electron supply layer (3) in the HEMT explained in FIG.
). That is, in this case, as shown in FIG. 5, for example, an InP substrate is used as the substrate (1), an undoped GalnAs halia layer (2) is formed on this by MOCVD, and an electron supply layer (3) is formed on this. A two-layer Brenner impurity doped layer (12B) is formed by repeatedly doping the compound semiconductor layer (12), that is, the undoped compound semiconductor layer explained in FIG. Configured HEMT. HE obtained at each position on this common substrate (1), i.e., the wafer, i.e., at different distances from its center.
FIG. 3 shows the results of measuring the threshold voltage vth of each MT with respect to its distance from its center.

これによればそのウェファの中心からウエファの周辺こ
の例においては半径25rmのウエファの各位置におい
てほぼ一様なしきい値電圧vthを示すことが分かる。
According to this, it can be seen that a substantially uniform threshold voltage vth is exhibited at each position on the wafer with a radius of 25 rm from the center of the wafer to the periphery of the wafer in this example.

つまりキャリア濃度が一様であることがわかる。In other words, it can be seen that the carrier concentration is uniform.

これに比し、第4図においては、第5図で説明したと同
様のHEMT構造のFETにおいてその電子供給層(3
)として同様にハリア層(2)としてアンドープのGa
lnAsを形成しこれの上にアンドープのA I In
Asを形成してこれの上に通常のようにnA I In
Asをその気相成長と同時に不純物ドーピングを行って
電子供給層(3)を構成した場合の同様のウェファの各
位置におけるHEMTのvthを測定した結果を示した
ものである。これによればウェファ上の位置によってv
thが変動するすなわち周辺に向かってvthが低下す
ること、すなわちキャリア濃度が増大していることがわ
かる。
In contrast, in FIG. 4, the electron supply layer (3
) and undoped Ga as the Haria layer (2).
lnAs is formed and undoped A I In is formed on this.
As is formed and nA I In is formed on this as usual.
This figure shows the results of measuring vth of HEMT at each position of a similar wafer in which the electron supply layer (3) was formed by doping As with impurities simultaneously with its vapor phase growth. According to this, v depends on the position on the wafer.
It can be seen that th fluctuates, that is, vth decreases toward the periphery, that is, the carrier concentration increases.

つまり第3図及び第4図を比較して明らかなよう、本発
明方法によって得た電子供給N(3)によるHEMTは
そのしきい値電圧vthがウェファの各位Wによって殆
ど変動することなく一様につまりキャリア濃度がウエフ
ァ面内で均一になっていることがわかる。
In other words, as is clear from a comparison of FIGS. 3 and 4, the threshold voltage vth of the HEMT with electron supply N(3) obtained by the method of the present invention is uniform with almost no variation depending on each part W of the wafer. In other words, it can be seen that the carrier concentration is uniform within the wafer surface.

なお上述した例においては、基体温度を一定に保持して
アンドープの気相成長工程と不純物ドーピング工程とを
連続的に行った場合であるが、それぞれ温度条件を丈え
ることもできる。
In the above-mentioned example, the undoped vapor phase growth step and the impurity doping step are performed continuously while keeping the substrate temperature constant, but the temperature conditions can be adjusted for each.

また本発明をn−^I InAsを得る場合に適用した
例を主として説明したが、他の各種化合物半導体に対す
る不純物ドーピングがなされる化合物半導体の成長方法
に適用することができる。
Furthermore, although the present invention has been mainly described as an example in which it is applied to obtaining n-^I InAs, it can also be applied to a method for growing compound semiconductors in which various other compound semiconductors are doped with impurities.

〔発明の効果] 上述したように本発明方法によれば、化合物半導体層の
全体の不純物濃度がとびとびの値を採るものの各値に関
しては均一に得ることができウェファの位置によること
なくウエファの全域に亘って均一な濃度に設定すること
ができるので安定して所定の特性を有する目的とする半
導体装置を再現性良く確実に得ることができ、その量産
性の向上と歩どまりの向上を図ることができる。
[Effects of the Invention] As described above, according to the method of the present invention, although the overall impurity concentration of the compound semiconductor layer takes discrete values, each value can be uniformly obtained, regardless of the position of the wafer. Since the concentration can be set uniformly over the area, it is possible to reliably obtain a target semiconductor device having predetermined characteristics with good reproducibility, thereby improving mass productivity and yield. I can do it.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による化合物半導体の成長方法の一例の
説明に供する工程図、第2図は不純物原料ガスの供給量
に対するキャリアの面密度の測定結果を示す図、第3図
及び第4図は本発明方法及び従来方法によるウェファ上
の各位置としきい値電圧vthとの関係の測定結果を示
す図、第5図は高電子移動度HEMTの略線的断面図で
ある。 (1)は基体、(2)はハリア層、(3)は電子供給層
、(l2)は化合物半導体層、(12A)はアンドープ
化合物半導体層、(12B)は不純物ドーピング層であ
る。
FIG. 1 is a process diagram for explaining an example of the method for growing a compound semiconductor according to the present invention, FIG. 2 is a diagram showing measurement results of the areal density of carriers with respect to the supply amount of impurity raw material gas, and FIGS. 3 and 4 5 is a diagram showing the measurement results of the relationship between each position on the wafer and the threshold voltage vth by the method of the present invention and the conventional method, and FIG. 5 is a schematic cross-sectional view of a high electron mobility HEMT. (1) is a substrate, (2) is a Haria layer, (3) is an electron supply layer, (12) is a compound semiconductor layer, (12A) is an undoped compound semiconductor layer, and (12B) is an impurity doped layer.

Claims (1)

【特許請求の範囲】 アンドープ化合物半導体層を気相成長させる工程と、 この気相成長を停止させた状態で不純物原料ガスを供給
してキャリアの面密度がほぼ飽和する量までドーピング
する工程と、 を有することを特徴とする化合物半導体の成長方法。
[Claims] A step of growing an undoped compound semiconductor layer in a vapor phase; A step of doping the layer by supplying an impurity raw material gas while stopping the vapor phase growth until the areal density of carriers is almost saturated; A method for growing a compound semiconductor, characterized by having the following.
JP2013125A 1990-01-23 1990-01-23 Compound semiconductor growth method Expired - Fee Related JP3057503B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013125A JP3057503B2 (en) 1990-01-23 1990-01-23 Compound semiconductor growth method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013125A JP3057503B2 (en) 1990-01-23 1990-01-23 Compound semiconductor growth method

Publications (2)

Publication Number Publication Date
JPH03218008A true JPH03218008A (en) 1991-09-25
JP3057503B2 JP3057503B2 (en) 2000-06-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013125A Expired - Fee Related JP3057503B2 (en) 1990-01-23 1990-01-23 Compound semiconductor growth method

Country Status (1)

Country Link
JP (1) JP3057503B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010192880A (en) * 2008-12-29 2010-09-02 Imec Method for manufacturing junction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010192880A (en) * 2008-12-29 2010-09-02 Imec Method for manufacturing junction

Also Published As

Publication number Publication date
JP3057503B2 (en) 2000-06-26

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