JPH03217017A - Semiconductor device - Google Patents

Abstract

PURPOSE:To use a minute electrode contact window, to decrease contact resistance and to form a wiring body having an excellent step coverage by embedding a conductor film into a hole which is formed in insulating films on a semiconductor layer and in a part of the semiconductor layer, and providing a wiring body which is connected to the conductor film. CONSTITUTION:A semiconductor layer 2 is provided in a semiconductor substrate 1 or on the semiconductor substrate 1. Insulating films 4 and 5 are provided on the semiconductor layer 2. A hole 6 is formed in the insulating films 4 and 5 and in a part of the semiconductor layer 2. A conductor film 7 is embedded in the hole 6 and connected to the side surface part and the upper surface part of the semiconductor layer 2. A wiring body 8 is connected to the conductor film 7. These parts are provided. For example, the electrode contact window 6 is formed not only in the impurity blocking oxide film 4 and the PSG film 5 provided on the N<+>-type impurity region 2 but also in a part of the N<+>-type impurity region 2. The tungsten film 7 grown in vapor phase by selective chemical growth is flatly embedded in the electrode contact window 6. One of the film 7 is connected to the side surface part and the upper surface part of the N<+>-type impurity region 2, and the other is connected to the Al wiring 8.

Description

[Detailed Description of the Invention] [Summary] A relatively high resistance semiconductor layer made of an impurity region formed in a semiconductor substrate or a relatively high resistance semiconductor layer made of polycrystalline silicon formed on a semiconductor substrate. For connection with the extremely low resistance AI wiring body, not only is an electrode contact window provided in the insulating film to expose the surface of the semiconductor layer, but also an electrode contact window is provided on the exposed semiconductor layer so that the side surface of the semiconductor layer is also exposed. Since the electrode contact window is provided with a low-resistance conductive film buried flatly in the electrode contact window, the conductive film buried in the side and top surfaces of the semiconductor layer is Since the contact area can be increased three-dimensionally from the bottom of the electrode contact window, it is possible to reduce resistance to contact 1, thereby increasing speed and integration. A semiconductor device that can be embedded, making it possible to form a wiring body with a good stepping force barrier, making it possible to achieve high reliability.

[Industrial Field of Application] The present invention relates to MIS and bibolar semiconductor devices, and particularly to a semiconductor device that enables the formation of high-speed, highly integrated semiconductor integrated circuits with reduced contact resistance using fine electrode contact windows.

Conventionally, in connection between a semiconductor layer (impurity region, polycrystalline silicon layer, etc.) and an A1 wiring body, an electrode contact window is opened in an insulating film formed on the semiconductor layer to expose the surface of the semiconductor layer. Connection was made by directly providing an A1 wiring body.However, in today's extremely high integration, semiconductor layer resistance can be reduced by making it finer, but electrode contact I
・Since the window is also made finer, the contact area becomes extremely small and contact I resistance increases, and high speed cannot be achieved despite the high integration.Also, since the window on electrode contact 1 becomes finer, the aspect ratio increases. As the ratio increases, it becomes impossible to form a wiring body with good stepping force leverage, and the problem of deterioration of the life of the wiring body is becoming more prominent. Therefore, there is a need for a means that can reduce contact resistance and form a wiring body with a good stepping force barrier by using fine electrode contacts and windows.・ [Prior Art] FIG. 5 is a schematic side sectional view of a conventional semiconductor device, and 51 is a p
1 type silicon (Si) substrate, 52 is an n0 type impurity region,
53 is a field oxide film, 54 is an oxide film for impurity blocking, 55 is a phosphosilicate glass (PSG) film, 5G is an electrode contact window, and 57 is an A1 wiring.

In the figure, an n0 type impurity region 52 is provided on a p type silicon substrate 51 and is insulated and isolated by a field oxide film 53, and an impurity blocking oxide film 54 provided on the n0 type impurity region 52 is shown. and phosphosilicate glass (PSG)
A connection between the n+ type impurity region 52 and the A1 wiring 57 is formed in the electrode contact window 56 formed in the film 55 . Due to high integration, the electrode contacts 1 to windows are formed finely, and the contact area decreases.
Since the contact resistance increases, high speed cannot be achieved, and since the aspect ratio increases, a wiring body with a good stepping force barrier cannot be formed, resulting in a shortened lifespan.

[Problems to be Solved by the Invention] The problems to be solved by the present invention are as shown in the conventional examples, because the contact area is reduced due to the fine formation of the electrode contact 1 and window, and the contact resistance is increased. Because of the increase in step force, it was not possible to achieve high speed, and because the aspect ratio increased, it was not possible to form a wiring body with a good stepping force barrier, so it was not possible to improve the deterioration of life.

[Means for Solving the Problems] The above problems include a semiconductor layer provided within a semiconductor substrate or on the semiconductor substrate, an insulating film provided on the semiconductor layer, and the insulating film and the semiconductor layer. of the present invention, comprising: an opening provided in a part of the semiconductor layer; a conductive film embedded in the opening and connected to a side surface and a top surface of the semiconductor layer; and a wiring body connected to the conductive film. This problem can be solved by semiconductor devices.

[Function] That is, in the semiconductor device of the present invention, a relatively high resistance semiconductor layer made of an impurity region formed within a semiconductor substrate or a relatively high resistance semiconductor layer made of polycrystalline silicon formed on a semiconductor substrate. The connection between the layer and the extremely low-resistance A1 wiring body is achieved by not only opening holes in the insulating film to expose the surface of the semiconductor layer, but also openings in the exposed semiconductor layer so that the side surfaces of the semiconductor layer are also exposed. A hole is provided, and the structure is formed with a conductive film buried flatly in the hole. Therefore, it is possible to form a connection with the buried conductive film on the side and top surfaces of the semiconductor layer, and the contact area can be three-dimensionally increased compared to the bottom surface of the electrode contact I/window, thereby reducing contact resistance. In order to achieve higher speed and higher integration, the conductive film can be flattened into the electrode contact window formed in part of the insulating film and semiconductor layer, making it possible to form a wiring body with a good stepping force barrier, thereby extending the life of the wiring body. High reliability can be achieved by improving the That is,
It is possible to obtain a semiconductor device that enables the formation of extremely high-speed, highly integrated, and highly reliable semiconductor integrated circuits.

[Examples] The present invention will be specifically described below with reference to illustrated examples. 1 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention, and FIG. 2 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention.
FIG. 3 is a schematic side sectional view of the third embodiment of the semiconductor device of the present invention, and FIGS.
(e) is a process cross-sectional view of one embodiment of the manufacturing method for the semiconductor device of the present invention.

Identical objects are indicated by the same reference numerals throughout the figures.

FIG. 1 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention when a p-type silicon substrate is used, and 1 is 10
``'c''p type silicon (Si) substrate of about 3, 2 is 10'', n0 type impurity region of about 0Cm-3, 3 is 000
4 is a field oxide film of about 35 nm, 5 is a phosphosilicate glass (PSG) film of about 600 nm, 6 is an electrode contact window of about 600 nm, and 7 is a buried conductive film (selectable). It is a chemical vapor.

In the figure, an n+ type impurity region 2 is provided on a p type silicon substrate 1 and is insulated and isolated by a field oxide film 3. The electrode contact window 6 is made of an impurity blocking oxide film 4 provided on the n+ type impurity region 2, a phosphosilicate glass (
A conductive film (selective chemical vapor deposition tungsten film) 7 with low resistance is formed not only on the PSG) film 5 but also on a part of the n-type impurity region 2, and a conductive film (selective chemical vapor deposition tungsten film) 7 with low resistance is formed on the electrode contact 1 to the window 6. One side is connected to the side surface and the top surface of the n+ type impurity region 2, and the other side is connected to the A1 wiring 8. Therefore, it is possible to form connections with the buried conductive film on the side and top surfaces of the semiconductor layer, which have relatively high resistance, and the contact area can be three-dimensionally increased from the bottom surface of the electrode contact window.
・High speed and high integration due to the reduction of resistance, and the ability to flatten the conductive film into the electrode contact window formed in a part of the insulating film and semiconductor layer, forming a wiring body with a good stepping force barrier. Therefore, high reliability can be achieved by improving the life of the wiring body. Note that in the connection between the conductive film (selective chemical vapor deposition tungsten film) 7 and the A1 wiring 8, since both have low resistance, the contact resistance is also low and does not pose a problem.

FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention, in which 1 to 8 are the same as in FIG. 1, and 9 is an n0-type impurity region subjected to compensation diffusion. .

In the same figure, since the electrode contact window 6 is formed deeper than the n0 type impurity region 2, the n0 type is compensated and diffused to prevent the AI wiring 8 from being exposed to the p1 type silicon substrate 1. The structure is the same as that in FIG. 1 except that impurity region 9 is formed. In this embodiment, since the contact resistance can be further reduced than the effect of the first embodiment, it is possible to achieve even higher speed and higher integration.

FIG. 3 is a schematic side sectional view of a third embodiment of the semiconductor device of the present invention, in which 1, 3 to 8 are the same as in FIG. 1, and 10 is a semiconductor layer (n+ type polycrystalline silicon layer). It shows.

In the figure, a semiconductor layer (n+ type polycrystalline silicon layer) 10 on a field oxide film 3 on a p-type silicon substrate 1 is shown.
The structure is the same as that in FIG. 1 except that the connection with the A1 wiring is formed in FIG.

In this embodiment as well, it is possible to obtain the same effects as in the first embodiment.

Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 4(a) to 4(e) and FIG. 1. However, only the manufacturing method related to the connection between the semiconductor layer and the wiring body will be described here, and the description of the manufacturing method related to the formation of various elements (transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit will be omitted.

Figure 4 (a) By applying the usual LOCOS technique,
I) A field oxide film 3 of about 600 nm is formed on a type 1 silicon substrate 1.

FIG. 4(b) Next, a thin oxide film (not shown) for ion implantation is formed.Next, using normal photolithography technology,
Using a resist (not shown) and field oxide film 3 as a mask layer, arsenic ions are implanted to selectively define n+ type impurity regions 2.

Then the resist is removed. Next, the thin oxide film for ion implantation is removed.

FIG. 4(C) Next, about 351 impurity blocking oxide films 4 are grown. Next, about 600 nn+ phosphosilicate glass (PSG
9) To grow the film 5, high-temperature heat treatment is then performed to control the activation and depth of the n+ type impurity region 2.

FIG. 4(d) Next, using a conventional photolithography technique and using a resist (not shown) as a mask layer, phosphosilicate glass (P) is deposited.
A part of the silicon substrate 1 on which the SG) film 5, the impurity blocking acid film 4, and the n+ type impurity region 2 are formed is dry-etched to selectively form electrode contact windows 6. Then the resist is removed.

FIG. 4(e) Next, a selective chemical vapor deposition tungsten film 7 is grown,
The electrode contact window 6 is buried flat, and connections between the side and top surfaces of the n+ type impurity region 2 and the selective chemical vapor deposition tungsten film 7 are formed.

Fig. 1 Next, an A1 film of about IPm is grown by sputtering 9
Next, using a normal photolithography technique, the A1 film is selectively dry-etched using a resist (not shown) as a mask layer to form an A1 wiring 8, and then a selective chemical vapor deposition tungsten film 7 and an A1 wiring 8 are formed. form a connection with.

As shown in the embodiments above, according to the semiconductor device of the present invention, it is possible to form a connection with the conductive film of low resistance buried in the side and top surfaces of the semiconductor layer of relatively high resistance, so that electrode contacts can be formed. Since the contact area can be three-dimensionally increased from the bottom of the window, contact resistance can be reduced, resulting in higher speed and higher integration. Since the wiring body can be embedded flatly and has a good stepping force barrier, it is possible to improve the life of the wiring body and achieve high reliability.

[Effects of the Invention] As described above, according to the present invention, in MIS and bibolar semiconductor devices, when connecting a relatively high-resistance semiconductor layer to a low-resistance wiring body, the side and top surfaces of the semiconductor layer are Since it is possible to form a connection with the conductive film with low resistance buried in the bottom part of the electrode contact window, the contact area can be three-dimensionally increased from the bottom part of the electrode contact window.
Since the conductive film can be flatly embedded in the electrode contact window formed in the insulating film and a part of the semiconductor layer, high reliability can be achieved by forming a wiring body with a good stepping force barrier. . In other words, extremely fast, highly integrated day 6 highly reliable ``1''. A semiconductor device that allows formation of a conductor integrated circuit can be obtained.

[Brief explanation of drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of a semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of a second embodiment of a semiconductor device of the present invention, and FIG. 3 is a semiconductor device of the present invention. A schematic side sectional view of a third embodiment of the device; FIGS. 4(a) to (e) are process sectional views of an embodiment of the manufacturing method for the semiconductor device of the present invention; FIG. 5 is a schematic side sectional view of a conventional semiconductor device. It is a schematic side sectional view. In the figure, l is a p-type silicon (Si) substrate, 2 is an n-type impurity region, 3 is a field oxide film, 4 is an oxide film for impurity blocking, 5 is a phosphosilicate glass (PSG) film, and 6 is an electrode contact. 7 is a buried conductive film (selective chemical vapor deposition tungsten film), 8 is an AI wiring, 9 is a compensated diffusion n-type impurity region, and 10 is a semiconductor layer (n-type polycrystalline silicon layer). show.

Claims (1)

[Claims] A semiconductor layer provided within a semiconductor substrate or on the semiconductor substrate, an insulating film provided on the semiconductor layer, an aperture provided in a part of the insulating film and the semiconductor layer, and an aperture provided in the aperture. A semiconductor device comprising: a conductive film embedded in the semiconductor layer and connected to a side surface and a top surface of the semiconductor layer; and a wiring body connected to the conductive film.