JPH03216568A - Test waveform generating system - Google Patents

Abstract

PURPOSE:To accurately generate a waveform and to miniaturize a circuit by adding the skew correction quantity of a signal pulse to the difference between a set timing time and a phase clock timing time in a shared resource type waveform generator to delay a phase clock signal. CONSTITUTION:Delay circuits 6a, 6c are provided to a waveform formatter 7 to make it possible to set a delay time by delay quantity setting registers 6b, 6d. The next correction quantity is added to the difference between this set timing time and the phase clock signal obtained by dividing the reference clock signal of a reference clock signal generating circuit 21 by a frequency divider circuit 22. That is, the phase clock signal is delayed only by the delay time wherein the skew correction quantity of the actually measured or calculated signal pulse determined by the phase clock signal and a pin position is added. As a result, even in a shared resource system, a test waveform of correct timing is accurately generated and a circuit scale can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test waveform generation method, and in particular, to a method for generating test waveforms for multiple ICs, such as generation of test waveform patterns for IC inspection.
The present invention relates to a test waveform generation method that allows easy setting of test waveform generation timing in a pattern generation system for a tester that generates respective waveform patterns on test pins.

[Prior Art] In an IC testing system, a multi-bit test waveform pattern necessary for performance and functional testing of an IC is
Automatically generated according to a test pattern program, etc. Therefore, as a conventional pattern generation system,
By using a common timing generator, the pattern data obtained from the pattern generator and the timing signal (hereinafter referred to as phase clock signal) having multiple phases generated by the timing generator are separated for each pin of the IC. There is a shared resource method in which each of the necessary items is selected and the desired waveform pattern is generated at a predetermined timing using the same waveform generation circuit, and a bar pin method in which a timing generator is created independently for each pin in the above case. be.

[Problem to be solved] In the shared resource method, the pin that supplies the phase clock signal generated by the timing generator is not fixed, but is determined depending on the test content, so the signal to the supply pin is Transmission path (hereinafter referred to as signal path)
Different skews occur depending on the difference in . Therefore, there is a disadvantage that the timing control becomes complicated because there are many gates that perform timing adjustment according to correction items depending on the difference in the length of the signal bus and the selected phase of the phase clock signal.

・On the other hand, the per-pin method requires almost no adjustment using gates, etc., and the signal path is fixed, so skew factors can be reduced and highly accurate timing correction is possible. Since this must be provided, the circuit scale inevitably increases.

The purpose of this invention is to solve the problems of the prior art, and to provide a test waveform generation method that does not require a large circuit scale and can perform highly accurate timing correction in the shared resource method. do.

[1000 Steps to Solve the Problem] The configuration of the test waveform generation method of the present invention to achieve such an objective is as follows: A timing generator that generates a plurality of timing signals each having a different phase, a selector that selects a predetermined timing signal according to the first control information, and one of a plurality of predetermined delay amounts can be selected according to the second control information, and the timing obtained as the output of the selector. a plurality of waveform generation circuits each having a delay circuit that delays a signal by a selected delay amount and outputs the signal; and a waveform formatter that receives a timing signal delayed by the delay circuit and generates a test waveform that is waveform-shaped by the delay circuit; a control device 7 for generating first control information and second control information, adding the first control information to the selector, and adding second control information to the delay circuit; -7 of the test waveform from the outside. When one of the timing times for L up, s7, and down is set, the timing signal with the phase that is closest to it and before it is selected from among multiple timing signals. Yes, and the second control information is determined by the first control information from the skew correction time determined by the timing signal selected by the first control information and the pin from which the test waveform is sent, and the timing set from the outside. The delay time that is the same as or closest to the time obtained as the sum of the time and the difference obtained by subtracting the time determined by the phase of the selected timing signal is selected.

[Function] In this way, by providing a delay circuit in which the delay time can be set in the waveform generation circuit, the phase clock signal and the pin signal are Note that timing pulses for the waveform formatter are generated by delaying the phase clock signal by the delay time determined by the actually measured or calculated signal path skew correction amount. If you do not use the per-pin method, you can also use the
A test waveform close to the EL timing can be easily generated.

As a result, the shared resource method allows the circuit scale to be reduced, and test waveforms can be generated at accurate timing regardless of the selected phase clock signal.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

Fig. 1 is a block diagram of the configuration of an embodiment, focusing on the timing generator and waveform generation circuit of a tester to which the test waveform generation method of the present invention is applied, and Fig. 2 shows skew correction in the memory of the control circuit. FIG. 2 is an explanatory diagram of a table regarding delay times for .

In FIG. 1, reference numeral 2 denotes a timing signal IT generation circuit, which is composed of a count clock generation section 2 and a timing clock generation section 3.

4a, 4b+ ●Fist● is a waveform generation circuit, and each waveform generation circuit 4a, 4b. Each of ●Φ● is
A selector 5a, a select data register 5b, a delay circuit 8a that generates a timing signal on the rising side of σ, a delay amount setting register 6b1, a delay circuit 8cs that generates a timing signal on the falling side, a delay amount setting register 6d, and a delay circuit 6a. , 6c.

Here, the delay circuits 8a*6c are each configured with tapped delay lines, and the delay amount setting registers 8b,
The tap is selected by the data set to 6d, and a predetermined amount of delay is applied to the phase clock signal, which is applied to the waveform formatter 7 as a timing pulse.

The waveform former 7 receives pattern data from the pattern generator 10 and sends the pattern data to the delay circuits 8a. A test waveform that rises and falls in response to the output of the pin electronics circuit 8c, or a test waveform that is the opposite thereof, is sent to a drive circuit provided corresponding to the pin of the pin electronics circuit 8.

The count clock generation section 2 includes a reference clock signal generation circuit 2l and a frequency division circuit 22 that divides the frequency of the reference clock signal output from this circuit.
2 receives a reference clock signal from the reference clock signal generation circuit 21 and converts it into a timing count clock signal having an integer multiple of the cycle (frequency of 1/integer) to match the cycle of the clock signal serving as the reference for timing count. Reduced to . The clock signal (counter clock signal 22a) reduced by this frequency dividing circuit 22 is then sent to the timing clock generator 3.

The timing clock generator 3 includes a timing count circuit 31a that counts timing count clock signals to generate a rate signal, and a timing count circuit 3lb. that counts timing count clock signals to generate a phase clock signal. 31c.
●●● and each of these timing count circuits 31as
3lb, 31c. Each is provided corresponding to ●●●,
NM circuit matrix 32at 32bt 32c* @ which receives each output pulse signal from these
@@, and each timing count circuit 31a, 3lb
, 3lc, ●O● and delay circuit matrix 3 2
a t 32bt 32c. Data memory 33at 33bt 33ct e e provided corresponding to s@e and storing timing data set therein
It is composed of e.

Here, each timing count circuit 3 1 al 3
lb, 31c●●● are external (for example, CPU
12 or the pattern generator 11), the timing count clock signal sent from the frequency divider circuit 22 and having a reference period for counting timing is counted, and the period setting value Nat for the pulse generation period is calculated. * Nbr w NCI m "●● is received in a corresponding manner and generates a pulse signal with a period corresponding to each one, and has, for example, an internal register and a preset counter. And ,
When each cycle setting value is set in each register, the set value is set in the preset counter, which is counted by the timing count clock signal from the frequency divider circuit 22, and every time the count is completed. A pulse signal is generated, and the value of the register is reset to each period setting value Nal t N bl + N Cl *
The timing count circuit 31a sequentially generates periodic pulse signals corresponding to ●●● as rate pulse signals, and the timing count circuits 3lb, 31c●●●
Then, the phase clock signals are generated sequentially. Note that the data memories 33a+ 33bs 33c. 3mm
Cycle setting value N a1 * N bl
v N cs +4I41● is given in real time from the pattern generator 7 as an RTTC signal (real time timing control signal). Further, the signal 22b returned from the timing count circuit 31a is a counter reset signal.

The periodic pulse signal obtained from each timing count circuit is then connected to the delay circuit matrix and 32 at 3
2 b+ 3 2 C* ” ” are manually inputted respectively. Each delay circuit matrix 32a.32b.3
2c, ●●● is a circuit that adjusts the generation timing of a rate pulse signal or a phase clock signal by adding a time greater than the resolution of the reference clock signal, for example,
For a pulse signal generated at a period of several tens of ns to several hundred ns, a delay time in the range of lns to 10 ns can be selected in ins units, and the time can be adjusted.

The selection of the delay time of each delay circuit matrix can be done using data memo in the same way as the period selection above. J 3 3 as 33
b+ 33c, Timing setting value for the delay time given to ●●● Na2 e Nb2 * NC2
*Performed according to the value of #Fist●. Therefore, each delay circuit matrix receives each of the above-mentioned timing setting values in a corresponding manner and provides a corresponding delay time to the periodic pulse signal received from the timing count circuit.

In addition, when not under RTTC control, each data memory 3
The cycle setting values Na1, Nbl, Ncl, ●●● set to 3a, 33b, 33c, *e* and the timing setting value Na21 N b2t N C2 t●●● are set in advance from the CPU 12 before the test starts. set,
Rate pulses and respective phase clock signals are generated accordingly.

The rate pulse signal and each phase clock signal thus delayed to appropriate values by each delay circuit matrix are then applied to the waveform generation circuits 4a+4b+Φ●●, respectively.

Each waveform generation circuit 4at 4bt ●-● (hereinafter, one of them is represented by waveform generation circuit 4) has its selector 5
A phase clock signal having a timing phase necessary for waveform shaping is selected by a. This selection is performed using data sent in advance from the CPU 12 and set in the select data register 5b.

Here, the selected phase clock signal is normally applied to the delay circuit 6a on the rising side and the delay circuit 6C on the falling side, respectively. Of course, just one of them is fine. The delay time of the delay circuit 6a is determined by the setting data of the delay fItti setting register 6b sent in advance from the CPU 12, and the phase clock signal skew-corrected by the selected delay amount is sent as a rising timing pulse to the waveform format. be done. Similarly, the delay time of the delay circuit 6C is determined by the setting data of the delay amount setting register 6d sent in advance from the CPU 12, and the phase clock signal skew-corrected by the delay amount is converted into a waveform format as a rising edge timing pulse. Sent out.

This determines whether the pattern data added to the waveform format tough from the pattern generator 11 rises and falls at a predetermined timing, or conversely falls and rises.
It is shaped as a test waveform that either only rises or only falls, and is output to the selected pin of the device under test (DUT) via the pin electronics circuit 8.By the way, the setting from cput2 mentioned above is output to the selected pin of the device under test (DUT). select data register 5b, delay amount setting register eb,
The data of ea is generated by the CPU 12 by referring to the NM time storage table stored in the memory 13.

Next, to explain this point, the memory 13 includes a phase clock pin skew correction amount table 13a as shown in FIG. 2(a), and a delay circuit 6 as shown in FIG. 2(b). A tap number table 13b1 that compares the NM amount of a * 6 c (these are the same circuit) and its tap number, and a delay data calculation/setting program 13c are stored.

Phase clock●Pin skew correction amount table l3a is
As shown in the figure, it is a matrix table of the identification number of the phase clock signal to be selected and the pin number to which the test waveform is added, and the amount of skew correction required at the intersection is stored, and the pin number of the phase clock signal and the pin number are stored. is selected, the skew correction voltage is searched. The skew correction amount stored here is determined when a certain number of phase clock signal and a certain pin number are selected in the hardware circuit when the pattern generation circuit is actually assembled. It is given as the actual skew correction value (corrected delay time) obtained by actually measuring the actual signal path. Note that this may be calculated from the length of the wiring, the operation delay time of the circuit, and the like.

Therefore, the timing value TJ that should be set as a test
When (time from rate pulse) is entered manually from outside (including when set as a program), i! ! The extension data calculation/setting program l3c calculates this timing value TJ! if the timing occurs. Set the count value that occurs at a short time timing that is closest to and slightly before this to one of the timing count circuits 31b * 31c, phase clock signal). If the time from the rate pulse of the phase clock signal is Ts, the time Td of these differences is Td
=TJ-Ts.

In addition, by referring to the phase clock pin skew correction amount table 13a in FIG. 2(a) using the number of the selected phase clock signal that becomes the phase clock signal at time Ts and the pin number to which the test waveform is added, Obtain the skew correction m T c of the signal path. Here, the delay data calculation/setting program 13c calculates the setting delay time Tdc=T
Calculate d + Tc.

Next, the delay data calculation/setting program 13c obtains a tap number with a delay time that matches or is closest to the set delay time Tdc by referring to the tap number table 13b, and the CPU 12 uses the tap number thus obtained. When the rising timing is specified, the data for selecting 17. (When the trailing timing is specified) 7. and the delay time setting register 6d of the delay side 6c. At the same time, the CPU 12 also sends data for selecting the selected phase clock signal number to the select data register 5b.

By doing the following I-, even in the shared resource method, it is possible to generate a test waveform finely and appropriately skew-corrected corresponding to the phase clock signal selected corresponding to the pin.

As explained above, in the embodiment, the frequency of the reference clock signal is divided by the frequency divider circuit to generate the timing count clock signal. Of course, the timing count clock signal may be counted by a timing count circuit. Therefore, a frequency dividing circuit is not necessarily required.

[Effects of the Invention] As can be understood from the above explanation, in the present invention, a delay circuit capable of setting a delay time is provided in the waveform generating circuit, and the timing time of the set timing time and the timing time of the phase clock signal are adjusted. Generate timing pulses for the waveform formatter by delaying the phase clock signal by the difference time plus the actual measured or calculated signal path skew correction amount determined by the phase clock signal and the pin. Therefore, when selecting the timing, it is possible to easily generate a test waveform close to the correct timing without using the per-pin method and without being aware of the amount of correction.

As a result, the shared resource method allows the circuit scale to be reduced, and test waveforms can be generated at accurate timing regardless of the selected phase clock signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of an embodiment centered on a timing generator and a waveform generation circuit of a tester to which the test waveform generation method of the present invention is applied, and FIG. 2 is a skew correction in the memory of the control circuit. FIG. 2 is an explanatory diagram of a table regarding delay times for . DESCRIPTION OF SYMBOLS 1... Timing signal generation circuit, 2... Count clock generation part, 3... Timing clock generation part, 4.4a, 4b... Waveform generation circuit, 5a... Selector, 5b... Select data register N Bat eb...Delay circuit, Oct 8d...
・Delay; i setting register, 7... him-gata formattuta,
11... Pattern generator, 12... CPU113.
...Memory, 13a...Phase clock ●Pin skew compensation + Effi table, 13b...Tap number table, 13c...Delay data calculation/setting program, 2
1... Reference clock signal generation circuit, 2 2-... Frequency division circuit, 31a, 31bt 31c"" timing count circuit, 32a. 322, 32c... slow circuit matrix,
3 3 a+ 3 3 bt 3 3 c”・Data memory.

Claims (2)

[Claims] (1) A timing generator that generates a plurality of timing signals with different phases, a selector that receives each of the plurality of timing signals and selects a predetermined timing signal according to first control information, and second control information. You can select one of multiple predetermined delay amounts depending on the
It has a delay circuit that delays the timing signal obtained as the output of the selector by a selected delay amount and outputs the delayed signal, and a waveform formatter that receives the timing signal delayed by the delay circuit and generates a waveform-shaped test waveform. comprising a plurality of waveform generation circuits, and a control device that generates first control information and second control information, adds the first control information to the selector, and adds second control information to the delay circuit. , the first control information is such that when the timing time for either the rise or fall of the test waveform is set from the outside, the timing signal having the phase that is closest to the timing and the timing before it is set as the timing signal. The second timing signal is selected from among multiple timing signals.
The control information is selected by the first control information from the skew correction time determined by the timing signal selected by the first control information and the pin to which the test waveform is sent, and the timing set from the outside. A test waveform generation method is characterized in that a delay time that is the same as or closest to the time obtained as the sum of the time determined by the phase of a timing signal obtained by subtracting the time determined by the phase of a timing signal is selected. (2) The skew correction time is stored as a table determined on a one-to-one basis based on the relationship between each timing signal of a plurality of phases and a pin from which a test waveform is sent. Test waveform generation method.