JPH03211735A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03211735A JPH03211735A JP2006660A JP666090A JPH03211735A JP H03211735 A JPH03211735 A JP H03211735A JP 2006660 A JP2006660 A JP 2006660A JP 666090 A JP666090 A JP 666090A JP H03211735 A JPH03211735 A JP H03211735A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- bumps
- substrate
- semiconductor chip
- flexible sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 229910000679 solder Inorganic materials 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000004642 Polyimide Substances 0.000 claims abstract description 3
- 229920001721 polyimide Polymers 0.000 claims abstract description 3
- 238000007789 sealing Methods 0.000 claims description 17
- 239000004020 conductor Substances 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置のはんだ封止技術、特に、半導体チ
ップをはんだバンプによって多層配線基板に接続するた
めに用いて効果のある技術に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a solder sealing technology for semiconductor devices, and in particular to a technology that is effective when used to connect a semiconductor chip to a multilayer wiring board using solder bumps. be.
Ｌｌｒ（大規模集積回路）の実装方法として、種々の方
式が提案されている。その代表的なものに、 Ｆ Ｔ
Ｃ（Ｆｌｉｐｐｅｄ ＴＡＢ Ｃａｒｒｉｅｒ： ７リ
ツプ・ＴＡＢ・キャリア）及びＭ ＣＣ（Ｍｉｃｒｏ
Ｃｈｉ、ｐ Ｃａｒ’ｒｉｅｒ：マイクロ・チップ・キ
ャリア）がある。Various methods have been proposed as methods for implementing LLRs (large-scale integrated circuits). A typical example is F.T.
C (Flipped TAB Carrier: 7-lip TAB Carrier) and MCC (Micro
There is a microchip carrier.
ＭＣＣは、はんだ接続面にはんだバンプ（ＣＣＢ ＝
Ｃｏｎｔｒｏｌｌｅｄ ＣａＩＩａｐｓｅ ＢｏｎｄＩ
ｎｇ ： ：７ントロールド・コラプス・ボンディング
）を備えた半導体チップを基板（またはベース）に接続
すると共に、キャップの内面を半導体チップの放熱面に
はんだ接続すると同時に封止部を基板にはんだ接続する
構成になっている。MCC is a solder bump (CCB =
Controlled CaIIapse BondI
A configuration in which a semiconductor chip equipped with ng : : 7-trolled collapse bonding is connected to a substrate (or base), the inner surface of the cap is soldered to the heat dissipation surface of the semiconductor chip, and the sealing part is soldered to the substrate at the same time. It has become.
また、第２図はＦＴＣの構成例を示す断面図であり、こ
の構成の詳細について以下に説明する。Further, FIG. 2 is a sectional view showing an example of the configuration of the FTC, and the details of this configuration will be explained below.
ＬＳＩ （大規模集積回路）が構成されているチップ】
は、下面にチップ外形より先端部がはみ出すようにして
Ｔ Ａ Ｂ （Ｔａｐｅ Ａｕｔｏｍａｔｅ＋ｊ Ｂｏ
ｎｄｉｎｇ）リード２が周辺部より一定間隔に突設され
ている。A chip that consists of an LSI (Large-Scale Integrated Circuit)]
T A B (Tape Automate+j Bo
(nding) Leads 2 are provided protruding from the periphery at regular intervals.
チップ１は下部にシリコンラバー３を介挿した状態で基
板４にはんだ接続される。基板４は、下部にツルｌ／
ハンプ５を備え、このソルダバンプ５はＴ Ａ Ｂ Ｉ
Ｊ−ド２の各々に電気的に接続されている。The chip 1 is soldered to a substrate 4 with a silicone rubber 3 inserted underneath. The board 4 has a vine l/
Equipped with a hump 5, this solder bump 5 is T A B I
It is electrically connected to each of the J-dos 2.
また、基板４には、放熱器となるキャップ６（材料は銅
とタングステンの合金）がチップ１を内蔵するようにし
てンーム溶接７によって固定されている。また、チップ
Ｉの上面とキャップ６の天井面とがグイ接着８により固
定される。Further, a cap 6 (made of an alloy of copper and tungsten) serving as a heat sink is fixed to the substrate 4 by welding 7 so as to incorporate the chip 1 therein. Further, the upper surface of the chip I and the ceiling surface of the cap 6 are fixed with a glue 8.
この構成では、チップ１が回路面を下側に向けて搭載さ
れ、発熱による影響を低減すると共に、キャップ６０組
付は時にシリコンラバー３がチップ１を押し上げるよう
に作用するので、グイ接着８による接着が確実に行われ
る。In this configuration, the chip 1 is mounted with the circuit surface facing downward, reducing the effect of heat generation, and when the cap 60 is attached, the silicone rubber 3 sometimes acts to push up the chip 1, so the adhesive 8 Adhesion is ensured.
なお、この種のＦＴＣに関するものに、例えば、工業調
査会発行「電子材料４１９８９年７月号、Ｐ６０〜Ｐ６
５に記載がある。In addition, regarding this type of FTC, for example, "Electronic Materials 4, July 1989 issue, published by Kogyo Research Association, P60-P6
It is described in 5.
ところが、上ａ己のＦＴＣによる半導体装置では、Ｔ
Ａ Ｂ ｌｊ−ドの取り出しがチップの周辺部に偏り、
１．０（１０４を子を越える高密度実装についての配慮
がなされておらず、実装効率の向上に問題がある。However, in the semiconductor device manufactured by the company's FTC, T
A B lj- The ejection of the board is biased towards the periphery of the chip,
1.0 (no consideration is given to high-density mounting exceeding 104 children), and there is a problem in improving mounting efficiency.
一方、ＭＣＣは高密度実装には最適であるものの、パッ
ケージ構造が剛構造であるため、ＣＣＢバンプに過大な
力が加わり、ＣＣＢバンプの変形などを招き、最悪の場
合にはバンプ間接続を招く恐れがあり、製品歩留りを低
下させる原因になっている。On the other hand, although MCC is ideal for high-density packaging, its rigid package structure applies excessive force to the CCB bumps, leading to deformation of the CCB bumps and, in the worst case, causing bump-to-bump connections. This can lead to a decrease in product yield.
そこで、本発明の目的は、高密度実装に最も適したＣＣ
Ｂはんだ接合における機械的ダメージを最少にすること
のできる技術を提供することにある。Therefore, an object of the present invention is to provide a CC that is most suitable for high-density packaging.
B. It is an object of the present invention to provide a technique that can minimize mechanical damage in solder joints.
本発明の前記目的と新規な特徴は、本明細書の記述及び
添付図面から明らかになるであろう。The above objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、以下の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、多層配線が形成された基板に、はんだバンプ
を接続面に備えた半導体チップをはんだ接続すると共に
前証半導体チップを覆う如くにしてキャップを配設し、
その内面を前記半導体チップの放熱面にはんだ接続する
と共に封止部を前記基板にはんだ接続する半導体装置の
封止構造であって、前記基板と前記はんだバンプの間に
可撓性シートを配設するようにしている。That is, a semiconductor chip having solder bumps on the connection surface is connected by solder to a substrate on which multilayer wiring is formed, and a cap is provided to cover the semiconductor chip.
A sealing structure for a semiconductor device in which an inner surface of the semiconductor chip is solder-connected to a heat dissipating surface of the semiconductor chip and a sealing portion is solder-connected to the substrate, wherein a flexible sheet is disposed between the substrate and the solder bumps. I try to do that.
上記した手段によれば、半導体チップのはんだバンプが
可撓性シートに接触するのみで、基板側の部材に圧接す
ることがないため、はんだバンプは機械的な応力を受け
ず、変形やバンプ間接続を生じることがない。したがっ
て、製品歩留りを向上させることができる。According to the above-mentioned method, the solder bumps of the semiconductor chip only come into contact with the flexible sheet and are not pressed into contact with the members on the substrate side, so the solder bumps are not subjected to mechanical stress, and there is no deformation or gap between the bumps. No connection occurs. Therefore, product yield can be improved.
第１図は本発明による半導体装置の一実施例を示す断面
図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.
半導体チップ９は、例えば、大型コンピュータ用の中央
処理装置ｎ！（ＣＰＵ）であり、その片面には外部回路
に接続するためのはんだバンプ１ｏが形成されている。The semiconductor chip 9 is, for example, a central processing unit n! for a large computer. (CPU), and solder bumps 1o for connection to an external circuit are formed on one side of the CPU.
半導体チップ９に対し電気的に接続されると共に、半導
体装置の基台として用いられる板状の基板１１が絶縁材
料を加工して作成されている。基板１１には、チップ接
続面に薄膜多層膜工３が形成されており、この薄膜多層
膜１３上には、はんだバンプ１０に対応した数のはんだ
接続１ｆｆｌ１２が形成されている。このはんだ接続部
１２は、基板１１側の電極として機能している。A plate-shaped substrate 11 that is electrically connected to the semiconductor chip 9 and used as a base of the semiconductor device is fabricated by processing an insulating material. A thin film multilayer film 3 is formed on the chip connection surface of the substrate 11, and a number of solder connections 1ffl12 corresponding to the number of solder bumps 10 are formed on this thin film multilayer film 13. This solder connection portion 12 functions as an electrode on the substrate 11 side.
一方、半導体チップ９を密封状態にして覆蓋するキャッ
プ１４は、その凹部内に半導体チップ９が配設されるよ
うにして、その天井面が半導体チツブ９の放熱面に背面
はんだ１５によってはんだ溶着で固定され、また側壁部
が封止部はんだ１６によって基板１１にはんだ溶着で固
定される。背面はんだ１５及び封止部はんだ１６の溶着
が確実に行われるように、キャップ１４の水平面（天井
部及び封止部）及び基板１１の封止部には、予めメタラ
イズ部（不図示）が形成されている。On the other hand, the cap 14 that seals and covers the semiconductor chip 9 is configured such that the semiconductor chip 9 is disposed within the recessed portion, and its ceiling surface is solder-welded to the heat dissipation surface of the semiconductor chip 9 by the rear solder 15. The side wall portion is fixed to the substrate 11 by solder welding using the sealing portion solder 16. In order to ensure the welding of the back surface solder 15 and the sealing portion solder 16, metallized portions (not shown) are formed in advance on the horizontal surface (ceiling portion and the sealing portion) of the cap 14 and the sealing portion of the substrate 11. has been done.
さらに、はんだバンプｌＯとはんだ接続部１２の間に、
可撓性シート１７が配設されている。この可撓性シート
１７は、はんだ接続の際の機械的歪みを吸収することが
できるような材料、例えば、低熱膨張ポリイミドを用い
ることができる。そして、本実施例では、可撓性シート
１７を用いるほかに、はんだバンプ１０とはんだ接続部
１２が対向しないように、接続方向に対して偏心させて
いる。はんだバンプ１０とはんだ接続部１２の位置をず
らした場合、その電気的な接続を直接的には行えない。Furthermore, between the solder bump lO and the solder connection part 12,
A flexible sheet 17 is provided. This flexible sheet 17 can be made of a material that can absorb mechanical strain during solder connection, such as low thermal expansion polyimide. In this embodiment, in addition to using the flexible sheet 17, the solder bumps 10 and the solder connection portions 12 are made eccentric with respect to the connection direction so that they do not face each other. If the positions of the solder bumps 10 and the solder connections 12 are shifted, the electrical connection cannot be made directly.
そこで、可撓性シート１７に両者を接続するための導体
配線のパターンを形成しておくようにする。Therefore, a conductor wiring pattern for connecting the two is formed on the flexible sheet 17 in advance.
次に、上記実施例の組立てについて説明する。Next, the assembly of the above embodiment will be explained.
まず、はんだ接続部１２上に可撓性シート１７を正確に
位置決めして載置する。ついで、半導体チップ９を位置
決めした状態で可撓性シート１７を介してはんだ接続部
１２上にフェースダウンする。さらに、半導体チップ９
の背面部及びキャップ１４の封止部（側壁下部の空間）
に背面はんだ１５及び封止部はんだ１６を介在させた状
態で、図示のようにキャップ１４を覆蓋する。ついで、
キャップ１４の上面を押下（すなわち、半導体チップ９
及び基板１１を押圧）する荷重を印加しながら設置雰囲
気を加熱し、背面はんだ１５及び封止部はんだ１６を溶
融させ、その介在面の両側の部材をはんだ固定し、半導
体チップ９の周囲を密封する。同時に、はんだバンプ１
０及びはんだ接続部１２が可撓性シー）１７の導体配線
の電極部に溶着し、基板１１のパターンとはんだバンプ
１０とが電気的に接続される。First, the flexible sheet 17 is accurately positioned and placed on the solder connection portion 12 . Then, with the semiconductor chip 9 positioned, it is placed face down onto the solder connection portion 12 via the flexible sheet 17. Furthermore, the semiconductor chip 9
The back part of the cap 14 and the sealing part of the cap 14 (the space at the bottom of the side wall)
As shown in the figure, the cap 14 is covered with the back surface solder 15 and the sealing portion solder 16 interposed therebetween. Then,
Press down on the top surface of the cap 14 (i.e., press down on the top surface of the cap 14 (i.e.,
The installation atmosphere is heated while applying a load (pressing the substrate 11), melting the backside solder 15 and the sealing portion solder 16, fixing the members on both sides of the intervening surface with solder, and sealing the periphery of the semiconductor chip 9. do. At the same time, solder bump 1
0 and the solder connection portion 12 are welded to the electrode portion of the conductor wiring of the flexible sheet 17, and the pattern on the substrate 11 and the solder bump 10 are electrically connected.
このとき、はんだバンプｌＯとはんだ接続部１２の位置
がずれているため、はんだバンプ１０がはんだ接続部１
２を直接的に押圧することは無い。At this time, since the positions of the solder bump lO and the solder connection part 12 are shifted, the solder bump 10 is
2 is not pressed directly.
この場合、可撓性シート１７は、はんだバンプｌＯ及び
はんだ接続部１２の各々によって、互いに逆方向に押圧
されるため、可撓性シート１７に凹凸が生じる。したが
って、可撓性シート１７上の導体配線の電極部が、押圧
時においても、はんだバンプ１０及びはんだ接続部１２
の各々からずれないように予め配慮したパターン形成が
要求される。In this case, the flexible sheet 17 is pressed in opposite directions by each of the solder bumps 10 and the solder connections 12, so that unevenness occurs on the flexible sheet 17. Therefore, even when the electrode portion of the conductor wiring on the flexible sheet 17 is pressed, the solder bump 10 and the solder connection portion 12
It is required to form a pattern with consideration in advance so as not to deviate from each of the above.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。Above, the invention made by the present inventor has been specifically explained based on Examples, but it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. stomach.
例えば、可撓性シート１７には、はんだ接続用の導体配
線を設けるものとしたが、更に、可撓性シート１７にコ
ンデンサ、抵抗などの電子部品を搭載し、ハイブリッド
ＩＣを構成するようにしてもよい。For example, the flexible sheet 17 is provided with conductor wiring for solder connection, but it is also possible to mount electronic components such as capacitors and resistors on the flexible sheet 17 to configure a hybrid IC. Good too.
さらに、可撓性シート１７には、半導体チップ９の電気
的特性を検査するための導体配線及び電極部を設けるこ
ともできる。このようにすれば、キャップ１４を接続す
る前に半導体チップ９を可撓性シート１７を介して基板
１１に仮止めし、この状態で完成前の動作チエツクを行
うことができる。この結果、工程の短縮化や完成時間の
短縮などを図ることができる。Further, the flexible sheet 17 may be provided with conductor wiring and electrode portions for testing the electrical characteristics of the semiconductor chip 9. In this way, before connecting the cap 14, the semiconductor chip 9 is temporarily fixed to the substrate 11 via the flexible sheet 17, and in this state, the operation before completion can be checked. As a result, it is possible to shorten the process and shorten the completion time.
本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば、下記の通りであ
る。Among the inventions disclosed in this application, the effects obtained by typical ones are as follows.
すなわち、多層配線が形成された基板に、はんだバンプ
を接続面に備えた半導体チップをはんだ接続すると共に
前記半導体チップを覆う如くにしてキャップを配設し、
その内面を前記半導体チップの放熱面にはんだ接続する
と共に封止部を前記基板にはんだ接続する半導体装置の
封止構造であって、前記基板と前記はんだバンプの間に
可撓性シートを配設するようにしたので、はんだバンプ
は機械的な応力を受けず、変形、損傷、バンプ間短絡な
どを生じることがない。したがって、製品歩留りを向上
させることができる。That is, a semiconductor chip having solder bumps on the connection surface is connected by solder to a substrate on which multilayer wiring is formed, and a cap is provided to cover the semiconductor chip,
A sealing structure for a semiconductor device in which an inner surface of the semiconductor chip is solder-connected to a heat dissipating surface of the semiconductor chip and a sealing portion is solder-connected to the substrate, wherein a flexible sheet is disposed between the substrate and the solder bumps. As a result, the solder bumps are not subjected to mechanical stress, and no deformation, damage, short circuit between bumps, etc. occur. Therefore, product yield can be improved.
また、可撓性シートをはんだ接続以外の用途にも利用で
きるので、製品の応用化及び工程の短縮化などを図るこ
とができる。Further, since the flexible sheet can be used for purposes other than solder connections, it is possible to apply the product and shorten the process.
第１図は本発明による半導体装置の一実施例を示す断面
図、
第２図はＦＴＣによる半導体装置の一例を示す断面図で
ある。
１・・・チップ、２・・・ＴＡＢリード、３・・・シリ
コンラバ・−４・・・基板、５・・・ソルダバンプ、６
・・・キャップ、７・・・シーム溶接、８・・・グイ接
着、９・・・半導体チップ、ｌＯ・・・はんだバンプ、
１１・・・基板、１２・・・はんだ接続部、１３・・・
薄膜多層膜、１４・・・キャップ、１５・・・背面はん
だ、１６・・・封止部はんだ、１７・・・可撓性シート
。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view showing an example of a semiconductor device using FTC. DESCRIPTION OF SYMBOLS 1...Chip, 2...TAB lead, 3...Silicon rubber-4...Substrate, 5...Solder bump, 6
... Cap, 7... Seam welding, 8... Gui adhesive, 9... Semiconductor chip, IO... Solder bump,
11... Board, 12... Solder connection part, 13...
Thin film multilayer film, 14... Cap, 15... Back solder, 16... Sealing portion solder, 17... Flexible sheet.
Claims (1)
面に備えた半導体チップをはんだ接続すると共に前記半
導体チップを覆う如くにしてキャップを配設し、その内
面を前記半導体チップの放熱面にはんだ接続すると共に
封止部を前記基板にはんだ接続する半導体装置の封止構
造であって、前記基板と前記はんだバンプの間に可撓性
シートを配設したことを特徴とする半導体装置。 ２、可撓性シートが、低熱膨張ポリイミドであることを
特徴とする請求項１記載の半導体装置。 ３、前記はんだバンプと前記基板上の接続部とが、接続
方向に対し偏心していることを特徴とする請求項１記載
の半導体装置。 ４、前記可撓性シートは、電子部品を搭載していること
を特徴とする請求項１記載の半導体装置。 ５、前記可撓性シートは、前記半導体チップの電気特性
を検査するための配線及び電極部を有していることを特
徴とする請求項１記載の半導体装置。[Claims] 1. A semiconductor chip having solder bumps on the connection surface is soldered to a substrate on which multilayer wiring is formed, and a cap is provided so as to cover the semiconductor chip, and the inner surface of the cap is covered with the semiconductor chip. A sealing structure for a semiconductor device in which a heat dissipating surface of a semiconductor chip is soldered and a sealing part is soldered to the substrate, characterized in that a flexible sheet is disposed between the substrate and the solder bumps. semiconductor device. 2. The semiconductor device according to claim 1, wherein the flexible sheet is made of low thermal expansion polyimide. 3. The semiconductor device according to claim 1, wherein the solder bump and the connection portion on the substrate are eccentric with respect to the connection direction. 4. The semiconductor device according to claim 1, wherein the flexible sheet has electronic components mounted thereon. 5. The semiconductor device according to claim 1, wherein the flexible sheet has wiring and electrode portions for testing electrical characteristics of the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006660A JPH03211735A (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006660A JPH03211735A (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03211735A true JPH03211735A (en) | 1991-09-17 |
Family
ID=11644537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006660A Pending JPH03211735A (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03211735A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6887777B2 (en) | 2002-07-24 | 2005-05-03 | Infineon Technologies Ag | Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement |
-
1990
- 1990-01-16 JP JP2006660A patent/JPH03211735A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6887777B2 (en) | 2002-07-24 | 2005-05-03 | Infineon Technologies Ag | Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5561323A (en) | Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
| US5773884A (en) | Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
| US5633533A (en) | Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
| US6165817A (en) | Method of bonding a flexible polymer tape to a substrate to reduce stresses on the electrical connections | |
| US6208025B1 (en) | Microelectronic component with rigid interposer | |
| US6461890B1 (en) | Structure of semiconductor chip suitable for chip-on-board system and methods of fabricating and mounting the same | |
| JPH0550134B2 (en) | ||
| JP2003133518A (en) | Semiconductor module | |
| JP3565090B2 (en) | Method for manufacturing semiconductor device | |
| US20050287703A1 (en) | Multi-chip semiconductor connector assembly method | |
| TW396467B (en) | Semiconductor device | |
| JPH08241940A (en) | Semiconductor device and its manufacture | |
| US7094966B2 (en) | Packaging integrated circuits with adhesive posts | |
| JP2002319781A (en) | Electronic part mounting module | |
| JPH03211735A (en) | Semiconductor device | |
| JP2000164792A (en) | Semiconductor device and manufacture thereof | |
| JP2748771B2 (en) | Film carrier semiconductor device and method of manufacturing the same | |
| JPH0236556A (en) | Pin grid array and mounting of semiconductor element | |
| TW541673B (en) | Semiconductor device formed by mounting semiconductor chip on support substrate, and the support substrate | |
| EP1317001A1 (en) | A semiconductor device | |
| JPS5848932A (en) | Preparation of semiconductor device | |
| JP3714127B2 (en) | Manufacturing method of semiconductor device | |
| JPH08181168A (en) | Semiconductor device | |
| JP2004247347A (en) | Semiconductor device and its manufacturing method | |
| JP2504262Y2 (en) | Semiconductor module |