JPH03211640A - Memory control system - Google Patents

Abstract

PURPOSE:To attain access to dictionary ROM at high speed without reducing a memory space which a user can use by switching highest ROM in the memory space at a protection address mode and dictionary ROM which is allocated in parallel to the ROM so as to attain access. CONSTITUTION:Bank numbers are allocated to the memory bank of dictionary ROM 13 and ROM 12 in the memory space at the protection address mode, and CPU 11 sets bank selection information to a bank register 17 based on the bank numbers. An address decoding part 32 decodes bank selection information and address information which CPU 11 outputs, and outputs a ROM selection signal 30 or 31. Thus, dictionary ROM 13 can be allocated to the memory space without reducing the memory area which the user can use. Thus, the capacity of dictionary ROM 13 is enlarged and high speed access is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access method suitable for a handheld information processing apparatus such as a personal combination, a computer, a word processor, and the like.

[Conventional technology]

In general, in order to handle Japanese data on a personal computer (hereinafter referred to as a personal computer), etc., it is necessary to use kanji CG and Japanese input W# to display Japanese 7 onts.
It is necessary to have elements such as a conversion dictionary for performing kana-kanji conversion.

Hereinafter, the conversion dictionary will be described.

When using a conversion dictionary on a personal computer, due to its large capacity, it is rarely allocated directly to memory space, but is often used by relegating it to a storage device such as a floppy disk or hard disk. many.

However, in recent years, there has been a strong demand for more efficient and faster Japanese input on computers, etc. Therefore, the capacity of conversion dictionaries has increased and the contents have been stored in memory. There is a growing demand for high-speed access.

By the way, if we take as an example the CPU8084 made by Intel Corporation in the United States, which is widely used in personal computers, its memory space is 1
It is M bytes (Kai = 2), and within that limited space,
It is necessary to allocate ROM, RAM, display memory, etc. 80284,5 which is the upper CPU of 8086
For $4,1486, etc., the memory space is t16M bytes ~
It has an operation mode called Hounagi address mode, which is expanded to 4 GB (G:2)K.

However, even in systems using these CPUs, 808
It is normal to allocate a memory map based on the same 1M byte memory as 6.

[Problem to be solved by the invention]

The above conventional technology has the following problems regarding the conversion dictionary.

That is, when the conversion dictionary files are stored and used on 70 disks, there is a problem that the capacity is limited and it becomes impossible to cope with an increase in the capacity of the conversion dictionary.

Further, if a hard disk device is used, it is possible to cope with an increase in capacity, but there is a problem that the device is expensive and is not widely used.

Furthermore, when using either a 74TB disk or a hard disk, since they are external storage devices, there is a problem that the access speed is slow.

Therefore, for high-speed access, it is effective to allocate the conversion dictionary to memory space.

When designing a burner converter with Japanese input in mind from the beginning, the specifications should be determined so that the aforementioned kanji CG, conversion dictionary, etc. can be placed efficiently in the memory space.

However, when a personal computer that is not designed for Japanese input, such as a personal computer commonly used in English-speaking countries, is enabled to input Japanese, the following problems arise.

Figure 5 shows the AS in English-speaking countries using 80284 as the CPU.
An example of the memory map of a commonly used personal computer is shown below.

In Figure 5, 1 is a standard RAM area with a capacity of 640x bytes, 2 is a video RAM with a size of 128 bytes and is used as display memory, and is is an I10 adapter ROM area with a size of 128 bytes. , 4 has a size of 441 bytes and is a system reserved area (a) reserved for use by the system, 5 is a BIO8-ROM (al) with a size of 64 bytes, and 6 is the topmost memory space. The IIO8-ROM(a) has the same contents as 5. The OB10g-ROM(b),9 is an extended RAM area having a maximum size of 15 bytes.

The memory space in the real address mode such as the above-mentioned 80286 is 1M byte from 00000 (IIE1 address to FFFFF(H) address, of which @ quasi-RAM area 1
06401 bytes is the area available to the user.

Further, the area above address 100000 (H) is normally accessible only when operating in the protected address mode. However, when resetting 80286 etc.,
While p in real address mode, the topmost memory space (
Execution starts from FFFFFO@address). Therefore, the BIO8-RO that stores the initialization program in this area
It is necessary to allocate M(b)6.

When allocating a conversion dictionary to the memory space shown in FIG. 5, there are the following problems.

First, we will start with Needa's application cage program (hereinafter referred to as A).
It is called P. ), there is a problem in that the standard RAM area 1 that can be used by the AP is reduced.

In addition, other areas of the memory space, such as the X10 adapter ROM area 3 and the system reserved area (&) 4, are allocated to the area used by the system. There is a risk of conflict with the memory element.

In addition, when using the extended RAM area 9KfilJ, R
There is a problem in that the maximum expansion capacity of AM is limited.

Also, for example, video RAM2 or BIO8-RO
There is also a method in which a conversion dictionary is assigned to the same address as Mk) 5, and these are used by switching.

Regarding this type of method, JP-A-60-17
If the system described in the 6088 publication is used, there is no need to reduce the standard RAM area 1 available to the user, but when switching to video RAM 2, the video RAM area
Simultaneous access to M2 and conversion word 1 becomes impossible, and B
When switching to IOS-ROM(a)5, BIO
Since the 8-ROM-) 5 cannot be seen, there are problems such as the risk of the system going out of control.

As described above, in the above-mentioned conventional technology, when an attempt is made to allocate a conversion dictionary to memory space in order to achieve high-speed access, there is a problem in that the memory area available to the user decreases.

Therefore, if the conversion dictionary is stored in a 7CI disk or the like so as not to reduce the usable memory area of the computer, there are problems in that the access time becomes slow and the capacity of the conversion dictionary is limited.

Also, to avoid reducing the user's usable memory area, if you switch with other devices on the memory,
There are problems such as memory map incompatibility.

Specifically, an object of the present invention is to provide a memory control method that allows high-speed access to a conversion dictionary without reducing the usable memory space of the processor.

In this specification, the conversion dictionary is described throughout, but the present invention is not limited to this, and can be similarly applied to a series of data that is desired to be accessed at high speed.

[Means to solve the problem]

By the way, as mentioned above, CPUs such as 80286 and 386.14B6 operate in real address mode at reset, but since execution starts from the highest address, systems using these CPUs generally To,
4 ROMt at the top between memory 9 in protected address mode
- Assign p.

However, the contents of the ROM are the same as those allocated to the memory space in the real address mode, and once the real address mode O memory space &'C line is moved, the ROM in this area It will never be accessed.

The present invention focuses on this point, and provides a Cable Cable Cable Controller that has at least 42 operating modes, including a real address mode and a protected address mode.
In an information processing device using Pt1, the ROM @2 is placed in the topmost memory space RO1l in protected address mode.
#C In parallel, the uppermost ROM between the memory vg in the protected address mode and the second ROM allocated in parallel to this are allocated on the back side, so to speak, and based on the ROM selection information outputted from the CPU as well. Access is made by switching between the ROM and the ROM.

Therefore, the topmost OROMKM row of the memory space in the protected address mode is allocated to the ninth RO tomb as the dictionary ROM.
By doing so, the dictionary ROM can be allocated to the memory space.

Furthermore, if the information stored such as dictionary information is larger than the ROM capacity of the memory space in the protected address mode, and the capacity of the second ROM exceeds the ROM capacity of the memory space in the protected address mode, uses a bank memory access method to divide the second ROM into a plurality of memory banks, and based on the bank selection information and address information output by the CPU, the ROM in the memory space in the protected address mode and the above The second ROM is switched and accessed.

To this end, for example, a bank register that stores the bank selection information and a decoder that decodes the bank information stored in the bank register and the address information output by the CPU are provided, and the decoder, based on the decoding result, R of the memory space in the above protected address mode
A ROM selection signal for switching between the OM and the second ROM may be output.

An example of a device related to the bank memory access method is Japanese Patent Application Laid-Open No. 105744/1983.

Further, when resetting the CPυ, it is preferable that the memory space OR0M in the protected address mode is selected.

[Effect]

The present invention focuses on the operation of a CPU such as 80284.586.1484 after being reset, and allocates a dictionary ROM to the memory space without reducing the memory space available to the user.

For example, in the 80284, the address generation method in the dark address mode is address = segment register Therefore, after the 80286 is reset,
Execution starts from address FFFFFO(H).

With the initial value of the segment register above, the address that can be generated using the above address generation method is FF0OOOO(
There are 641 bytes from address H) to FFFFFF(H) address 1. Generally, ROM is allocated to this area as well. However, the contents of the ROM are the same as those allocated to the memory space in real address mode, and once a branch instruction is executed, as long as the ROM is operating in real address mode, the upper segment registers above are Since the 4 bits are always 0, the ROM is never used.

Therefore, in this issue, for example, the ROM and KRO between the dictionary ROM and the memory 9 in the protected address mode are
The CPU may output the ROM selection information and switch the ROM based on the ROM number.

In addition, in the bank memory access method, a bank number is assigned to the memory bank of the dictionary ROM and the ROM of the memory space of the protected address mode, and the CPU
The bank selection information may be set in the bank register based on the bank number.

The decoder decodes the bank selection information set in the bank register and the address information output by the CPU, and outputs an RO selection signal. Some F
F0OOOQl[) ~ FFFFFF (If the bank selection information set in the bank register above is 0 in W# where the address of address H1 is output, ROM selection is performed for the ROMK in the memory space in the protected address mode. If the bank selection information is other than 0, the circuit may be configured to send a ROM selection signal to the dictionary ROMK.

Furthermore, when resetting the system, the ROM selection information is output to select the ROM in the memory space in the protected address mode, or in the memory bank access method, the bank register is reset and the bank selection information is output. If set to O, the ROM in the memory space in the protected address mode will be selected, so the system will not malfunction.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows the memory map of a Japanese language processing system that uses the CPt1K80284 and is capable of inputting Japanese on a PC commonly used in English-speaking countries.
K shows the configuration of the system.

In Figure 1, 6 is a BrO3-ROM (b) placed at the top of the memory space in protected address mode, has a capacity of 64 bytes, and has a bank number of 0 (b), and 7 is a dictionary with a capacity of 1M bytes. ROM 8 divides the dictionary ROM 7 into 16 banks with a size of 64 bytes, each with 1 bank.
This is dictionary ROM bank number 1 with bank numbers of ~16.

Figure 2 K>, 11 is CPo, 12 is BrO5-ROM with a capacity of 641 bytes, 1S is a dictionary ROM with a capacity of 1M bytes, 14 is a reset switch, 17 is C
A bank register that outputs the bank selection information written by PtJl 1 through the data bus 24 to the bank address bus 25, 22 is a CPυ address bus, 25 is a reset signal, 26 is an I10 write signal, and 50 is sent by the address decoder 52. Bi12-ROM selection signal, 51
is a dictionary ROM selection signal sent by the address decoding section 32.

In the address decoding unit 52, 15 is a 1M address decoder that decodes the upper 8 bits of the CPU address bus 22, 6 to A□ and sends out a 1-digit decode signal 27, and 16 is a 1M address decoder that decodes the upper 8 bits of the CPU address bus 22. Pitutom,
6~mu2. The 14M address decoder 18 decodes the bank selection information output from the bank register 17 and sends out the 16M6 iris decode signal 8.
a bank address decoder 19 for sending out a switching signal 29;
is the BrO8-OR gate which sends out the ROM selection signal 50), 20 is mt which sends out the 14MB BrO8 selection signal 55, &
AHD Goo) (b), 21 is the dictionary ROM selection signal 51
1 is sent out^ND gate (o).

Next, the operation of this embodiment will be explained.

When the CPU 11 in FIG. 2 operates in the real address mode, the CPU 11 in FIG.
Only 0FFFFF (H) address tf01M bytes can be accessed from address 00@).

02 port 11 operates in real address mode, and the BI in Figure 1
When accessing the O$-ROM (a) 5, the CPU 11 outputs 24-bit address signals A0 to M□ to the CPU address 22 in FIG. Bit A, 4
~'2M is decoded and 1 irises decoded signal 27 is sent out, and gate (a) 1? sends out the Bi12-ROM selection signal 50.

BrO8-ROM12 is the lower 16 bits A of the CPU address bus 22. ～M, S is taken as an address,
By the BrO8-ROM selection signal 50, the data bus 2
Output the data to 4.

In the memory map shown in FIG. 1, when accessing the upper address tube from the address 100,000, it is necessary to operate the CPU 11 in FIG. 2 in the protected address mode.

When the CPU 11 is operated in the protected address mode and the dictionary ROM bank 1 and 8 in FIG. 1 is accessed, the Crtill #i and bank number 1 in FIG. 2 are output to the data bus 24 as bank selection information. Furthermore, from I10 write signal 24fC.

The lower 8 bits D0 to D7 of the data bus 24 are written to the bank register 17. The bank register 17 transfers the written bank selection information to the bank address A11. ~MuN
m" and outputs it to the bank address bus 23.

Therefore, in the address decoding section 32, the bank address decoder 18 decodes that the dictionary ROMIS is selected, and the ROM switching signal 2? Send out.

Furthermore, the CPU 11 has the BIOs-ic in FIG.
The address of OM(b)4 is output to the CPU address bus 22. The 16M address decoder 16 decodes the upper 8 bits A14 to M□ of the CPU address bus 22, and sends out a 16M6 address decode signal 8. AND game 11
0) 21 is 110M switching signal 2? A dictionary ROM selection signal s1 is sent from the 14M4 irises decode signal 8. The dictionary ROMI S is the lower 16 of the CPU address bus 22.
A total of 24 bits, including bits A0 to M, 5 and 8 bits A1, 6 to 5B2M of the bank address bus 2s, are input as an address, and data is output according to the dictionary ROM selection signal 51.

Further, when the system is reset, the reset switch 14 in FIG. 2 sends out a reset signal 25 to clear the bank register 17.

At this time, the same condition as when bank number a was set in bank register 17 is set to 1, and the user requests 1st! ! ! BiO2-ROM in II (N6 accessible system,
Post-reset processing can be performed.

In actual operation, when CPt111 is 80284, immediately after reset, execution starts from address FFFFFO@, so BiO2-ROM (b) 6 is used, and execution moves to the real address mode memory space after -1. B.
I OS-ROkl (a) 5 f usage, dictionary ROMJ
When accessing %3, you can use software to switch the CPU 11 to operate in protected address mode.
86 and 1486 virtual 86 modes, etc.
Bank switching may be performed using the function 110 of 11.

This embodiment is not limited to the above-described example. For example, the CPDll is not 80284 but 584 or 14
86 or BiO2-ROM-)5 and BiO
2-ROM (b) 6a, Tsuretsure, 64 is set as a byte, but s2 may be set as 14 of the bytes, or may be set as 128.

In addition, the size of the dictionary ROM 40 is 1M byte, and 9.
It may be 2M bytes or 4M bytes, or it may be 256 out of 512 bytes.

In addition, although the explanation was made using a dictionary ROM that stores a conversion dictionary, a kanji CG-ROM that stores 7-ont information of kanji
may be similarly allocated.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to allocate more dictionary ROMs to the memory space without reducing the memory area available to the user, so it is possible to expand the capacity of the dictionary ROM and achieve high-speed access. Moreover, it has the effect of improving the conversion efficiency of kana-kanji conversion in a Japanese processing system and enabling high-speed conversion.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram showing a memory map in one embodiment of the present invention, Fig. 2 is a block diagram showing the configuration of a system to which this embodiment is applied, and Fig. 5 is a system widely used in English-speaking countries. FIG. 2 is an explanatory diagram showing a personal combination controller O memory map. Explanation of symbols 1...mark*RAM area, 2...video RAM. 3...I10 adapter ROM area, 4...
...System reserved area-), 5. ,,-BiO
2-ROM(a), 6...BiO2-ROM(
b), 7-------Dictionary ROM. 8...Dictionary ROM bank number 1, 11...
-cpu. 12...BiO2-ROM, 15...
...Dictionary ROM, 14-----Reset switch, 15...1M address decoder, 1
6...-16M address decoder, 17...
... Bank register, 18 ... Bank address decoder, 22 ... CPU address bus, 23 ... Bank address bus, 24.
...Data bus% 25 ...Reset signal, 26 ...Ilo 5 itte signal, 2
9------- ROM switching signal, 50...----
BiO2-ROM selection signal, S1-...Dictionary R
OM selection signal, 52...address decoding section.

Claims (1)

[Claims] 1. An information processing device comprising a CPU having at least two operating modes, a real address mode and a protected address mode, and a first ROM allocated to the top of the memory space of the CPU. Allocating a second ROM to the same address as the first ROM, and accessing by switching between the first ROM and the second ROM based on ROM selection information output from the CPU. A memory control method featuring: 2. In an information processing device comprising a CPU having at least two operating modes, a real address mode and a protected address mode, and a first ROM allocated to the top of the memory space of the CPU, a plurality of memory banks are provided. each memory bank is set to be assignable to the same address as the first ROM, and each memory bank is set to be assignable to the same address as the first ROM, and based on the bank selection information and address information output by the CPU,
and a selected memory bank of the second ROM. 3. The memory control system according to claim 1 or 2, wherein dictionary information is stored in the second ROM. 4. The memory control system according to claim 1 or 2, wherein the second ROM stores a character pattern. 5. Using the memory control method according to claim 3 or 4,
An information processing device equipped with a Japanese language processing system that performs kana-kanji conversion. 6. Claims 1 and 2, characterized in that after resetting the CPU, switching is made to select the first ROM.
Memory control method according to item 3 or 4, or claim 5
The information processing device described.