JPH03211617A - Block or circuit and shift system - Google Patents

Abstract

PURPOSE:To reduce a hardware quantity by generating a shift circuit obtaining the total OR of bits, which are to be omitted by means of shift, in parallel to a right shift operation which is stepwise executed. CONSTITUTION:A first block OR circuit 130 obtains the first intermediate total OR 133 of the bits omitted by a first shift circuit 150 in accordance with the higher two bits 113 of a shift quantity 102. A second OR circuit 131 obtains the second intermediate total OR 134 of the bits omitted by the first and second shift circuits 150 and 151 in accordance with the medium bits 114 of the shift quantity 102. A third block OR circuit 132 obtains the total OR 104 of the bits omitted by the first to third shift circuits 150-152 in accordance with the low order two bits 115 of the shift quantity 102. Thus, the right shift circuit can be realized by a small quantity of hardware.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a shift method that performs the 2G shift required when performing floating point addition and simultaneously calculates the total OR of the numbers truncated by the shift. This relates to an OR circuit used for this purpose.

('Prior art 2) FIG. 3 shows a 64-bit right shift circuit diagram as an example of this type of conventional shift method.

The first shift circuit 310 is a circuit that shifts 0.1.2.3 bits of 64-bit input data 301 according to the lower two hits 303 of the 6-bit shift amount 302, and the second shift circuit 311 is According to the middle two hits 304 of the shift amount 302, 0.4.8.1 of the input category 301
The third shift circuit 312, which is a circuit that performs a 2-bit shift, is a circuit that performs a 0.16.32.48-bit shift of the input data 301 according to the upper 2 bits 305 of the shift amount 302.

In order to obtain the total OR of the bits discarded by the shift using the conventional right shift circuit as shown in 2, first find all the bits discarded by the shift, and then add the OR to the OR gate 320. I try to take it with.

(Problems to be Solved by the Invention) In the conventional shift method described above, all the bits discarded by the shift are determined and then the logical sum is performed, which not only increases the amount of hardware but also slows down the speed. There is a problem.

The purpose of the present invention is to create a block block that significantly reduces the amount of hardware compared to the conventional method by creating a shift circuit that calculates the total OR of the bits to be truncated by the shift in parallel with the stepwise right shift operation. The purpose of this invention is to provide an OR circuit and a shift method.

[Means to solve the problem]

The block OR circuit of the present invention includes a first inverter that receives the lower bits of a 2-bit shift amount and outputs its inverted signal, and a second inverter that receives the upper bits of the shift amount and outputs its inverted signal. an inverter; and a first AN that receives the upper bits and the lower bits as inputs.
a D gate, a second AND gate whose inputs are the upper bits of the shift amount and the output of the first inverter, and a third AND gate whose inputs are the output of the second inverter and the lower bits.
an AND gate, an output of the second inverter and the first
a fourth AND gate whose input is the output of the inverter; a first OR gate whose input is the 1.2.3.4 input data; a second OR gate whose input is the 1.2.3 input data; 1. A third OR gate that receives the second input data as input; a fifth AND gate that receives the outputs of the first AND gate and the first OR gate as input; and a fifth AND gate that receives the outputs of the second AND gate and the second OR gate as inputs. 6 AND gate, a 7th AND gate that receives the outputs of the third AND gate and the third OR gate, an 8th AND gate that receives the output of the fourth AND gate and the first input data, and the 5th to 8th AND gates. Take the output of the gate as input,
and a fourth OR gate that outputs a logical sum signal.

In addition, the shift method of the present invention is a shift method that can calculate the total OR of the bits discarded by the shift, and in parallel with the shift operation performed in stages, the intermediate OR of the discarded bits is calculated as described above. It is characterized by being created using a block OR circuit.

[Effect]

In the conventional shift method, when trying to calculate the total OR of the bits truncated by the shift, a shift result with the same number of bits as the sum of the number of bits of the output data and the maximum shift amount is calculated, and the bits truncated by the shift are calculated. It was necessary to find the total disjunction of .

By using the block OR circuit of the present invention, the number of bits of the shift circuit in each stage is the same as the number of output bits, and the total OR is also calculated in parallel with the shift operation, so it can be calculated at high speed. .

〔Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the block OR circuit of the present invention.

The block OR circuit in this figure has a 2-bit shift amount A. ,
A first inverter 210 that receives the lower bit 201 of A1 and outputs its inverted signal, and a 2-bit shift amount A.
a second inverter 211 which receives the upper bit 202 of o, A and outputs an inverted signal thereof; and a shift amount A. , A1's upper bits 202 and shift amount A.

, a second AND gate 221 whose input is the lower bit 201 of AI, the upper bit 202 and the first inverter 210.
A second AND gate 221 receives the output of the second inverter 211 and the lower bit 201 as inputs, a third AND gate 222 receives the output of the second inverter 211 and the lower bit 201 as inputs, and a third AND gate 222 receives the output of the second inverter 211 and the output of the first inverter 210 as inputs. 4AN
D gate 223 and t, 2, 3.4 input data 204.205206.2
A first OR gate 230 that receives 07 as an input, and a second OR gate 2 that receives 1.2.3 input data as an input.
31, and a third OR gate 232 which receives the first and second input data as input.
and a fifth AND gate 224 whose inputs are the outputs of the first AND gate 220 and the first OR gate 230;
A sixth AND gate 225 whose inputs are the outputs of the D gate 221 and the second OR gate 231, and a third AND gate 22.
2 and the output of the third OR gate 232 as inputs.
D gate 226, and an eighth AND gate 22 which receives the output of the fourth AND gate 223 and the first input data 204 as inputs.
7 and the outputs of the fifth to eighth AND gates 224 to 227 as inputs, and outputs a logical OR signal)-233
It consists of

This block OR circuit calculates in advance the bitwise OR that may be truncated by shifting, and sequentially calculates the 4th and 3rd bits of the block OR circuit from the highest order.
．． 2 data input 207.206205. In addition, the output of the block OR circuit on the first stage is input to the first data input 2.
04, and the total OR of the bits truncated for each stage is calculated according to the shift amount (2 and t).

FIG. 2 is a circuit diagram of a 64-bit barrel right shifter which is an embodiment of the shift method of the present invention using the above-described block OR circuit.

First, the method for obtaining shift data will be described.

In this figure, the shift amount 102 is given by 6 bits,
Specifies that 64-bit input data 101 is shifted by 0 to 63 bits. The output is 64 bits of output data 103 and the total logic phase 104 of the bits truncated by the shift.

The first shift circuit 150 is a circuit that shifts the input data 101 by any one of 0116, 32, and 48 bits according to the upper two bits 110 of the shift amount 102.
1. with bi-soto output. Similarly, the second shift circuit 151
is 0 according to the middle two bits 111 of the shift amount 102.
．． 4.8.12 Only input data 101
This is a circuit that shifts the . The third shift circuit 152 outputs 0.1 to 0.1 according to the lower two bits 112 of the shift amount 102.
This circuit shifts input data 101 by either 2.3 bits.

Next, a method for calculating the total OR 104 of the bits to be truncated will be described.

The first shift circuit 150 is a circuit that shifts the input data 101 by any one of 0.16, 32, and 48 bits,
Before shifting the input data 101, the 17th to 32nd bits (i16), the 33rd to 48th bits (117), and the 49th to
6th 1.2.3 OR where the logical sum of 64 (118) bits is calculated by the 1.2.3 OR circuits 120 to 122
The outputs of the circuits 120 to 122 are sent to the first block OR circuit 1.
30 and calculates the first intermediate total logic phase 133 of the bits to be discarded by the first shift circuit 150 according to the upper two bits 113 of the shift amount. Since the first block OR circuit 1.30 does not have anything equivalent to the previous block OR circuit, the first data input line 142 is grounded.

The second shift circuit 151 is a circuit that shifts the input data 101 by one of 20.4.8.12 hits, and before shifting the input data 101, the first intermediate shift signal 14
The logical sum of the 53rd to 56th bits (126>, 57th to 60th bits (127), and 61st to 64th bits <128> of 0 is determined by the 4.5.6 OR circuits 123 to 125.4. The outputs of the 5.6 OR circuits 123 to 125 are input to the second block OR circuit 131, and according to the middle two bits 114 of the shift amount, the outputs of the 1.2 shift circuits 150.
A second intermediate total OR 134 of the bits truncated by 151 is determined. A first intermediate logic phase signal 133, which is an output of the first block OR circuit 130 at the previous stage, is connected to the first input of the second block OR circuit 131.

The third shift circuit 152 is a circuit that shifts the input data 101 by any one of 0, 1, 2, and 3 bits.
62nd bit (126), 63 of intermediate shift signal 141
Bits (127) to 64 bits (128>) are input to the third block logic phase circuit 132, and according to the lower two bits 115 of the shift amount, the first, second and third shift circuits 150 and 15 are input.
Total OR of bits truncated by 1°152 1
Find 04. This total OR 104 corresponds to the total OR of bits that are discarded by the shift circuit. A second intermediate OR signal 134, which is the output of the second block logic phase circuit 131 at the previous stage, is connected to the first input of the third block logic sum circuit 132.

〔Effect of the invention〕

As described above, according to the present invention, a right shift circuit can be realized with a smaller amount of hardware than in the past.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an embodiment of the block OR circuit of the present invention, Figure 2 is a block diagram showing an embodiment of a 64-bit barrel right shifter using the block OR circuit of the present invention, and Figure 3 is a block diagram of a conventional right shifter. FIG. 2 is a block diagram of a shifter. 120 to 125...first to sixth OR circuits, 230 to 2
33... 1st to 4th OR gates, 220 to 227...
・1st to 8th AND gates, 320... Total OR gate, 210.211... Inverter, 150° 310
...First shift circuit, 151,311...Second shift circuit, 152,312...Second shift circuit, 130
~132...First to third block OR circuits.

Claims (1)

[Scope of Claims] A first inverter that receives the lower bits of a 1-bit or 2-bit shift amount and outputs its inverted signal; and a second inverter that receives the upper bits of the shift amount and outputs its inverted signal. and a first AN that receives the upper bits and the lower bits as inputs.
a D gate, a second AND gate whose inputs are the upper bit and the output of the first inverter, a third AND gate whose inputs are the output of the second inverter and the lower bit, and the output of the second inverter and the a fourth AND gate that receives the output of the first inverter; a first OR gate that receives the first, second, third, and fourth input data; and a second OR gate that receives the first, second, and third input data. , a third OR gate that receives the first and second input data as input; a fifth AND gate that receives the outputs of the first AND gate and the first OR gate; and a fifth AND gate that receives the outputs of the second AND gate and the second OR gate as inputs. a seventh AND gate whose inputs are the outputs of the third AND gate and the third OR gate; an eighth AND gate whose inputs are the output of the fourth AND gate and the first input data; ~8AND gate output as input,
A block OR circuit comprising a fourth OR gate that outputs a OR signal. 2. In a shift method that can obtain the total OR of the bits that have been discarded by shifting, the block of claim 1 calculates the intermediate OR of the discarded bits in parallel with the shift operation that is performed in stages. A shift method created by an OR circuit.