JPH0321063Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to an improvement of the mute circuit in FM receivers and the like.

A conventional mute circuit will be explained with reference to FIG. A signal input terminal 1 is connected to the drain of a field effect transistor 3 via a capacitor 2 . Output terminal 4 is connected to the source of field effect transistor 3 via capacitor 5 . These drains and sources are connected to a power supply 8 by bias resistors 6 and 7 and to ground by bias resistors 9 and 10, respectively, and are supplied with a bias voltage. The miute terminal 11 is connected to the gate of the field effect transistor 3 via a resistor 12. Furthermore, the gate has a resistor 13 and a capacitor 1
4 are connected in parallel and grounded.

The operation of this circuit is as follows. That is, the source and drain bias voltages by the bias resistors 6, 7, 9, and 10 are set to be equal to or higher than the pinch-off voltage of the field effect transistor 3. As a result, the field effect transistor 3 is turned off when no voltage is applied to the mute terminal 11 (that is, no signal is output to the output terminal 4). The resistors 12 and 13 make the gate voltage almost the same as the source and drain bias voltages when a voltage is applied to the mute terminal 11. As a result, the field effect transistor 3
turns on when a voltage is applied to the mute terminal 11 (that is, a signal is output to the output terminal 4).

In this circuit, if there are no variations in the resistors 6, 7, 9, and 10, the bias voltages at the source and drain of the field effect transistor 3 will be the same, but since there are variations in general, a difference occurs in the bias voltages. This voltage difference is transmitted to the output terminal 4 when the transistor 3 is turned on and off, and is finally outputted as an abnormal sound (pop sound) from the speaker via a power amplification section connected at a later stage of this circuit.

This invention is an improvement to eliminate this drawback.

An embodiment of this invention will be described below with reference to FIG. A signal input terminal 1 is connected to the drain of a field effect transistor 3 via a capacitor 2. Output terminal 4 is connected to the source of field effect transistor 3 via capacitor 5 . The source is biased by bias resistor 7 and resistor 10.
Further, the drain is biased by resistors 15 and 16 with the same voltage as the source bias. Capacitor 17 prevents a signal from going out to output terminal 4 via resistors 15 and 16 when field effect transistor 3 is off. The miute terminal 11 is connected to the gate of the field effect transistor 3 via a resistor 12. Furthermore, the gate is grounded by connecting a resistor 13 and a capacitor 14 in parallel.

The operation of this circuit is as follows. That is, the source bias voltage applied by the bias resistors 7 and 10 is set to be equal to or higher than the pinch-off voltage of the field effect transistor 3. Since the drain is connected to the source through resistors 15 and 16, it has the same bias voltage as the source. As a result, the field effect transistor 3 is turned off when no voltage is applied to the mute terminal 11 (that is, no signal is output to the output terminal 4). 12 and 13, when a voltage is applied to the mute terminal 11, the voltage at the gate is made almost the same as the bias voltage at the source and drain.
As a result, the field effect transistor 3 is turned on when a voltage is applied to the mute terminal 11 (that is, a signal is output to the output terminal 4).

In this circuit, the source and drain bias voltages are determined by a pair of bias resistors 7 and 10, so no voltage difference occurs. In addition, a bias resistor 7 is connected to the output terminal 4 side (source side in this embodiment).
10, voltage changes due to leakage current and charging current of the capacitor 2 are unlikely to occur on the output terminal 4 side when the field effect transistor 3 is turned on and off. In this way, voltage changes that cause abnormal noises (pops) are eliminated, and the drawbacks of the conventional technology can be eliminated. The mute circuit according to this invention does not generate any abnormal noise (pop sound), and can be used in multi-frequency receivers and the like that have a large number of mute sounds.

[Brief explanation of drawings]

FIG. 1 shows a conventional mute circuit, and FIG. 2 shows an embodiment of the present invention. 1: input terminal, 2, 5, 14, 17: capacitor, 3: field effect transistor, 4: output terminal,
6, 7, 9, 10, 12, 13, 15, 16: Resistor, 8: Power supply, 11: Mute terminal.

Claims (1)

[Scope of utility model registration request] The drain and source of the field effect transistor are connected in series through a capacitor between the input and output of the signal, the source and drain electrodes are connected with two series resistors, and the midpoint is grounded through the capacitor, and the source is a resistor. A mute circuit configured to be connected to a power supply via a mute circuit, and a mute signal is applied to the gate of the field effect transistor to control a signal input to the drain.