JPH03209917A - Pll type frequency synthesizer - Google Patents

Abstract

PURPOSE:To hold the frequency of a VCO constant with inexpensive, simple constitution by storing a memory with frequency shifts at respective temperatures, and reading the data out according to the output of a temperature sensor and adjusting the frequency division ratio of a frequency divider. CONSTITUTION:The shifts in oscillation frequency of a reference frequency oscillator 1 corresponding to the respective temperatures are written as digital data in an EEPROM 10. The VCO 5 is oscillated and the output of the temperature sensor 8 is digitized through an AD converter 9; and data is read out of the ROM 10 according to the temperature and sent to a control circuit 7 to adjust the frequency division ratio of a 2nd frequency divider 6, thereby holding the frequency of the VCO 5 constant.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a PLL type frequency synthesizer used as a local oscillator of a radio device, and particularly to stabilization of its frequency.

(Prior Art) Generally, the stability of this type of PLL circuit depends on the stability of a reference frequency oscillator, and therefore a crystal spine oscillator has been used as the reference frequency oscillator.

However, since the temperature characteristics of a crystal oscillator are a cubic function, correction by a temperature compensating element such as a thermistor is not sufficient, and in order to achieve a high degree of stabilization, it is necessary to house the crystal oscillator in a constant temperature bath.

(Problem to be solved by the invention) Products that use a constant temperature bath have a large shape and power consumption,
Another disadvantage is that it is expensive.

In order to perform temperature compensation without using a constant temperature bath, an element with completely opposite temperature characteristics to that of a crystal oscillator is required, but such an element is currently not available. Furthermore, since there are various characteristics, it is extremely difficult to adapt them individually.

(Means for Solving the Problems) In order to solve these drawbacks, the present invention stores the frequency deviation of the reference frequency oscillator at each temperature in a memory as digital data, and extracts the data from the output of the temperature sensor. The device is configured to automatically and finely adjust the frequency division ratio of the frequency divider used in the voltage controlled oscillator (hereinafter referred to as VCO) to maintain the Vco oscillation frequency at a constant value. This will be explained in more detail below.

(Example) The figure shows an example of the present invention, where 1 is a reference frequency oscillator, 2 is a first frequency divider, 3 is a phase comparator, and 4 is a low-pass filter (
(hereinafter referred to as LPF), 5 is a VCO.

6 is a second frequency divider, 7 is a control circuit, 8 is a temperature sensor,
9 is an analog-to-digital converter (hereinafter referred to as ADC)
, 10 are EEPROMs.

To operate this, first, the deviation in the oscillation frequency of the reference frequency oscillator 1 at each temperature (temperature per unit step) is converted into digital data and written in the EEPROMIO. In this state, the VCO 5 is caused to oscillate, but at this time the output of the temperature sensor 8 is transferred to the EEPROM via the ADC 9.
The data corresponding to the temperature is read from the IO and input to the control circuit 7. Therefore, the frequency division number of the second frequency divider 6 designated by the control circuit 7 is a value corrected for the deviation of the reference frequency. This makes the oscillation frequency of the VCO 5 stable. An example will be given here. VC
The oscillation frequency of O5 is 100MHz.

Assuming that the frequency of the reference frequency oscillator 1 is 10 MHz and the frequency division number of the first frequency divider 2 is 10.00, the frequency division number of the second frequency divider 6 in this case is 1,000. Here, the ambient temperature changes and the oscillation frequency of reference frequency oscillator 1 becomes 10Hz.
(lppm) and becomes 10.00001MHz, the oscillation frequency of VCO5 is 100.0001MHz.
It becomes Hz. However, in the present invention, a value corresponding to the deviation in the oscillation frequency of the reference frequency oscillator 1 is read from the EEPROMIO by the temperature sensor 8, and the control circuit 7
is input to correct the frequency division number of the second frequency divider 6. Therefore, the frequency division number of the second frequency divider 6 is 9,999.9.
9, the frequency input from the 20th frequency divider 6 to the phase comparator 3 is 1 when the oscillation frequency of the VCO 5 is 100 MHz.
It becomes 0,000.0IHz. Also, the frequency input from the first frequency divider 2 to the phase comparator 3 is 10,000.0
Since it is 1 Hz, the PLL circuit will be locked in this state.

Therefore, even if the oscillation frequency of the reference frequency oscillator 1 changes due to temperature, the oscillation frequency of the VCO 5 does not change, and the oscillation frequency of 100M
A highly stable PLL circuit with a constant Hz can be obtained.

A known decimal point frequency divider can be used as the second frequency divider 6 used here.

(Effect of the invention) As explained above, a temperature sensor and a temperature sensor are included in a general PLL circuit.
High stability can be obtained by adding ADC, EEPROM and control circuit. Further, the control circuit can use a CPU built into the device, and other temperature sensors, ADCs, and EEPROMs can be easily integrated into ICs, which has the advantage of being small and inexpensive.

Reference frequency oscillator, temperature sensor, ADC, EEPROM
Alternatively, if the first frequency divider (dotted line portion in the figure) is provided as a separate unit if necessary, writing to the EEPROM can be automated, and it can be widely used as a more inexpensive and highly stable reference frequency oscillator.

[Brief explanation of drawings]

The figure is a configuration diagram of an embodiment of the present invention. 1... Reference frequency oscillator, 2... First frequency divider, 3
...Phase comparator, 4...Low pass filter, 5...
- Voltage controlled oscillator, 6... 20th frequency divider, 7... Control circuit, 8... Temperature sensor, 9... SO analog-digital converter, 10... EEPROM.

Claims (2)

[Claims] (1) A reference frequency oscillator, a first frequency divider that divides the frequency of the oscillator, a phase comparator, a low-pass filter, a voltage controlled oscillator, and a second frequency divider that divides the frequency of the oscillator.
a frequency synthesizer comprising a frequency divider, a control circuit that controls a frequency division ratio of the second frequency divider, and a temperature sensor that measures the temperature of an oscillator of the reference frequency oscillator;
an analog-to-digital converter that converts the output of the temperature sensor into a digital value; and a memory that uses the output of the converter as an address to store in advance the deviation of the oscillation frequency of the reference frequency oscillator from the center value as correction data. A PLL type frequency synthesizer, characterized in that the PLL type frequency synthesizer is configured to read a corresponding value in the memory from the temperature sensor output and apply it to the control circuit during operation. (2) A PLL frequency synthesizer according to claim 1, which includes a reference frequency oscillator, a temperature sensor, an analog-to-digital converter, a memory, and, if necessary, a first frequency divider.