JPH03209851A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To realize a power supply bus line optimal in impedance by a method wherein the power supply line wire is divided into narrow power supply line wires through the intermediary of slits, and the power supply line wires are adjusted in wiring width by filling the slit of the same layer with a wiring material basing on the ratio of number of circuits to which the line wires concerned supply power. CONSTITUTION:A power supply wiring 1 is made to serve as a TTL output bus line, and a power supply wiring 4 is made to serve as an ECL output bus line. Provided that TTL circuits are larger than ECL circuits in number, slit filling patterns 6a are filled into slits to enable power supply bus lines 1-3 to serve as the TTL output bus line. Therefore, the TTL output bus line becomes large in width, so that it can be decreased in impedance and made smaller in fluctuation of ground level when a TTL output terminal is switched from a high to a low level. By this setup, a power supply bus line optimal in impedance can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device, and particularly to power supply wiring for a master slice integrated circuit.

[Conventional technology]

ECL level interface circuit, TTL and CMO
In semiconductor devices in which S-level interface circuits, etc. are mounted on a single chip, the ground is grounded as shown in Figure 4 to prevent it from affecting other input/output circuits or affecting the internal ground. In Fig. 4, when the signal level of the output terminal of the TTL output circuit switches from a high level to a low level, the discharge current of the load is Since this discharge current flows to the ground through the TTL level pass line, this discharge current and the impedance of the TTL level pass line cause a voltage drop on the TTL level pass line, causing a temporary rise in the ground level.
If the input threshold level increases and a high level is applied to the input, a malfunction may occur where the signal is transmitted as a low level, or the low level of the output may fluctuate and rise. , a signal may be erroneously transmitted to the next stage integrated circuit.

Also, when the output terminal of the ECL output circuit switches from a low level to a high level, the charging current of the load flows from the ground to the ECL output level path line, so due to this charging current and the impedance of the ECL level path line, A voltage drop occurs on the ECL output level pass line and the ground level temporarily drops, which affects the output levels of other ECL output circuits whose levels depend on the ground.

[Problem to be solved by the invention]

Since the power supply wiring width of the conventional master slice type integrated circuit device described above is designed and determined in advance as shown in FIG. 3, it is not easy to change the structure. Therefore, even when the number of ECL level interfaces is larger than that of TTL level interfaces, the impedance of the ECL output pass line and the impedance of the TTL output bus line are the same, and the ground level fluctuation due to switching of the ECL output is large. When the number of level interfaces is larger than that of ECL level interfaces, the drawbacks are that ground level fluctuations due to TTL output switching are large and that the power supply wiring is wide and wasteful through which only a small amount of current flows.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device in which the width of power supply wiring can be easily changed depending on the ratio of the number of types of circuits used, and an optimum impedance of a power supply path line can be obtained.

[Means to solve the problem]

In the semiconductor device of the present invention, the power line wiring is divided into thin sections through slits, and the width of the power line wiring is determined by filling the slits in the same layer with wiring material, depending on the ratio of the number of circuit types used. It has a means of making the pass line thicker and reducing the impedance.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of one embodiment of the present invention. Power wiring 1
is a pass line for TTL output, and power supply wiring 4 is a pass line for ECL output. For example, when the number of TTL circuits is larger than the number of ECL circuits, power supply pass lines 1 and 2 are connected as shown in the figure.
．． By inserting the slit filling pattern 6a in the same layer as the power supply wiring in 3, the path line for TTL output is made thicker and the impedance is reduced, thereby reducing the ground level when the TTL output terminal switches from high level to low level. fluctuations can be reduced. In addition, if the number of ECL output circuits is larger than the number of TTL circuits, by inserting a slit filling pattern into the slits on the ECL pass line 4 side, the ECL output pass line can be made thicker and the impedance reduced. It is possible to further reduce ground level fluctuations when the output terminal switches from low level to high level.

FIG. 2 is a plan view of another embodiment of the invention. Power supply wiring 1 is a pass line for TTL output, and power supply wiring 4 is an E
This is a pass line for CL output, and the pass line for impedance adjustment is divided for each side. If TTL output is often used on side A and ECL output is often used on side B, as shown in the same figure, by inserting the slit filling pattern 6b on side A, TTL output is often used.
By strengthening the TL output pass line and inserting a slit filling pattern 6C on side B, the ECL output pass line can be strengthened.The width of the power supply wiring is changed for each side, and the side where large current flows is strengthened. It is possible to reduce the impedance of the pass line and reduce level fluctuations.

〔Effect of the invention〕

As explained above, the present invention divides the power supply wiring into thin sections through slits, and depending on the number of circuit types used, the impedance of the power supply path line is optimized by inserting a slit filling pattern in the same layer in the width of the power supply line wiring. There are effects that can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view of the main parts of an embodiment of the present invention, FIG. 2 is a plan view of the main parts of another embodiment of the invention, and FIG. 3 is a plan view of the power line wiring of a conventional semiconductor device. , Figure 4 shows the conventional EC
FIG. 2 is a circuit diagram of a semiconductor device in which an L level output circuit, a TT613, and an L level output circuit are mounted together in one chip. 1.4... Pass line, 2, 3... Pass line for impedance adjustment, 5... Slit, 6a, 6b. 6C... Same layer slit filling button, 7... Pass line for TTL output, 8... Bus run for ECL output.

Claims (1)

[Claims] In an integrated circuit device in which a plurality of power line wirings of a master slice type integrated circuit device are provided concentrically around the periphery of the device, the power line wiring of the integrated circuit device is divided into thin sections through slits, and the circuit type An integrated circuit characterized by easily reducing the impedance of the power line on the side through which large current flows by adjusting the power line wiring width by filling the slits in the same layer with wiring material according to the ratio of the numbers used. circuit device.