JPH03209818A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a stabilized low contact resistor between a high melting point metal or its silicide layer and a diffused layer by a method wherein a defective layer is provided on the surface of the diffused layer on the boundary surface between a wiring, the lower layer part of which is composed of high melting point metal or its silicide layer, and the diffused layer. CONSTITUTION:A silicon defective layer 7 is provided on the surface of the diffusion layer 4 of a semiconductor device having a wiring 20, formed with high melting point metal or its silicide layer on the part which is brought into contact with the diffusion layer 4. To be more precise, the defective layer 7 is formed by implanting the ions such as Ar, Si, Ga and the like into a contact hole 6, and when a W-layer 8 is formed thereon, the contact resistance of the layer 8 and the defective layer 7 becomes lower than the contact resistance in effective barrier height of the W and silicon by the increase of level in the energy gap of the defective layer 7. As a result, a low contact resistance can be obtained between the W-layer 8 and the P<+> type diffusion layer 4 in a stable manner through the intermediary of the defective layer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a structure of a connecting portion between a wiring and a diffusion layer.

[Conventional technology]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device in which a diffusion layer is electrically connected to a wiring whose lower layer is made of a high-melting-point all-pole or its silicide will be described with reference to the drawings.

First, as shown in FIG. 2(a), a field oxide film 3 is formed on a silicon substrate 11, and then impurities are introduced to form a diffusion layer 12. Next, an interlayer insulating film 5 made of BP8G or the like is formed over the entire surface.

Next, as shown in FIG. 2(b), a contact hole 6 is formed in the interlayer insulating film 5 on the diffusion layer 12, and then a contact hole 6 is formed by a CVD method or the like.
llWll all layers.

Next, as shown in FIG. 2(C), AI! layer 9
After forming, buttering is performed to form a wiring 10 consisting of a W layer 8 and an AJ layer 9.

[Problem to be solved by the invention]

In the wiring formed by the conventional semiconductor device manufacturing method described above, a high melting point metal or its silicide layer and a diffusion layer 1 are used.
The contact resistance RcO value becomes high due to the value of the barrier hide qφ3, which is the Fermi level difference between the metal and silicon at the contact part with the metal, and the element speed decreases, and the yield and reliability of the semiconductor device decreases. The disadvantage is that it decreases.

Here, the contact resistance BJc is Rc2exp, but ε
S is the dielectric constant of the semiconductor, fi* is the effective mass, φ8 is the Schottky barrier, and NI) is the impurity concentration of the diffusion layer.

For example, in a CMO8 integrated circuit, when a refractory metal or its silicide has a low contact resistance with an N-type diffusion layer, a high contact resistance with a P-type diffusion layer.
When the contact resistance with the N-type diffusion layer is high, a phenomenon occurs in which the contact resistance with the P-type diffusion layer becomes low.

Possible causes of this phenomenon are as follows.

The sum of the barrier hide q$BN between the high melting point metal or its silicide and N-type silicon and the barrier hide q#BP between the high melting point metal or its silicide and P-type silicon is the energy gap Eg of silicon. Because it becomes
When qφBN is low, qφ8° is high, and when qφBN is high, qφB and P are low, which affects the value of the contact resistance. In particular, the contact resistance with the P-type diffusion layer may become extremely high.

[Means to solve the problem]

A semiconductor device of the present invention includes an impurity diffusion layer formed on a semiconductor substrate and a wiring provided on the diffusion layer and having at least a portion in contact with the diffusion layer made of a high melting point metal or its silicide layer. In the device, a silicon defect layer is provided on the surface of the diffusion layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views of semiconductor chips arranged in a sequential process order to explain an embodiment of the present invention.

First, as shown in FIG. 1 (ta+), an N well layer 2 is formed on a P type silicon substrate 1, and then a P+ type diffusion layer 4 and a field oxide film 3 are formed. Next, an interlayer insulating film 5 made of a BPSG film is formed.

Next, as shown in FIG. 1(b), a contact hole 6 is opened in the interlayer insulating film 5 on the P type diffusion layer 4.

Next, as shown in Fig. 1 (tc), crystal defects are generated in the silicon by implanting ions of Ar, Si, Ga, In, BF2, etc. into the contact hole 6 at a dose of about 1x1014 to 1x10 m. to a thickness of 10 mm on the surface of the diffusion layer below the contact hole 6.
A defect layer 7 of about 00 to 2000A is formed.

Next, as shown in FIG. 1(d), after forming a W layer 8 on the entire surface, as shown in FIG. 1(e), AI! Form layer 9.

Next, as shown in FIG. 1(f), the W layer 8 and AI! %9 patterning is performed to form wiring 20.

According to this embodiment configured in this way, the W layer 8 borders the defect layer 7, and the contact resistance between the W layer 8 and the defect layer 7 is lower than the contact resistance with the diffusion layer. It gets lower. Possible reasons for this are as follows. In other words, in the defect layer, the energy level in the energy gap increases and the effective barrier height between W and silicon (qφ8) decreases compared to when contacting with a defect-free layer, so the contact resistance R6 decreases. It is something.

As described above, W%g can stably obtain low contact resistance with the P+ type diffusion layer 4 via the defect layer 7.

Incidentally, in the above embodiment, the case where W is used as the high melting point metal constituting the wiring is explained, but the invention is not limited to this, and MO-? Ti and silicides thereof may also be used. Further, the wiring may be made of a single layer of high melting point metal or its silicide.

〔Effect of the invention〕

As explained above, the present invention provides a method for forming a high melting point metal layer by providing a defect layer on the surface of the diffusion layer at the interface between the wiring and the diffusion layer, the lower layer of which is made of a high melting point metal or its silicide layer. Alternatively, a stable and low contact resistance can be obtained between the silicide layer and the diffusion layer. Therefore, stable characteristics of the element can be obtained and the speed can be improved, which has the effect of improving the yield rate and reliability of the semiconductor device.

61

[Brief explanation of drawings]

1(a) to 1(f) are cross-sectional views of semiconductor chips arranged in the order of manufacturing steps for explaining one embodiment of the present invention;
Figures (a) to (C) are cross-sectional views of semiconductor chips arranged in the order of manufacturing steps to explain a conventional example. 1... P type silicon substrate, 2... N well layer, 3...
...Field oxide film, 4...P-type diffusion layer, 5...
- Interlayer insulating film, 6... Contact hole, 7... Defect layer, 8... W layer, 9... Aj? Layer 10...wiring,
11... Silicon substrate, 12... Diffusion layer.

Claims (1)

[Claims] In a semiconductor device having an impurity diffusion layer formed on a semiconductor substrate and a wiring provided on the diffusion layer and having at least a portion in contact with the diffusion layer made of a high melting point metal or a silicide layer thereof, the diffusion layer surface A semiconductor device characterized in that a silicon defect layer is provided in the semiconductor device.