JPH03209733A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03209733A JPH03209733A JP2003975A JP397590A JPH03209733A JP H03209733 A JPH03209733 A JP H03209733A JP 2003975 A JP2003975 A JP 2003975A JP 397590 A JP397590 A JP 397590A JP H03209733 A JPH03209733 A JP H03209733A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- connection
- tip
- semiconductor element
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 230000006866 deterioration Effects 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 4
- 238000005452 bending Methods 0.000 abstract description 3
- 238000007665 sagging Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 239000010931 gold Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体素子上の複数の電極端子と、該半導体素子の外周
に沿って該各電極端子と対応して位置する外部リード端
子とをボンディング接続してなる半導体装置に関し、
ボンディング接続特性の向上を図ることを目的とし、
半導体素子表面の周辺に沿う複数の電極端子と、該半導
体素子の外周に沿って上記電極端子に対応して位置する
複数のリード端子の先端部との間を、ワイヤボンディン
グ接続してなる半導体装置であって、半導体素子の同電
位となる複数の電極端子に繋がる複数のボンディングワ
イヤが、リード端子の先端部に垂直方向に積み重ねた状
態でボンディング接続して構成する。[Detailed Description of the Invention] [Summary] A semiconductor formed by bonding a plurality of electrode terminals on a semiconductor element and external lead terminals located corresponding to each electrode terminal along the outer periphery of the semiconductor element. Regarding the device, for the purpose of improving bonding connection characteristics, a plurality of electrode terminals along the periphery of the surface of the semiconductor element and a plurality of lead terminals located along the outer periphery of the semiconductor element corresponding to the electrode terminals are provided. A semiconductor device in which a plurality of bonding wires connected to a plurality of electrode terminals having the same potential of a semiconductor element are stacked vertically on the tip of a lead terminal, in which a plurality of bonding wires are connected to the tip by wire bonding. Configure by making bonding connections.
本発明は半導体素子上の電極端子と該半導体素子の周囲
で該各電極端子と対応して位置する外部リード端子との
間のボンディング接続技術に係り、特にボンディング接
続特性の向上を図った半導体装置に関する。The present invention relates to a bonding connection technology between electrode terminals on a semiconductor element and external lead terminals located around the semiconductor element in correspondence with each electrode terminal, and in particular to a semiconductor device with improved bonding connection characteristics. Regarding.
近年の半導体素子の高集積化に伴い該半導体素子に接続
されるボンディングワイヤの数が急速に増大しつつある
が、その結果該半導体素子の周囲に該半導体素子の電極
端子の数に対応して配設する外部リード端子の幅および
ピッチが益々狭くなることから上記ボンディングワイヤ
の接続が難しくなってきている。The number of bonding wires connected to a semiconductor element is rapidly increasing due to the high integration of semiconductor elements in recent years. As the width and pitch of external lead terminals are becoming increasingly narrower, it is becoming more difficult to connect the bonding wires.
［従来の技術〕
第３図は従来の半導体装置のワイヤボンディング部分を
説明する図である。[Prior Art] FIG. 3 is a diagram illustrating a wire bonding portion of a conventional semiconductor device.
図でセラミック等からなる絶縁基板ｌの表面には、複数
の電極端子２ａが周辺に沿って例えば１２６μｍピッチ
で形成されている半導体素子２を実装する例えば金（Ａ
ｕ）メツキされたグランド領域１ａと。In the figure, a plurality of electrode terminals 2a are formed along the periphery at a pitch of, for example, 126 μm on the surface of an insulating substrate l made of ceramic or the like.
u) Plated ground area 1a.
該領域１ａの周囲から上記複数の電極端子２ａに対応し
て内側に向かう逆放射状に形成されている金（ＡＵ）メ
ツキされた複数のリード端子１ｂとがパターン形成され
ている。A plurality of gold (AU) plated lead terminals 1b are formed in a reverse radial pattern from the periphery of the region 1a toward the inside corresponding to the plurality of electrode terminals 2a.
なお、該リード端子１ｂの上記電極端子２ａと対向する
各先端部１ｃは、例えば隣接間ピッチｐと個々の幅Ｗが
それぞれ１５０μｍ程度で、上記半導体素子２の各対応
する電極端子２ａからの隔たりｄがほぼ一定になるよう
に該半導体素子２ひいては上記グランド領域１ａの中心
をセンタとする半径Ｒの円上に位置するように配置され
ている。Note that each tip portion 1c of the lead terminal 1b facing the electrode terminal 2a has, for example, an adjacent pitch p and an individual width W of about 150 μm, and a distance from each corresponding electrode terminal 2a of the semiconductor element 2. The semiconductor element 2 is arranged so as to be located on a circle having a radius R and centered on the center of the ground area 1a so that d is approximately constant.
なお上記の各先端部１ｃの隣接間ピッチｐと個々の幅Ｗ
は、前者はパターン形成技術および隣接間の絶縁性確保
の面から設定され、また後者はボンディング特性を確保
するための有効幅として設定されるものであるが、現状
では上記１５０μｍはほぼ最小値とされている。In addition, the pitch p between adjacent tips of each of the above-mentioned tip portions 1c and the individual width W
The former is set from the perspective of pattern formation technology and ensuring insulation between adjacent parts, and the latter is set as an effective width to ensure bonding characteristics, but at present, the above 150 μm is almost the minimum value. has been done.
そこで、上記半導体素子２をグランド領域１ａの所定位
置に搭載接続した後、図示されないボンディング・マシ
ーンによって上記半導体素子２の各電極端子２ａと該各
電極端子２ａと対応するリード端子１ｂの先端部１ｃと
の間を例えば直径が３８μｍ位の金（Ａｕ）線からなる
ボンディングワイヤ（以下単にワイヤとする）３でボン
ディング接続（以下単に接続とする）すると絶縁基板１
に接続された半導体装置を得ることができる。Therefore, after mounting and connecting the semiconductor element 2 at a predetermined position in the ground area 1a, each electrode terminal 2a of the semiconductor element 2 and the tip portion 1c of the lead terminal 1b corresponding to each electrode terminal 2a are bonded by a bonding machine (not shown). When a bonding wire (hereinafter simply referred to as wire) 3 made of, for example, a gold (Au) wire with a diameter of about 38 μm is used to make a bonding connection (hereinafter simply referred to as connection) between the insulating substrate 1
A semiconductor device connected to the semiconductor device can be obtained.
なお、例えば複数（図では２ａ’と２ａ″の２個の場合
としている）の電極端子を同し電位の電源ライン等に接
続するようなときには、該複数の電極端子（２ａ°と２
ａ”）に対応するリード端子（ｌｂ゛）の先端部（ｌｃ
“）を共通して使用するようにしている。For example, when connecting a plurality of electrode terminals (2a' and 2a'' in the figure) to a power supply line with the same potential, the plurality of electrode terminals (2a' and 2a'')
The tip (lc) of the lead terminal (lb) corresponding to
“) are commonly used.
かかる図示の如き半導体装置では、上述したように半導
体素子２の各電極端子２ａとリード端子１ｂの先端部１
ｃとの間の隔たりｄがほぼ一定になっているため、安定
した状態で接続することができる。In the semiconductor device as shown in the figure, each electrode terminal 2a of the semiconductor element 2 and the tip end 1 of the lead terminal 1b are connected to each other as described above.
Since the distance d between the terminal and the terminal c is approximately constant, the connection can be made in a stable state.
しかし、複数のワイヤを接続する先端部（図では１０°
）の幅（Ｗ“）は安定した接続特性を確保するため接続
するワイヤ数に対応して拡げる必要があり、その結果所
定数のリード端子を確保するには他の先端部１ｃの隣接
間ピッチｐまたは幅Ｗを狭くせざるを得ない。However, the tip part that connects multiple wires (10° in the figure)
) must be increased in accordance with the number of wires to be connected in order to ensure stable connection characteristics.As a result, in order to secure a predetermined number of lead terminals, the width (W") of p or the width W has to be narrowed.
一方、上述したように該ピッチｐまたは先端部１ｃの幅
Ｗを狭くすることは好ましくない。On the other hand, as described above, it is not preferable to narrow the pitch p or the width W of the tip 1c.
そこで、上述した半径Ｒすなわち半導体素子２の電極端
子２ａから先端部１ｃまでの上記隔たりｄを大きくして
上記のピッチｐおよび有効なボンディング幅Ｗ＠確保す
るようにしているが、この場合にはワイヤが長くなるた
め該ワイヤの曲がりや垂れ下がり等が発生して隣接ワイ
ヤ間で接触する等の現象が生じ、結果的に接続特性の低
下を招くことになる。Therefore, the above-mentioned radius R, that is, the above-mentioned distance d from the electrode terminal 2a to the tip 1c of the semiconductor element 2 is increased to ensure the above-mentioned pitch p and effective bonding width W@. As the wire becomes longer, the wire may bend or sag, causing phenomena such as contact between adjacent wires, resulting in deterioration of connection characteristics.
従来の半導体装置では、複数の電極端子を同電位のリー
ド端子に纏めて接続する場合には該リード端子の先端部
の幅を拡げなければならないことから、所定数のリード
端子を確保するには各リード端子の先端部位置を該半導
体素子から離さなければならず、結果的にワイヤが長く
なって該ワイヤの曲がりや垂れ下がりによって隣接ワイ
ヤ間で接触する等の如く接続特性が低下するという問題
があった。In conventional semiconductor devices, when connecting multiple electrode terminals to a lead terminal with the same potential, it is necessary to increase the width of the tip of the lead terminal, so in order to secure a predetermined number of lead terminals, The tip of each lead terminal must be moved away from the semiconductor element, which results in longer wires, resulting in lower connection characteristics such as contact between adjacent wires due to bending or sagging of the wires. there were.
［課題を解決するための手段〕
上記問題点は、半導体素子表面の周辺に沿う複数の電極
端子と、該半導体素子の外周に沿って上記電極端子に対
応して位置する複数のリード端子の先端部との間を、ワ
イヤボンディング接続してなる半導体装置であって、半
導体素子の同電位となる複数の電極端子に繋がる複数の
ボンディングワイヤが、リード端子の先端部に垂直方向
に積み重ねた状態でボンディング接続されている半導体
装置によって解決される。[Means for Solving the Problems] The above problem is caused by a plurality of electrode terminals along the periphery of the surface of a semiconductor element, and tips of a plurality of lead terminals located along the outer periphery of the semiconductor element corresponding to the electrode terminals. A semiconductor device in which a plurality of bonding wires connected to a plurality of electrode terminals having the same potential of a semiconductor element are stacked vertically on the tip of a lead terminal. The problem is solved by bonding connected semiconductor devices.
同質材料からなるワイヤ相互間は容易にボンディング接
続することができる。Wires made of the same material can be easily bonded to each other.
本発明では、リード端子の先端部に対する複数のワイヤ
の接続を従来の平面的配置から垂直方向の積み重ね接続
に代えることで該リード端子の先端部の幅の拡大を抑制
している。In the present invention, the connection of a plurality of wires to the tip of the lead terminal is changed from the conventional planar arrangement to a vertically stacked connection, thereby suppressing an increase in the width of the tip of the lead terminal.
この場合には、半導体素子の電極端子からリード端子の
先端部までの隔たりを大きくすることなく所定のリード
端子を所要数だけ形成することが可能となる。In this case, it is possible to form a predetermined number of lead terminals without increasing the distance from the electrode terminal of the semiconductor element to the tip of the lead terminal.
従ってワイヤを長くする必要がないため、該ワイヤの曲
がりや垂れ下がりによる隣接ワイヤ間の接触等の接続特
性の低下を抑制することができる。Therefore, since it is not necessary to make the wires long, it is possible to suppress deterioration of connection characteristics such as contact between adjacent wires due to bending or hanging of the wires.
［実施例］
第１図は本発明になる半導体装置主要部の一例を示す図
であり、（Ａ）は外観図、（Ｂ）は接続部を拡大した側
面図である。[Embodiment] FIG. 1 is a diagram showing an example of a main part of a semiconductor device according to the present invention, in which (A) is an external view and (B) is an enlarged side view of a connecting portion.
また第２図は他の実施例を示す図である。Moreover, FIG. 2 is a diagram showing another embodiment.
第１図（Ａ） 、 （Ｂ）で、第３図同様のセラミック
等からなる絶縁基板ｌＯの表面には、第３図で説明した
半導体素子２を実装する金（Ａｕ）メツキされたグラン
ド領域１０ａと、該領域１０ａの周囲から上記半導体素
子２の複数の電極端子２ａに対応して内側に間かう逆放
射状の金（Ａｕ）メツキされた複数のリード端子１０ｂ
とがパターン形成されている。In FIGS. 1(A) and 1(B), the surface of an insulating substrate lO made of ceramic or the like similar to that shown in FIG. 10a, and a plurality of lead terminals 10b plated with gold (Au) in a reverse radial shape extending inward from the periphery of the region 10a corresponding to the plurality of electrode terminals 2a of the semiconductor element 2.
A pattern is formed.
なお、該各リード端子１０ｂの上記電極端子２ａと対問
する各先端部１０ｃが、隣接間ピッチｐと個々の幅Ｗが
それぞれ１５０μｍ程度に形成されており、更に上記半
導体素子２の各対応する電極端子２ａからの隔たりｄが
ほぼ一定になるように該半導体素子２ひいては上記グラ
ンド領域１０ａの中心をセンタとする半径Ｒの円上に配
置されていることは第３図の場合と同様である。Note that each tip end portion 10c of each lead terminal 10b facing the electrode terminal 2a is formed with an adjacent pitch p and an individual width W of approximately 150 μm, and furthermore, each of the tip portions 10c of each lead terminal 10b is formed to have a pitch p between adjacent portions and an individual width W of approximately 150 μm, and furthermore, each tip portion 10c of each lead terminal 10b is formed to have a pitch p between adjacent portions and an individual width W of approximately 150 μm. As in the case of FIG. 3, the semiconductor element 2 is arranged on a circle having a radius R centered on the center of the ground area 10a so that the distance d from the electrode terminal 2a is approximately constant. .
そこで、第３図で説明したように上記半導体素子２をグ
ランド領域１０ａの所定位置に搭載接続した後、図示さ
れないボンディング・マシーンによって上記半導体素子
２の各電極端子２ａと該各電極端子２ａと対応するリー
ド端子１０ｂの先端部１０ｃとの間を第３図で説明した
ワイヤ３で接続するが、この際電源ラインの如き同電位
のリード端子ｌＯｂ′に繋がる該半導体素子２の２個の
電極端子２８′と２ａ”は、例えば電極端子２８ｆから
のワイヤ３１を上記リード端子１０ｂ ’の先端部１０
０′に接続した後、該ワイヤ３°の該接続部上に電極端
子２８″からのワイヤ３ ＩＴを接続するようにしてい
る。Therefore, after the semiconductor element 2 is mounted and connected at a predetermined position in the ground area 10a as explained in FIG. The wire 3 explained in FIG. 28' and 2a'', for example, connect the wire 31 from the electrode terminal 28f to the tip 10 of the lead terminal 10b'.
0', the wire 3IT from the electrode terminal 28'' is connected onto the connection at 3° of the wire.
図はこの状態を表わしたものである。The figure shows this state.
特にこの場合には、ワイヤ３′と３”が同質材料なるた
め積み重ねたときの接続が容易であり且つ上述したよう
に半導体素子２の各電極端子２ａとリード端子ｌＯｂの
先端部１０ｃとの間の隔たりｄがほぼ一定であるため安
定した状態で接続することができる。Particularly in this case, since the wires 3' and 3'' are made of the same material, connection when stacked is easy, and as described above, the connection between each electrode terminal 2a of the semiconductor element 2 and the tip portion 10c of the lead terminal lOb is facilitated. Since the distance d is almost constant, the connection can be made in a stable state.
更に、該先端部１０ｃ°の幅を拡げる必要がないことか
ら、他の各リード端子１０ｂの先端部１０ｃの位置を半
導体素子２の各電極端子２ａから離すことがなくなって
第３図で説明したような隣接ワイヤ間の接触等ボンディ
ング特性の低下を抑制することができる。Furthermore, since there is no need to widen the width of the tip 10c, the tip 10c of each of the other lead terminals 10b is not separated from each electrode terminal 2a of the semiconductor element 2, as explained in FIG. It is possible to suppress deterioration of bonding characteristics such as contact between adjacent wires.
３個のワイヤを１個のリード端子に接続する状態を示す
第２図で、平面図（ａ−１）とその側面図（ａ〜２）は
接続点を垂直に積み重ねた場合を示し、また平面図（ｂ
−１）とその側面図（ｂ−２）は接続点をリード端子の
長手方向に沿ってずらした場合をそれぞれ表わしている
。Figure 2 shows how three wires are connected to one lead terminal, and the top view (a-1) and side views (a-2) show the connection points stacked vertically; Plan view (b
-1) and its side view (b-2) respectively represent the case where the connection point is shifted along the longitudinal direction of the lead terminal.
なお（ａ−１） 、 （ａ−２）と（ｂ−１） 、 （
ｂ−２）共に、２が半導体素子、 ２ａが電極端子を示
し、またｌＯが絶縁基板、１０ａがグランド領域、１０
ｂ’が３個のワイヤを接続するリード端子＋ｉ０ｃ’が
該リード端子１０ｂ°の先端部を示していることは第１
図の場合と同様である。Note that (a-1), (a-2) and (b-1), (
b-2) In both, 2 indicates a semiconductor element, 2a indicates an electrode terminal, lO indicates an insulating substrate, 10a indicates a ground region, and 10
The first fact is that b' indicates the lead terminal connecting the three wires +i0c' indicates the tip of the lead terminal 10b°.
This is the same as the case shown in the figure.
（ａ−１） 、 （ａ−２）の場合では、先ずワイヤ３
ａを該先端部１０ｃ′に接続した後ワイヤ３ｂを該ワイ
ヤ３ａの接続部の真上に積み重ねて接続し、更にワイヤ
３Ｃを該ワイヤ３ｂの真上に積み重ねて接続している。In cases (a-1) and (a-2), first wire 3
After connecting the wire 3a to the tip 10c', the wire 3b is stacked and connected right above the connection part of the wire 3a, and the wire 3C is further stacked and connected right above the wire 3b.
また（ｂ−１） 、 （ｂ−２）の場合では、先ずワイ
ヤ３ａを該先端部１０ｃ ’のＰｔ点に接続した後、該
先端部１０ｃ ’の長手方向で上記９１点の外側に近接
して位置する９２点にワイヤ３ｂ”を接続し、更に該ｐ
！点の外側に近接して位置する該先端部１０Ｃ°上の９
３点にワイヤ３ｃ’をそれぞれ接続している。In cases (b-1) and (b-2), the wire 3a is first connected to the Pt point of the tip 10c', and then the wire 3a is connected to the outside of the 91 points in the longitudinal direction of the tip 10c'. Connect the wire 3b'' to 92 points located at
! 9 above the tip 10C° located close to the outside of the point
Wires 3c' are connected to three points, respectively.
特にかかる接続の場合には、各ワイヤが同質材料で構成
されているため各ワイヤ相互間の接続性が良好であり、
各ワイヤ間で脱落したり接触性が低下する等のことがな
くなって確実な接続特性を確保することができる。Especially in the case of such a connection, since each wire is made of the same material, the interconnectivity between each wire is good,
Reliable connection characteristics can be ensured since the wires do not fall off or the contact properties deteriorate.
上述の如く本発明により、ボンディング接続特性の向上
を図った半導体装置を提供することができる。As described above, according to the present invention, a semiconductor device with improved bonding connection characteristics can be provided.
第１図は本発明になる半導体装置主要部の一例を示す図
、
第２図は他の実施例を示す図、
第３図は従来の半導体装置のワイヤボンディング部分を
説明する図、
である。図において、
２は半導体素子、
２ａ、 ２ａ ’ 、 ２ａ”は電極端子、３＋ ３
’ ＋３”＋３ａｔ３ｂ＋３ｃ、３ａ ’ ＋ ３ｂ
’ ＋ ３ｃ ’はボンディングワイヤ、
１０は絶縁基板、 １０ａはグランド領域、１０ｂ
、 １０ｂ’はリード端子、
１０ｃ、 １０ｃ ’は先端部、
をそれぞれ表わす。
（Ａ）
（Ｂ）
オＪ斧明（＝なう４Ｐ場イ本装置」ミチ音戸の一ヂクリ
を示す国事
図
（α−
）
（ｄ
２ン
（ｂ−１）
（１−２）
他へわ己伊１を示す図
第
凹FIG. 1 is a diagram showing an example of the main part of a semiconductor device according to the present invention, FIG. 2 is a diagram showing another embodiment, and FIG. 3 is a diagram illustrating a wire bonding part of a conventional semiconductor device. In the figure, 2 is a semiconductor element, 2a, 2a', 2a'' are electrode terminals, 3+3
'+3''+3at3b+3c, 3a'+3b
'+3c' is a bonding wire, 10 is an insulating substrate, 10a is a ground area, 10b
, 10b' represents a lead terminal, and 10c, 10c' represent a tip, respectively. (A) (B) OJ Akiaki (= Now 4P field this device) National affairs map showing Michi Ondo's first work (α-) (d 2n (b-1) (1-2) Other pages Diagram showing self-I 1 concave
Claims (1)
導体素子の外周に沿って上記電極端子に対応して位置す
る複数のリード端子の先端部との間を、ワイヤボンディ
ング接続してなる半導体装置であって、 半導体素子（２）の同電位となる複数の電極端子（２ａ
′、２ａ″）に繋がる複数のボンディングワイヤ（３′
、３″）が、リード端子（１０ｂ′）の先端部（１０ｃ
′）に垂直方向に積み重ねた状態でボンディング接続さ
れていることを特徴とした半導体装置。[Claims] Wire bonding is performed between a plurality of electrode terminals along the periphery of the surface of a semiconductor element and the tips of a plurality of lead terminals located along the outer periphery of the semiconductor element corresponding to the electrode terminals. A semiconductor device formed by connecting a plurality of electrode terminals (2a) that have the same potential of a semiconductor element (2).
′, 2a″) connected to multiple bonding wires (3′, 2a″)
, 3'') is the tip (10c) of the lead terminal (10b').
′) A semiconductor device characterized by being bonded and connected in a vertically stacked state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003975A JPH03209733A (en) | 1990-01-11 | 1990-01-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003975A JPH03209733A (en) | 1990-01-11 | 1990-01-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03209733A true JPH03209733A (en) | 1991-09-12 |
Family
ID=11572062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003975A Pending JPH03209733A (en) | 1990-01-11 | 1990-01-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03209733A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002033347A (en) * | 2000-07-17 | 2002-01-31 | Rohm Co Ltd | Semiconductor device |
| JP2003051514A (en) * | 2001-08-06 | 2003-02-21 | Rohm Co Ltd | Connection method using fine metal wire and semiconductor device employing the same |
| JP2008047679A (en) * | 2006-08-15 | 2008-02-28 | Yamaha Corp | Semiconductor device and wire bonding method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6143436A (en) * | 1984-08-08 | 1986-03-03 | Hitachi Ltd | Bonding process |
| JPS63114138A (en) * | 1986-10-31 | 1988-05-19 | Hitachi Ltd | Bonding method for wire laminated layer |
-
1990
- 1990-01-11 JP JP2003975A patent/JPH03209733A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6143436A (en) * | 1984-08-08 | 1986-03-03 | Hitachi Ltd | Bonding process |
| JPS63114138A (en) * | 1986-10-31 | 1988-05-19 | Hitachi Ltd | Bonding method for wire laminated layer |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002033347A (en) * | 2000-07-17 | 2002-01-31 | Rohm Co Ltd | Semiconductor device |
| JP2003051514A (en) * | 2001-08-06 | 2003-02-21 | Rohm Co Ltd | Connection method using fine metal wire and semiconductor device employing the same |
| JP4680439B2 (en) * | 2001-08-06 | 2011-05-11 | ローム株式会社 | Connection method using thin metal wire and semiconductor device using the same |
| JP2008047679A (en) * | 2006-08-15 | 2008-02-28 | Yamaha Corp | Semiconductor device and wire bonding method |
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