JPH03205919A - Compound semiconductor integrated circuit using gallium arsenide - Google Patents

Abstract

PURPOSE:To obtain a prescribed value in an output H level, and also, to reduce the variance of an output by providing a resistance element between the source electrode of a load element consisting of an enhancement type field effect transistor(FET) and the prescribed potential. CONSTITUTION:When an input node N10 comes to an L level, an enhancement type driving FET F11 is cut off, and an output node N11 rises to an H level. In connection therewith, the value of a current IH increases gradually, and when currents flowing through an enhancement type load FET F10 and a resistance element become equal, the rise of the node N11 stops. In such a case, the value of the current IH when the potential rise of the node N11 stops is set in advance to a value being equal to the value of a sub-threshold current when the gate-source voltage of the FET F10 comes to a threshold voltage of the FET F10. In such a way, the output level can be set to a value as designed, and also, its variance is reduced.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to an integrated circuit using a compound semiconductor gallium arsenide, and particularly to increasing the accuracy of level setting thereof.

[Conventional technology]

Conventionally, logic circuits in integrated circuits using compound semiconductor gallium arsenide are DCFL (Dire
ct Coupled FET logic)
is commonly used. This circuit uses a depletion field effect transistor (hereinafter referred to as FET) F20, whose gate electrode is connected to the source electrode, as a load element, and an enhancement type circuit in which a logic signal is input to a node (gate electrode) N20. FET
F21 is a switching element, the drain of FET F20 is connected to the power supply Vcc, and the source of FET F2↓ is connected to the power supply Vss. In Figure 2, for the following explanation,
This shows a case where two stages of DCFLs are connected in cascade. In this circuit, the inverted output of the signal input to the node N20 is obtained at the node N21, and FIG. 3 shows the relationship between the input signal and the output signal. When the input signal of node N20 becomes II High high TT level, the output level of node N21 becomes "LoII+".
" level, and its value is approximately Vss. Also, when the input signal of node N20 becomes "Low" level,
The output level of node N21 becomes "High" level and approaches the Vcc level, but the output level of the next stage FET
Due to the Schottky characteristic between the gate and source of F23, V
Clamped to ss+0.7V. In this way, the output level of the logic circuit is determined by vSS and the Schottky characteristic, and there is no large difference from the value obtained by circuit simulation. In addition, in the circuit of FIG. 2, the DCFL consisting of the next stage FETs F22 and F23
+1 of node N21 if the circuit is not connected }
{ i gh I+ level becomes Vcc. However, all logic circuits in this integrated circuit are D
It is not possible to construct the circuit using only CFLs, but it is necessary to use the circuit shown in FIG. 4 due to the necessity of obtaining an output level of a predetermined potential. In FIG. 4, F40 and F41 are enhancement type FETs, a logic signal is input to a node N40, and an inverted output is obtained at a node N41. FET
A constant potential Vg for defining the "High" level of the output node N41 is applied to the gate electrode Ng40 of F40. In this case, “High” of node N41
"It was common to assume that the level was given by Vg - VthE. Here, VthE is the threshold voltage of FET F40, and when the gate-source voltage is less than VthE, the current flowing through the FET is defined as a value that can almost be considered a cutoff."H" of node N41
The reason why the "High" level is set to Vg-VthE is as follows.In order to set the node N41 to the "High" level, the node N40 first becomes the "Low11" level, that is, the potential of Vss. FET F41
The current Ids flowing through is cut off. This operation causes the potential at node N41 to rise until the current Ids flowing through FET F40 is cut off without charging the capacitive load associated with node N41. FETF40
The current Ids becomes cut-off because the potential of the node N41 rises and the potential VN41 becomes a value VthE lower than the potential Vg of the node Ng40, that is, Vg −
When VN4 1 = VthE, node N41
The change in potential of will stop. This means that node N
The "High" level of 41 is the Vg-Vt mentioned above.
This means that it is set to hE. however,
As explained in FIG. 5 below, even if the gate-source voltage becomes less than V thE, the current flowing through the FET is not completely cut off, and the “High” level of node N41
This will cause an error in the level. Figure 5 shows FET
This figure shows the relationship between the drain-source current 1 ds and the gate-source voltage Vgs per 10 μm gate width of F40. As can be seen from this figure, as the voltage Vgs decreases, the current Ids decreases rapidly, but the degree of decrease gradually becomes smaller, and when the current Ids is about to stop flowing, the current Ids decreases with respect to the change in the voltage Vgs. The rate of decrease becomes a very small value. The threshold voltage V thE of FET is gate @IOμm, LJ, 5μA
Generally, the voltage Vgs is taken as the voltage when the current Ids decreases to There is a region where the current does not decrease and a current of about μA remains. In this way, the current Ids that flows even if the voltage Vgs becomes less than vth is defined as the subthreshold current (I
dsb). This current I ds
b, the output level of the circuit shown in FIG.
"A phenomenon occurs in which the potential increases further than the expected level value. In other words, the potential VN41 of the node N41 is
Since the current Ids increases until it is completely cut off, it does not stop at the potential of Vg41-VthE, and the current Ids
sb continues to rise until it reaches the cutoff. This potential increase is as much as 0.1-0.2V, and from this,
This results in an increase in the width of the signal IiR of note N41 and an increase in delay time at the time of a transient signal change. In addition, in MOSFETs using Si as a substrate, the value of this subthreshold current I dsb is about nA, which is three orders of magnitude smaller, and in circuits using FETs using gallium arsenide as a substrate, the influence of I dsb occurs significantly. do. In addition, in the region where the gate-source voltage Vgs is less than V thE. The value of Ids is μA
If there is a small leakage current in FET F41 in FIG.
The potential rise of 0.2v is greatly affected, and node N41
This also causes variations in the "High" level. The influence of the subthreshold current I dsb of the FET on the output level has been described above, but we will now discuss a specific example where the circuit shown in #4 is used in an integrated circuit. FIG. 6 shows a circuit of memory cells and data lines to which the memory cells are connected, which is commonly used in static memory LSIs. In the figure, 6
0 is a memory cell, d60 and d61 are data lines to which a plurality of memory cells are connected, L60. L61 is a load element connected to a data line, S60 and S61 are switch elements for selecting a data line pair, and SA is a sense amplifier for amplifying a read signal from a memory cell. In FIG. 6, load element L60. L61 is F in FIG.
The FET F40 is connected to the FET F60 in the memory cell.
F61 corresponds to FETF41 in FIG. Load elements L60, L61 and FET in the memory cell
By making all of them enhancement type FETs and setting them to the same threshold voltage vth, the influence of manufacturing variations in threshold voltage vth is minimized. In FIG. 6, information is read from the memory cell 60 in the following manner. Each memory cell 60 is a flip
It is composed of a flop, and the node N60 is at a low level, that is, the potential of Vss, and the node N61 is at a high potential.
Assume that the potential is h level, that is, Vss+0.7V. In this state, the word line WL60 goes high.
When the level is reached, it means that the memory cell 60 has been selected, and the read current Ir changes as shown in FIG. Vcc
-+ L 6 0→d60-eF60-+F62→Vs
s, and the potential of the data line d60 decreases. On the other hand, in the data line cl61, FET F63.
Since F61 is cutoff, the read current I
If r does not flow and the potential of node Ng61 is Vg61, it is set to Vg61 - VthE. In this way, a potential difference is generated between the data lines d60 and d61, this potential difference is input to the sense amplifier SA through the switch elements S60 and S6l, and the amplified signal is taken out of the chip. However, as explained in Figures 4 and 5. FET subthreshold current I
dsb, the potential of data line d61 is Vg6 1
- Increased by 0.1 to 0.2V from VthE, sono result, d60. d6l(1) Potential difference, that is, the read signal voltage is about 0.2Vl of the design value: 1.5 to 2.
This increases by a factor of 0, resulting in an increase in the delay time on the data line.
Furthermore, since a large number of memory cells are connected to the data line, if there is a slight leakage current to the memory cells that are not in the selected state, the potential of the data line d61 will be 0.1 to It will vary within a range of 0.2V. Due to this phenomenon, the read signal amplitude varies depending on the combination of information retention states of the memory cells connected to the data line, which also increases the delay time variation during the read operation. A circuit similar to that shown in FIG. 6 is disclosed in Japanese Patent Application Laid-Open No. 61-208697. JP-A-63-160087. Unexamined Japanese Patent Publication 1986
-311691. Japanese Patent Publication No. 63-34793, and
Institute of Electronics, Information and Communication Engineers Study Group Technical Research Report ED86-135
, P39-P46, rGaAs4Kb static RAMJ. In addition, Japanese Patent Application Laid-Open No. 63-311691. In the circuit described in the technical research report of the Institute of Electronics, Information and Communication Engineers, the gate electrode of the load element of the data line is connected to the drain electrode.
1-208697, a circuit for applying a potential to the gate electrode of the load element is added, but there is no essential difference in that the phenomenon described above occurs.

[Problem to be solved by the invention]

In the above conventional technology, in a logic circuit whose load element is an enhancement type FET whose gate electrode is fixed at a constant potential, no consideration is given to the setting of the "High" level of the output level of this logic circuit. There has been a problem in that an increase in the output level due to the subthreshold current and variations in the output "High" level due to leakage current of the drive element occur. The object of the present invention is that the output +l High+ of the logic circuit
The objective is to obtain a predetermined value at the ``level'' and to reduce variations.

Means for Solving the Problems 1 In order to achieve the above object, the present invention forms a leak path by inserting a resistance element between the source electrode of an enhancement type FET and a constant potential. [Function] The resistance element inserted between the output terminal of the logic circuit and a constant potential causes the gate-source voltage Vgs of the enhancement type load element to become V thE when the logic circuit outputs a "High" level. Since it is designed to flow a current equivalent to the subthreshold current when
This means that hE can be set to a value that can be predicted at the time of design. Furthermore, since the enhancement type load element operates in a region where the impedance is low with respect to the leakage current of the perturbation FET, it is possible to reduce level variations. [Embodiment] An embodiment of the present invention will be described below with reference to FIG. 1st
In the figure, Vcc. Vss is a power supply kept at a constant potential, FIO is an enhancement type load FET. F11 is an enhancement IJig movement FET, RIO is a resistance element inserted between the output node Nil and the power supply Vss,
NglO is a level setting potential input terminal connected to the gate electrode of the load FET FIO, node 10 is the input terminal, and II is the potential that flows through the load FET FIO and the resistive element RIO when the circuit in Figure 1 outputs a "High" level. It is an electric current. In the circuit shown in Figure 1, the node NIO is “LOW
” level, that is, Vss, the drive FET
Fil becomes the cutoff and node N. 1 1 is “H”
II H of node Nil.
As the current IH rises to the igh ++ level, the value of the current IH also gradually increases, and the load FET FIO and resistance element R1
When the currents flowing through 0 become equal, the node N 1 1
stops rising. In the present invention, the value of the current [1 at the time when the potential rise of the node Nil stops is the value of the resistance element RIO
Therefore, the subthreshold current I when the gate-source voltage of the load FET FIO becomes V thE
It is important that the value is set equal to the value of dsb. In this way, by setting the value of the resistive element RIO to satisfy the above conditions, the "High" level of Nil is given by the gate-source voltage of the load FET FIO - V thE. . This situation will be explained in more detail using FIG. 7. In FIG. 7, the vertical axis represents the current IH in FIG. 1, and the horizontal axis represents the gate-source voltage of the load FET FIO in FIG. The node NglO(7) potential is set to VglO. When the potential of N11 is VNII, the gate-source voltage of the load FET FIO is VglO-VNI1. curve 70
shows the relationship between the drain-source current flowing through the load FET FIO and the gate-source voltage VglO-V'NII, and the value of VglO-VNII is V th
When it becomes less than E, the subthreshold current I ds
Region b appears, and the current reduction rate with respect to the gate-source voltage rapidly decreases. In FIG. 1, the resistance element R
If IO is not provided, the potential of node Nil will rise until the load FET FIO is cut off, so
In FIG. 7, the point where the current shown by curve 70 is cut off, that is, vgiO-Nl 1 is V thE'
It rises until . Conventionally, the point at which the current flowing through the load FET has decreased to 5 μA per 10 μm of gate width is defined as V.
thE, and the potential rise of the node Nil stops when VglO-VNII reaches VthE, so the node Nil is set to a value higher by a voltage corresponding to VthE-VthE'. VthE
The value of -VthE' is approximately 0.1 to 0.2V, although it also depends on the element dimensions of the load FET. FIG. 7 also shows a current 71 flowing through this resistance element RIO when the resistor shown in FIG.
The current flowing through the load FET at the time of thE is 70
If the resistance value is designed so that the current flowing through the resistor and the current flowing through the resistor are equal, the rise in the potential of the node Nil will stop when VglO-VN11=VthE, that is, at the point where VN11=Vg10-VthE, Node Nil”
The "High" level is set by the difference between the gate voltage of the load FET and V thE in the general definition. Also, as can be seen from FIG. 7, the voltage-current characteristics of the curve 70 are Beyond the point, the rate of change of current with respect to voltage increases rapidly, and in this region, the load F
This means that the impedance of ET is much smaller compared to the subthreshold region.
This means that even if a small leakage current occurs in the inductive element Fil shown in FIG.
The level means that it is less susceptible to that influence. Note that in FIG. 1, the resistance element RIO is connected to the node Ni
Although VNII is inserted between Vgl and power supply VSs, VNII is
When the potential reaches O-V thE, the load FET F
As long as it is set so that the same current as the current flowing through IO flows through the resistive element RlO, it may be inserted between the node NIL and a power source other than Vss. moreover,
In FIG. 1, load FET F10. Canter FET F
il and enhancement type FET, but both or one of them can be depletion type FE.
It may be T. FIG. 8 shows another embodiment of the circuit shown in FIG. 1, in which it is used in a static memory integrated circuit. FIG. 8 shows the circuit shown in FIG. 6 with a resistive element R80. R81 was added. Resistance element R8
0, R81 correspond to the resistance element RIO in the drawing, and data line loads L80, L81 correspond to F10. FETs
F80 and F81 correspond to Fil. In FIG. 8, resistance element R80. The effects of R81 will be explained below. The read operation from the memory cell 80 in FIG.
This is done in a manner similar to that described in FIG. However, when looking at the data line d81 on the high potential side, the resistance element R81 is connected, and a current corresponding to the subthreshold current Idsb when the gate-source voltage Vgs of the voltage line load L81 is VthE is generated. Resistance element R
81, so the data l!
The potential of d81 is set to Vg8 1 - VthE, and the original value of the design is obtained. As a result, the potential difference between the data lines d81 and d80, that is, the read signal voltage, also becomes a predetermined value, and no increase in delay time occurs in the data lines. Regarding the potential of the data line d80,
By providing resistance element R80, data line load L8
The value of the current Ir flowing through 0 increases, and the data! There is a concern that the potential of d80 will be lower than before, but compared to the value of current Ir, the current flowing through resistive element R80 is negligibly small at about μA, so there is no effect that would cause a potential change. Furthermore, data line d80. Even if a small leakage current 11,..., Iln, etc. occurs to a large number of unselected memory cells connected to d81, the data line load L
81 operates in a low impedance region, the potential of the data line d81 on the high potential side varies depending on the information retention state of unselected memory cells, and this greatly reduces defects such as variation in read time. Ru. Further, FIG. 9 shows a modification of the embodiment of FIG. 8, in which data line loads L90 and L91 are connected to data line pair switch S90.
, 591, the respective data lines d90, d9l are connected to the commonly connected common bus lines B90, B91, respectively, and the data lines d90. d91 to the common bus line B90. It is intended to be smaller than that of B91 and to increase speed. In this case, the leak path resistor R91 functions similarly to the resistive element R81 described in FIG. Furthermore, FIG. 10 shows the data line load L9 in FIG.
0 and L91 are LIOOA, LIOOB and LIOIA.
LIOIB respectively, and the data lines dloo. dlo1 and common bus line BIOO. This is intended to reduce the signal amplitude of both BIOI and increase the speed. In this case as well, the leak bus resistance RIOO. RIOI is
Common path line BIOO. It is connected to the BIOI and functions similarly to that described in FIG. Effect of the Invention 1 As described above, according to the present invention, the current corresponding to the subthreshold current sdb of the load FET when the gate-source voltage Vgs of the load FET becomes V thE is transferred to the leak path resistance. By flowing the output level of the logic circuit and the data line potential of the static memory to the designed values, it is possible to reduce the variation thereof, and it is possible to realize faster logic circuits and memory LSIs than before.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, FIGS. 2 to 7 are diagrams for explaining a conventional example, and FIGS. 8 to 10 are diagrams showing other embodiments of the present invention, respectively. It is. In the figure, FIO is an enhancement type load element, Fil is an enhancement type drive element, RIO is a leak path resistance element, N10 is an input terminal, and Nil is an output terminal. NglO is a level setting potential input terminal, Vcc.
Vss is a power supply, and IH is a leak bus current. ll Figure 2nd Circle 3rd Figure Evening Figure → 1 冫r冫s (Yノ 7th 躬Vyyρ１N/! (77) Figure 8 %b Vt t th γB

Claims (1)

[Claims] 1. An enhancement type field effect transistor whose gate voltage and drain voltage are fixed at constant potential is used as a load element, an input signal according to a logic level is supplied to the gate electrode, and the drain electrode is connected to the enhancement type field effect transistor. The driver element is connected to the source electrode of the field effect transistor, and is composed of at least one field effect transistor whose source potential is connected to a constant potential, and whose source potential is constant with the source electrode of the load element consisting of the enhancement type field effect transistor. A compound semiconductor gallium arsenide integrated circuit comprising a logic circuit characterized in that a resistance element is provided between potentials. 2. The compound semiconductor gallium arsenide integrated circuit according to claim 1, wherein the current flowing through the resistance element is set to a value of about 5 μA per 10 μm gate width of the load element consisting of the enhancement type transistor. 3. A static memory integrated circuit is constructed by using the load element made of the enhancement type field effect transistor as a load element of a data line and using the drive element as a field effect transistor in each memory cell. The compound semiconductor gallium arsenide integrated circuit according to claim 1 or 2.