JPH03205891A - Ceramic circuit board - Google Patents
Ceramic circuit boardInfo
- Publication number
- JPH03205891A JPH03205891A JP136490A JP136490A JPH03205891A JP H03205891 A JPH03205891 A JP H03205891A JP 136490 A JP136490 A JP 136490A JP 136490 A JP136490 A JP 136490A JP H03205891 A JPH03205891 A JP H03205891A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- pattern
- ceramic substrate
- conductive layer
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims description 38
- 239000004020 conductor Substances 0.000 claims description 14
- 230000002411 adverse Effects 0.000 abstract description 6
- 238000010030 laminating Methods 0.000 abstract description 4
- 229910010293 ceramic material Inorganic materials 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 238000007772 electroless plating Methods 0.000 abstract description 2
- 238000003475 lamination Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 18
- 239000010949 copper Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 230000008602 contraction Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 235000021395 porridge Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
セラミック基板の貫通穴に設けられたビアが該セラミッ
ク基板の表面に形成されたパターンに直交することで当
接されるように形成されたセラミック回路基板に関し、
ビアの熱膨張による伸縮によってパターンが悪影響を受
けることのないようにすることで信頼性の向上を図るこ
とを目的とし、
貫通穴の内壁に所定の膜厚の導電層を積層し、該導電層
が積層された該貫通穴の中空部がセラミック基板の膨張
係数とほぼ同等の膨張係数を有する部材によって埋設さ
れることによりビアが形成されるように、または、貫通
穴の内壁をプラズマ加工により面荒しを行い、該プラズ
マ加工時に生じた生成物を除去後、該貫通穴に導電材を
充填させることによりビアが形成されるように、更には
、ビアがパターンに直交するように当接される当接部に
、弾性を有する導電性有機部材を設け、該導電性有機部
材を介在することで該ビアが該パターンに電気導通を有
するように接続されるように構成する。[Detailed Description of the Invention] [Summary] A ceramic circuit board formed in such a manner that vias provided in through holes of the ceramic substrate abut perpendicularly to a pattern formed on the surface of the ceramic substrate, In order to improve reliability by preventing the pattern from being adversely affected by expansion and contraction due to thermal expansion of the via, a conductive layer of a predetermined thickness is laminated on the inner wall of the through hole, and the conductive layer The hollow part of the through hole in which the ceramic substrate is laminated is buried with a member having an expansion coefficient almost equivalent to that of the ceramic substrate, so that a via is formed, or the inner wall of the through hole is surface-surfaced by plasma processing. After roughening and removing products generated during plasma processing, the through hole is filled with a conductive material to form a via, and the via is brought into contact perpendicularly to the pattern. A conductive organic member having elasticity is provided in the contact portion, and the via is electrically connected to the pattern by interposing the conductive organic member.
本発明はセラミック基板の貫通穴に設けられたビアが該
セラミック基板の表面に形成されたパターンに直交する
ことで当接されるように形成されたセラミック回路基板
に関する。The present invention relates to a ceramic circuit board formed such that vias provided in through-holes of a ceramic substrate abut perpendicularly to a pattern formed on a surface of the ceramic substrate.
半導体素子などの電子部品の実装が行われるセラミック
基板は、一般的に、セラミック基板の所定個所に設けら
れたビアがセラミック基板の表裏面に張架されたパター
ンに接続され、互いのパターン間がビアによって電気導
通を有するように接続されている。Ceramic substrates on which electronic components such as semiconductor devices are mounted are generally connected to vias provided at predetermined locations on the ceramic substrate to patterns stretched between the front and back surfaces of the ceramic substrate, and the patterns are connected to each other. They are electrically connected by vias.
一方、このような半導体素子などの電子部品は、近年、
高密度実装化、高速化が推進されるようになり、これら
の高密度実装化、高速化に伴い、セラミック基板には微
細なパターンが形成されるようになり、当然、これらの
パターンを接続するビアも微細化される傾向にある。On the other hand, in recent years, electronic components such as semiconductor elements have
High-density packaging and high speeds are being promoted, and with these high-density packaging and high speeds, fine patterns are being formed on ceramic substrates, and it is natural to connect these patterns. Vias are also becoming smaller.
したがって、このようなパターンおよびビアの微細化が
行われても、パターンとビアとの接続に断線などの障害
が生じることのないように、確実に接続され、信頼性の
高いことが重要となる。Therefore, even with such miniaturization of patterns and vias, it is important that the connections between patterns and vias be reliable and reliable to avoid disconnections or other problems. .
従来は、第７図の（ａ）（ｂ）の従来の側面断面図に示
すように構成されていた。Conventionally, the structure was as shown in the conventional side sectional views of FIGS. 7(a) and 7(b).
第７図の（ａ）に示すように、セラミック基板ｌの所定
個所に加工された貫通穴２に導電材７を充填することで
ビア３が設けられ、セラミック基板ｌの表裏面１Ａ，Ｉ
Ｂに張架されたパターン４がビア３を介在することで電
気導通を有するように接続されている。As shown in FIG. 7(a), vias 3 are provided by filling conductive material 7 into through holes 2 formed at predetermined locations on the ceramic substrate l, and
The patterns 4 stretched over B are connected to each other through vias 3 so as to have electrical continuity.
このようなビア３は、通常、導体ペーストを貫通穴２に
充填させ、所定温度の加熱によって焼成することで形成
され、また、パターン４はエッチング処理によって表裏
面１Ａ，ＩＢに導体層を積層することで形成される。Such a via 3 is usually formed by filling the through hole 2 with a conductive paste and baking it by heating at a predetermined temperature, and the pattern 4 is formed by laminating a conductive layer on the front and back surfaces 1A and IB by an etching process. It is formed by
しかし、このようなビア３に充填される導電材７は、銅
Ｃｕによって構成されているため、セラミック基板ｌが
、例えば、ボンディング処理などによって加熱された時
、ビア３とセラミック基板１との熱膨張係数の差によっ
て伸縮に違いが生じ、第７図の（ｂ）に示すように、セ
ラミック基板ｌの表裏面１Ａ， １Ｂに形成されたパタ
ーン４に亀裂ｌＯが発生することがある。However, since the conductive material 7 filled in such a via 3 is made of copper Cu, when the ceramic substrate l is heated by, for example, a bonding process, the heat between the via 3 and the ceramic substrate 1 is The difference in expansion coefficient causes a difference in expansion and contraction, and as shown in FIG. 7(b), cracks 1O may occur in the pattern 4 formed on the front and back surfaces 1A and 1B of the ceramic substrate 1.
したがって、パターン４間に於ける電気導通が断線され
たり、または、電気抵抗が増加し、電気特性に悪影響を
及ぼす問題を有していた。Therefore, there is a problem in that electrical continuity between the patterns 4 is broken or electrical resistance increases, which adversely affects electrical characteristics.
そこで、本発明では、ビアの熱膨張による伸縮によって
パターンが悪影響を受けることのないようにすることで
信頼性の向上を図ることを目的とする。Therefore, an object of the present invention is to improve reliability by preventing patterns from being adversely affected by expansion and contraction due to thermal expansion of vias.
第１図は本第１の発明の原理説明図で、第２図は本第２
の発明の原理説明図で、第３図は本第３の発明の原理説
明図である。Figure 1 is an explanatory diagram of the principle of the first invention, and Figure 2 is an illustration of the principle of the second invention.
FIG. 3 is a diagram explaining the principle of the third invention.
第１図〜第３図に示すように、貫通穴２の内壁２Ａに所
定の膜厚の導電層５を積層し、該導電層５が積層された
該貫通穴２の中空部２Ｂがセラミック基板の膨張係数と
ほぼ同等の膨張係数を有する部材６によって埋設される
ことによりビア３が形成されるように、または、貫通穴
２の内壁２Ａをプラズマ加工により面荒しを行い、該プ
ラズマ加工時に生じた生成物を除去後、該貫通穴２に導
電材７を充填させることによりビア３が形成されるよう
に、更には、ビア３がパターン４に直交するように当接
される当接部８に、弾性を有する導電性有機部材９を設
け、該導電性有機部材９を介在することて該ビア３が該
パターン４に電気導通を有するように接続されるように
構成する。As shown in FIGS. 1 to 3, a conductive layer 5 having a predetermined thickness is laminated on the inner wall 2A of the through hole 2, and the hollow part 2B of the through hole 2 on which the conductive layer 5 is laminated is a ceramic substrate. The inner wall 2A of the through hole 2 is roughened by plasma processing so that the via 3 is formed by being buried with a member 6 having an expansion coefficient substantially equal to that of After removing the generated product, the through hole 2 is filled with a conductive material 7 to form a via 3. Furthermore, a contact portion 8 is formed in which the via 3 is brought into contact with the pattern 4 perpendicularly. A conductive organic member 9 having elasticity is provided, and the via 3 is electrically connected to the pattern 4 through the conductive organic member 9.
このように構成することによって前述の課題は解決され
る。With this configuration, the above-mentioned problem is solved.
即ち、貫通穴２の内壁２Ａに導電層５を積層し、貫通穴
２に導電層５を積層することで形成された中空部２Ｂに
は熱膨張係数の小さい部材６を充填させることでビア３
を形成し、ビア３の熱膨張が部材６の内部応力によって
抑止されるように、または、貫通穴２の内壁２Ａをプラ
ズマ加工によって面荒しを行い、導電材７の充填によっ
てビア３を形成するようにし、ビア３の熱膨張が内壁２
Ａの摩擦力によって抑止されるようにしたものである。That is, the conductive layer 5 is laminated on the inner wall 2A of the through hole 2, and the hollow portion 2B formed by laminating the conductive layer 5 in the through hole 2 is filled with a member 6 having a small coefficient of thermal expansion, thereby forming the via 3.
or the inner wall 2A of the through hole 2 is roughened by plasma processing, and the via 3 is formed by filling with the conductive material 7. so that the thermal expansion of via 3 is
It is designed to be restrained by the frictional force of A.
したがって、いずれの場合でもビア３に於ける熱膨張が
なくなり、ビア３がパターン４の形或面に突出すること
がないようにすることができる。Therefore, in either case, there is no thermal expansion in the vias 3, and the vias 3 can be prevented from protruding into a certain surface of the pattern 4.
また、ビア３とパターン４との当接部８に弾性を有する
導電性有機部材９を設けるようにし、ビア３が熱膨張に
よってパターン４の形成面に突出されても、その突出が
導電性有機部材９によって吸収させることにより、パタ
ーン４の形成に悪影響を及ぼすことのないようにしたも
のである。In addition, an elastic conductive organic member 9 is provided at the abutting portion 8 between the via 3 and the pattern 4, so that even if the via 3 protrudes onto the pattern 4 formation surface due to thermal expansion, the protrusion will not be caused by the conductive organic member 9. By absorbing it by the member 9, the formation of the pattern 4 is prevented from being adversely affected.
したがって、従来のような熱膨張によるパターン４の断
線などの発生を防ぐことが行え、信頼性の向上が図れる
。Therefore, occurrence of disconnection of the pattern 4 due to thermal expansion as in the conventional case can be prevented, and reliability can be improved.
以下本発明を第４図〜第６図を参考に詳細に説明する。 The present invention will be explained in detail below with reference to FIGS. 4 to 6.
第４図は本第１の発明による一実施例の説明図で、（ａ
）は斜視図． （ｂｌ）〜（ｂ５）は製造工程図，第５
図は本第２の発明による一実施例の説明図で、（ａ）は
斜視図，（ｂｌ）〜（ｂ５）は製造工程図，第６図は本
第３の発明による一実施例の説明図で、（ａ）は斜視図
，（ｂｌ）〜（ｂ６）は製造工程図である。FIG. 4 is an explanatory diagram of an embodiment according to the first invention, (a
) is a perspective view. (bl) to (b5) are manufacturing process diagrams, 5th
The figures are explanatory diagrams of an embodiment according to the second invention, (a) is a perspective view, (bl) to (b5) are manufacturing process diagrams, and FIG. 6 is an explanation of an embodiment according to the third invention. In the figures, (a) is a perspective view, and (bl) to (b6) are manufacturing process diagrams.
全図を通して、同一符号は同一対象物を示す。The same reference numerals indicate the same objects throughout the figures.
第４図の（ａ）に示すように、セラミック基板１の所定
個所に設けられた貫通穴２の内壁２Ａに導電層５を積層
し、導電層５の積層が行われた貫通穴２の中空部２Ｂに
は熱膨張係数の小さい部材６を充填させることてビア３
を形成し、セラミック基板ｌの表裏面１Ａ， ＩＢに形
成されたパターン４に接続が行われるように構成したも
のであるっこのよな構成は、第４図の（ｂｌ）〜（ｂ５
）に示す製造工程によって製造することが行える。As shown in FIG. 4(a), a conductive layer 5 is laminated on the inner wall 2A of the through hole 2 provided at a predetermined location on the ceramic substrate 1, and the conductive layer 5 is laminated in the hollow of the through hole 2. The via 3 is filled in the portion 2B with a member 6 having a small coefficient of thermal expansion.
This configuration is configured such that connections are made to the patterns 4 formed on the front and back surfaces 1A and IB of the ceramic substrate l.
) can be manufactured by the manufacturing process shown in FIG.
先づ、（ｂｌ）に示すように、セラミック基板１の所定
個所に貫通穴２をレーザ加工によって穴明けを行い、（
ｂ２）に示すように、無電解メッキによってセラミック
基板１の貫通穴２の内壁２Ａおよび表裏面１Ａ， ＩＢ
に厚み５〜６μｍの銅Ｃｕなどによる導電層５の積層を
行い、導電層５が積層されることで形成された貫通穴２
の中空部２Ｂには膨張係数の小さい部材６の充填を行う
。First, as shown in (bl), through holes 2 are drilled at predetermined locations on the ceramic substrate 1 by laser processing.
b2), the inner wall 2A of the through hole 2 of the ceramic substrate 1 and the front and back surfaces 1A, IB are coated by electroless plating.
A conductive layer 5 made of copper or the like with a thickness of 5 to 6 μm is laminated on the top of the conductive layer 5, and a through hole 2 is formed by laminating the conductive layer 5.
The hollow portion 2B is filled with a member 6 having a small expansion coefficient.
この場合、実際には、部材６としてポリイミドを充填，
加熱し、硬化させ（ｂ３）に示すように、貫通穴２を埋
設した。In this case, the member 6 is actually filled with polyimide,
It was heated and cured, and a through hole 2 was embedded as shown in (b3).
次に、（ｂ４）に示すように、セラミック基板１の表裏
面１Ａ， ＩＢを研磨することで表裏面１Ａ，ＩＢに積
層された導電層５を除去することによってビア３の形成
を行い、エッチングなどによって（ｂ５）に示すように
ビア３に接続されるパターン４の張架が行われるように
製造することができる。Next, as shown in (b4), the conductive layer 5 laminated on the front and back surfaces 1A and IB of the ceramic substrate 1 is removed by polishing to form the via 3, and etching is performed. As shown in (b5), the pattern 4 connected to the via 3 can be fabricated in such a manner that the pattern 4 is stretched.
この場合、導電層５はリンク状に形成され、そのリング
の外輪がセラミック基板ｌに密着され、内輪が部材６に
密着されることになり、また、セラミック材の熱膨張係
数は４ＸＩＯ−８で、銅Ｃｕの熱膨張係数は１２Ｘ１０
−’であるのに対してポリイミドの熱膨張係数は４Ｘｌ
Ｏ−’で、銅Ｃｕより小さく、セラミック材とほぼ同等
の値であるため、導電層５の熱膨張による伸びは殆ど生
じなくすることが行える。In this case, the conductive layer 5 is formed in the shape of a link, the outer ring of the ring is tightly attached to the ceramic substrate l, and the inner ring is closely attached to the member 6, and the thermal expansion coefficient of the ceramic material is 4XIO-8. , the thermal expansion coefficient of copper Cu is 12X10
-', whereas the coefficient of thermal expansion of polyimide is 4Xl
Since the value is O-', which is smaller than copper Cu and approximately the same as that of a ceramic material, elongation due to thermal expansion of the conductive layer 5 can be almost prevented.
したがって、熱膨張によってビア３の導電層５がパター
ン４を持ち上げる方向に膨張することが抑止され、殆ど
導電層５に於けるセラミック基板１の厚み方向に対する
熱膨張がなく、熱膨張によるパターン４に対する影響を
なくすことができ、前述のような断線障害がなくなる。Therefore, the conductive layer 5 of the via 3 is prevented from expanding in the direction of lifting the pattern 4 due to thermal expansion, and there is almost no thermal expansion in the conductive layer 5 in the thickness direction of the ceramic substrate 1, and the conductive layer 5 of the via 3 is prevented from expanding in the direction of lifting the pattern 4 due to thermal expansion. This eliminates the effect of wire breakage as described above.
また、第５図の（ａ）の場合は、セラミック基板ｌの所
定個所に貫通穴２をレーザ加工によって穴明けを行い、
その貫通穴２の内壁２Ａには面荒しを行い、導電材７を
充填することによってビア３を形成し、セラミック基板
ｌの表裏面１Ａ，ＩＢに形成されたパターン４に接続が
行われるように構成したものである。In the case of (a) in FIG. 5, a through hole 2 is drilled at a predetermined location on the ceramic substrate l by laser processing.
The inner wall 2A of the through hole 2 is roughened and filled with a conductive material 7 to form a via 3, so that connection can be made to the pattern 4 formed on the front and back surfaces 1A and IB of the ceramic substrate l. It is composed of
？のよな構成は、第５図の（ｂｌ）〜（ｂ５）に示す製
造工程によって製造することが行える。? Such a configuration can be manufactured by the manufacturing steps shown in (bl) to (b5) of FIG. 5.
先づ、（ｂ１）に示すように、セラミック基板ｌの所定
個所に貫通穴２をレーザ加工によって穴明けを行い、硝
酸ｌに対してフッ酸３を加えた、酸性処理液に約１０分
浸し、穴明けに際して貫通穴２の内壁２Ａに付着したド
ロス１１の除去を行い、酸素が７５％，フロンｌ４が２
５％の雰囲気中でセラミック基板ｌを約ＩＨのプラズマ
処理を行い、（ｂ２）に示すように、貫通穴２の内壁２
Ａにプラズマ生成物ＳｉＯ■ｌ２の生成と同時に、内壁
２Ａに凹凸を形成させる面荒しを行う。First, as shown in (b1), through holes 2 are drilled at predetermined locations on the ceramic substrate l by laser machining, and the substrate is immersed in an acidic treatment solution containing 3 parts of hydrofluoric acid to 1 part of nitric acid for about 10 minutes. During drilling, the dross 11 attached to the inner wall 2A of the through hole 2 was removed, and the oxygen content was 75% and the Freon l4 content was 2.
The ceramic substrate l was subjected to approximately IH plasma treatment in a 5% atmosphere, and as shown in (b2), the inner wall 2 of the through hole 2
Simultaneously with the generation of the plasma product SiO2A, surface roughening is performed to form irregularities on the inner wall 2A.
次に、硝酸に約１０分浸し、（ｂ３）に示すように、プ
ラスマ生成物３１０２ １２を除去し、内壁２Ａの凹凸
に形成された面荒しの個所を露出させ、（ｂ４）に示す
ように、銅ペーストなどの導電材７の充填を行い、焼成
することでビア３の形成を行う。Next, it is immersed in nitric acid for about 10 minutes to remove the plasma product 3102 12 as shown in (b3), expose the roughened areas formed on the unevenness of the inner wall 2A, and as shown in (b4). The vias 3 are formed by filling with a conductive material 7 such as copper paste and firing.
最後に、（ｂ５）に示すように、エッチングによってセ
ラミック基板ｌの表面１Ａにパターン４の形成を行い、
ビア３にパターン４が接続されるようにすることができ
る。Finally, as shown in (b5), a pattern 4 is formed on the surface 1A of the ceramic substrate l by etching,
The pattern 4 can be connected to the via 3.
この場合は、ビア３を形成する導電材７が内壁２Ａの凹
凸に噛み合うことで強固に貫通穴２に固着されているた
め、導電材７が熱膨張によってパターン４の形成された
表面ｌＡ側に突出することがないようにすることができ
る。In this case, since the conductive material 7 forming the via 3 is firmly fixed to the through hole 2 by engaging with the unevenness of the inner wall 2A, the conductive material 7 is thermally expanded to the surface 1A side where the pattern 4 is formed. You can prevent it from sticking out.
したがって、前述と同様に、ビア３の熱膨張によるパタ
ーン４に対する影響をなくすことができ、パターン４の
断線障害などをなくすことができる。Therefore, as described above, it is possible to eliminate the influence of the thermal expansion of the via 3 on the pattern 4, and it is possible to eliminate problems such as disconnection of the pattern 4.
更に、第６図の（ａ）の場合は、セラミック基板ｌの所
定個所に貫通穴２をレーザ加工によって穴明けを行い、
その貫通穴２に導電材７を充填することによってビア３
を形成し、パターン４の形成はビア３との当接部８が弾
性を有する導電性有機材９によって行われるように構成
したものである。Furthermore, in the case of FIG. 6(a), through holes 2 are drilled at predetermined locations on the ceramic substrate l by laser processing,
By filling the through hole 2 with a conductive material 7, the via 3
The pattern 4 is formed such that the contact portion 8 with the via 3 is made of an elastic conductive organic material 9.
このような構成は、第６図の（ｂｌ）〜（ｂ６）に示す
工程によって製造することができる。Such a structure can be manufactured by the steps shown in (bl) to (b6) in FIG.
先づ、（ｂｌ）に示すように、セラミック基板ｌの所定
個所に貫通穴２をレーザ加工によって穴明けを行い、（
ｂ２）に示すように、貫通穴２には銅ぺ一ストなどの導
電材７を充填，焼成し、ビア３の形成を行い、エッチン
グによってパターン４の形成を（ｂ３）に示すように形
成する。First, as shown in (bl), through holes 2 are drilled at predetermined locations on the ceramic substrate l by laser processing.
As shown in b2), the through hole 2 is filled with a conductive material 7 such as copper paste and fired to form a via 3, and etched to form a pattern 4 as shown in (b3). .
次に、（ｂ４）に示すように、パターン４とビア３とが
当接された当接部８に座グリ穴４Ａを加工し、ビア３を
露出させ、（ｂ５）に示すように、座グリ穴４Ａにはゴ
ムシ一ト状の例えば、エラスティクコネクタなどの弾性
を有する導電性有機部材９の挿入を行う。Next, as shown in (b4), a counterbore hole 4A is machined in the contact part 8 where the pattern 4 and the via 3 are in contact to expose the via 3, and as shown in (b5), A conductive organic member 9 having elasticity, such as a rubber sheet-shaped elastic connector, is inserted into the bore hole 4A.
この場合の座グリ穴４Ａの直径はビア３の直径より大き
くする必要がある。In this case, the diameter of the counterbore hole 4A needs to be larger than the diameter of the via 3.
そこで、パターン４とビア３と接続が導電性有機部材９
とを介して行われ、導電性有機部材９を介在することで
パターン４とビア３と間の電気導通が行われるようにす
ることができる。Therefore, the pattern 4 and the via 3 are connected to the conductive organic member 9.
By interposing the conductive organic member 9, electrical continuity can be established between the pattern 4 and the via 3.
また、パターン４の上層に更に、パターン４−１を積層
する場合は、（ｂ６）に示すように、パターン４の上層
に絶縁層ｌ３を積層し、その上にパターン４−１を形成
するようにすることが行える。In addition, when pattern 4-1 is further laminated on the upper layer of pattern 4, as shown in (b6), an insulating layer l3 is laminated on the upper layer of pattern 4, and pattern 4-1 is formed on it. can be done.
したがって、このような導電性有機部材９を設けると、
熱膨張によってビア３が突出しても、その突出は導電性
有機部材９の収縮によって吸収されることになり、パタ
ーン４および４−１に全く影響することがないようにす
ることができる。Therefore, when such a conductive organic member 9 is provided,
Even if the via 3 protrudes due to thermal expansion, the protrusion is absorbed by the contraction of the conductive organic member 9, so that it does not affect the patterns 4 and 4-1 at all.
以上説明したように、本発明では、ビアの熱膨張による
伸縮を抑止するか、または、ビアの熱膨張による突出を
弾性材の導電性有機部材によって吸収させることによっ
てビアに接続されるパターンに悪影響が及ぼすことがな
いようにすることが行える。As explained above, in the present invention, by suppressing the expansion and contraction of the via due to thermal expansion, or by absorbing the protrusion due to the thermal expansion of the via with a conductive organic member made of an elastic material, it is possible to adversely affect the pattern connected to the via. Measures can be taken to ensure that this does not occur.
したがって、従来のような、熱膨張によりパターンに断
線障害が生じるようなことが防げ、信頼性の向上が図れ
、実用的効果は大である。Therefore, it is possible to prevent disconnection of the pattern due to thermal expansion, which is the case in the past, and to improve reliability, which has a great practical effect.
第１図は本第１の発明の原理説明図，
第２図は本第２の発明の原理説明図，
第３図は本第３の発明の原理説明図，
第４図は本第１の発明による一実施例の説明図で、（ａ
）は斜視図，（ｂｌ）〜（ｂ５）は製造工程図，
第５図は本第２の発明による一実施例の説明図で、（ａ
）は斜視図， （ｂｌ）〜（ｂ５）は製造工程図，
第６図は本第３の発明による一実施例の説明図で、（ａ
）は斜視図， （ｂｌ）〜（ｂ６）は製造工程図，
第７図の（ａ）（ｂ）は従来の側面断面図を示す。
図において、
ｌはセラミック基板， ２は貫通穴，
３はビア， ４はパターン，５は導電層，
６は部材，
７は導電材， ８は当接部，９は導電性有機
部材． １Ａは表面，１Ｂは裏面，
２Ａは内壁，２Ｂは中空部を示す。
本第１の発明の原理説明図
第１図
３ヒ′゛ア
本第２の楚８月の原刊桔も期図
第２口
本第３の余明０原理髭明図
第３ 図
（昆）
（ｂ３）
＄第１の紫８月１二よろ一笑施ｇＩ＋の説明図第４ 図
（α）
（ｂ３）
，ｔ粥２の茫明ｔ；よろ一実施伊ｊの説明図本第３の茫
明（二よろ一笑那例の妃明閃消６ 図
３ビア
（α）
（ｂ）
ｑ１どヒ来の錦！η面断面ｂ？１
第７図Fig. 1 is an explanatory diagram of the principle of the first invention, Fig. 2 is an explanatory diagram of the principle of the second invention, Fig. 3 is an explanatory diagram of the principle of the third invention, and Fig. 4 is an explanatory diagram of the principle of the third invention. An explanatory diagram of an embodiment according to the invention, (a
) is a perspective view, (bl) to (b5) are manufacturing process diagrams, and FIG. 5 is an explanatory diagram of an embodiment according to the second invention.
) is a perspective view, (bl) to (b5) are manufacturing process diagrams, and FIG. 6 is an explanatory diagram of an embodiment according to the third invention.
) is a perspective view, (bl) to (b6) are manufacturing process diagrams, and FIGS. 7(a) and 7(b) are conventional side sectional views. In the figure, l is a ceramic substrate, 2 is a through hole, 3 is a via, 4 is a pattern, 5 is a conductive layer,
6 is a member, 7 is a conductive material, 8 is a contact portion, and 9 is a conductive organic member. 1A is the front side, 1B is the back side,
2A indicates an inner wall, and 2B indicates a hollow portion. Illustration of the principles of the first invention. ) (b3) $ 1st Purple August 1 2 Yoro Ichi Sho g I + Explanatory Diagram 4 Figure (α) (b3) , t porridge 2 no dazzling t; Dazzling light (Niyoro Ichisho Nabe no Himei flashing 6 Figure 3 Via (α) (b) q1 Dohirai no Nishiki! η plane cross section b?1 Figure 7
Claims (1)
たパターン（４）と、該セラミック基板（１）の貫通穴
（２）に設けられたビア（３）とを備え、該ビア（３）
が該パターン（４）に直交するように当接され、互いに
電気導通を有するように接続されるセラミック回路基板
であって、 前記貫通穴（２）の内壁（２Ａ）に所定の膜厚の導電層
（５）を積層し、該導電層（５）が積層された該貫通穴
（２）の中空部（２Ｂ）がセラミック基板（１）の膨張
係数とほぼ同等の膨張係数を有する部材（６）によって
埋設されることにより前記ビア（３）が形成されること
を特徴とするセラミック回路基板。 〔２〕セラミック基板（１）の表面（１Ａ）に形成され
たパターン（４）と、該セラミック基板（１）の貫通穴
（２）に設けられたビア（３）とを備え、該ビア（３）
が該パターン（４）に直交するように当接され、互いに
電気導通を有するように接続されるセラミック回路基板
であって、 前記貫通穴（２）の内壁（２Ａ）をプラズマ加工により
面荒しを行い、該プラズマ加工時に生じた生成物を除去
後、該貫通穴（２）に導電材（７）を充填させることに
より前記ビア（３）が形成されることを特徴とするセラ
ミック回路基板。 〔３〕セラミック基板（１）の表面（１Ａ）に形成され
たパターン（４）と、該セラミック基板（１）の貫通穴
（２）に導電材（７）を充填させることで設けられたビ
ア（３）とを備え、該ビア（３）が該パターン（４）に
直交するように当接され、互いに電気導通を有するよう
に接続されるセラミック回路基板であって、 前記ビア（３）が前記パターン（４）に直交するように
当接される当接部（８）に、弾性を有する導電性有機部
材（９）を設け、該導電性有機部材（９）を介在するこ
とで該ビア（３）が該パターン（４）に電気導通を有す
るように接続されることを特徴とするセラミック回路基
板。[Claims] [1] A pattern (4) formed on the surface (1A) of the ceramic substrate (1), and a via (3) provided in the through hole (2) of the ceramic substrate (1). and the via (3)
are in contact with the pattern (4) perpendicularly and are connected to each other so as to have electrical continuity, the inner wall (2A) of the through hole (2) having a predetermined thickness of conductive film. A member (6) in which the layers (5) are laminated, and the hollow part (2B) of the through hole (2) on which the conductive layer (5) is laminated has an expansion coefficient substantially equal to that of the ceramic substrate (1). ), wherein the via (3) is formed by embedding the via (3). [2] Comprising a pattern (4) formed on the surface (1A) of the ceramic substrate (1) and a via (3) provided in the through hole (2) of the ceramic substrate (1), the via ( 3)
are abutted perpendicularly to the pattern (4) and are connected to each other so as to have electrical continuity, the inner wall (2A) of the through hole (2) being surface roughened by plasma processing. A ceramic circuit board characterized in that the via (3) is formed by filling the through hole (2) with a conductive material (7) after removing the products generated during the plasma processing. [3] The pattern (4) formed on the surface (1A) of the ceramic substrate (1) and the via provided by filling the through hole (2) of the ceramic substrate (1) with a conductive material (7) (3), the via (3) is brought into contact with the pattern (4) perpendicularly and connected to each other so as to have electrical continuity, the via (3) being A conductive organic member (9) having elasticity is provided on the contact portion (8) that abuts perpendicularly to the pattern (4), and by interposing the conductive organic member (9), the via (3) is electrically connected to the pattern (4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP136490A JPH03205891A (en) | 1990-01-08 | 1990-01-08 | Ceramic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP136490A JPH03205891A (en) | 1990-01-08 | 1990-01-08 | Ceramic circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03205891A true JPH03205891A (en) | 1991-09-09 |
Family
ID=11499446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP136490A Pending JPH03205891A (en) | 1990-01-08 | 1990-01-08 | Ceramic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03205891A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9148956B2 (en) | 2012-04-27 | 2015-09-29 | Seiko Epson Corporation | Base substrate, electronic device, and method of manufacturing base substrate |
-
1990
- 1990-01-08 JP JP136490A patent/JPH03205891A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9148956B2 (en) | 2012-04-27 | 2015-09-29 | Seiko Epson Corporation | Base substrate, electronic device, and method of manufacturing base substrate |
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