JP2002319767A - Multilayer printed board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed board capable of improving the connection reliability of a via hole connection portion. SOLUTION: Forming dummy via holes 6, 8 that are not connected to circuit patterns sandwiching an insulating layer and are larger than 1 around a via hole for electrically connecting the circuit patterns can lessen a thermally extending/contracting stress of the insulating layer applied to a via hole plating layer, thus preventing the via hole plated layer from being broken or cracked or the via hole plated layer from being separated from an upper first circuit pattern bonding portion of a bottom part, and thus improve bonding reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed circuit board having improved connection strength between a via hole and a via hole plating layer.

[0002]

2. Description of the Related Art In general, a printed circuit board used for various electric products has been developed as a multilayer printed circuit board having a structure in which a circuit pattern is multi-layered with an increase in circuit density and an insulating layer is interposed therebetween. Has been done.

[0003] This multilayer printed board is formed by sequentially laminating a circuit pattern and an insulating layer on both sides of an insulating inner layer plate as a base material. The electrical connection of the circuit patterns of each layer can be electrically connected at an interlayer connection portion formed by drilling an insulating layer between the circuit patterns as necessary, or a circuit on the opposite side of the inner layer plate. When connecting to a pattern, electrical connection between both surfaces is made through through-holes formed in the inner layer plate at an early stage of manufacturing.

FIG. 1 is an enlarged sectional view of the above-mentioned conventional multilayer printed circuit board. Reference numeral 1 denotes an inner layer plate, which is formed by forming an insulating material such as glass epoxy resin into a plate shape. Here, a multilayer printed circuit board having a four-layer structure in which one surface is formed of two layers is shown (in the illustrated example, FIG. Since the structure of the lower two layers is the same as that of the upper two layers, the description is omitted.)
The electrical connection between the required circuit patterns is made by forming a via hole 5 reaching the target circuit pattern by ablation of an insulating layer by, for example, a laser beam or by photolithography, and simultaneously forming the via hole 5 on the inner wall surface at the time of pattern formation. The connection is made by forming a via-hole plating layer 9 to be formed. In this illustrated example,
Electrical connection between the upper first layer circuit pattern 2 and the upper second layer circuit pattern 10 is made via the via hole plating layer 9.

In recent electronic circuits, there has been a demand for a reduction in the size of the line width, the thickness of the plating layer, and the diameter of the via hole due to a demand for a reduction in the size.
This type of multilayer printed circuit board is generally exposed to temperature rise and fall with a high temperature difference due to the flow of electricity, depending on the use environment, and thus the plating film is subjected to thermal stress accompanying the temperature rise and fall. For example, the thickness of the insulating layer 4 is about 20 μm,
The thickness of the plating layer forming each pattern is about 10 μm, and both are very small. However, the insulating layer also undergoes thermal expansion and contraction in the vertical and horizontal directions due to the temperature rise and fall as described above. In this case, there is no problem if the amount of expansion and contraction is within the allowable range of the strength of the via hole plating layer. However, if the expansion amount exceeds this allowable range, a large thermal stress is applied to the via hole plating layer, and this plating layer and the upper first layer circuit There is a problem that a crack or a break occurs at a connection portion with the pattern, and the reliability of bonding is deteriorated.

[0006] In particular, the insulating layer thermally expands and contracts by about 20 to 25% in thickness under a general use environment, depending on the temperature difference, which causes a reduction in the reliability of bonding. The problem of such cracks and breakage increases as the length of the via-hole plating layer, that is, as the depth of the via-hole increases, increases the amount of thermal expansion and contraction.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems and has been made in order to solve the problems effectively. The purpose of the present invention is to improve the connection reliability of a via-hole connection portion. To provide a multi-layer printed circuit board.

[0008]

According to the present invention, a circuit pattern and an insulating layer are sequentially laminated on the surface of an inner layer plate, and a desired circuit pattern is electrically connected via a via-hole plating layer. In a multi-layered printed circuit board that is to be electrically connected, a via hole for connecting a desired circuit pattern and preferably a via hole (dummy via hole) that is not connected to one or more circuit patterns are provided around the via hole. This alleviates the stress due to thermal expansion and contraction, so that the thermal stress applied to the via hole plating layer is dispersed. Accordingly, the connection strength is correspondingly increased, and the connection reliability between circuit patterns can be improved.

Such via holes that are not electrically connected are formed by the same laser beam or photolithography technique as the via holes that connect a desired circuit pattern.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multilayer printed circuit board according to the present invention and a method for manufacturing the same will be described below with reference to the accompanying drawings.

FIG. 2 is a partially enlarged sectional view showing an example of the multilayer printed board of the present invention, and FIG. 3 is a view of the printed board shown in FIG. 2 as viewed from above. The same parts as those in the conventional structure described above are denoted by the same reference numerals and described.

The inner layer plate 1 in the figure is formed of an insulating material such as glass epoxy resin in the form of a plate. Here, a multilayer printed board having a four-layer structure having two layers on each side is shown. In the illustrated example, the structure of the lower two layers is the same as that of the upper two layers, so that the description is omitted.) Centering on the inner layer plate 1,
Above this, an upper first layer circuit pattern made of, for example, copper foil,
The upper second layer circuit pattern is laminated via an insulating layer.

The electrical connection between the required circuit patterns is made by forming a via hole 5 reaching the target circuit pattern by, for example, ablating the insulating layer with a laser beam or by photolithography, and forming the via hole 5 on the inner wall surface. The connection is made by forming a via hole plating layer 9 which is formed simultaneously with the pattern formation. In the illustrated example, the upper first layer circuit pattern 2 and the upper
Electrical connection with the layer circuit pattern 10 is made via the via-hole plating layer 9. Then, at least one via hole 6 (dummy via hole) that is not electrically connected is provided around the via hole 5 that connects a desired circuit pattern.

The dummy via hole is formed by the same laser beam or photolithography technique as the via hole for connecting a desired circuit pattern. The dummy via hole is located in a range of about 0.01 to 50 mm in radius around the via hole. Here, the thickness of the insulating layer 4 is about 20 μm, and the thickness of the plating layer forming each pattern is about 5 to 20 μm.
μm, and the diameter of the bottom of the via hole is about 5 to 20 μm. Note that these numerical values are merely examples, and the present invention is not limited to these numerical values. Also, the electronic component is mounted on the land (not shown) of the upper second circuit pattern 3, which is the outermost layer.

When a thermal stress accompanying thermal expansion and contraction is applied to the multilayer printed circuit board formed in this way, for example, the via hole plating layer formed on the inner wall surface of the via hole also undergoes thermal expansion and contraction of the insulating layer in the lateral direction. As a result, a thermal stress is applied, and a load for breaking the plating layer is applied. In this case, one or a plurality of dummy via holes formed around the via hole plating layer relieve the thermal expansion and contraction stress of the insulating layer applied to the via hole plating layer. Cracks can be prevented from occurring, and the joint between the via hole plating layer and the upper first layer circuit pattern on the bottom can be prevented from peeling off. Therefore,
The reliability of the connection between the circuit patterns can be improved.

A method of manufacturing a printed circuit board having a structure in which dummy via holes are formed will be described with reference to FIG. First,
As shown in FIG. 4 (A), for example, copper foil is formed on both surfaces of the inner layer plate 1 by electroless plating on both surfaces thereof, and the upper and lower first layer circuit patterns 2 and 2A are pattern-etched into a predetermined shape. And the upper and lower dummy via hole lands 3.3A are respectively formed.

Next, as shown in FIG. 4B, for example, a resin is applied to the entire front and back surfaces of the intermediate body and cured to form an upper insulating layer 4 and a lower insulating layer 4A.

Next, as shown in FIG. 4C, the upper insulating layer and the lower insulating layer are ablated at positions corresponding to the copper foil circuit patterns 2 and 2A by, for example, a laser beam, or via holes are formed by photolithography. 5.5A
Is formed to expose the copper foil circuit pattern.

Next, as shown in FIG. 4C, one or more dummy via holes 6 and 6A are formed around the via hole for connecting the circuit pattern by laser light, or formed by photolithography. I do. However, in the cross-sectional view of FIG. 4C, two dummy via holes are formed.

Next, as shown in FIG. 4D, plating layers 7.7A are formed on the surfaces of the upper insulating layer and the lower insulating layer, the via holes, and in the via holes. This plating layer is usually formed by electroless plating, but may be used in combination with electrolytic plating. At this time, the plating layer formed in the via hole is formed up to the surface of the copper foil circuit pattern exposed in the hole.

Next, as shown in FIG. 4E, a wiring circuit pattern is formed by patterning the plating layers formed on the surfaces of the upper and lower insulating layers, thereby completing a multilayer printed wiring board. The wiring circuit pattern is formed by etching, and the pattern is formed while leaving the plating layer also in the dummy via hole.

The present invention is not limited to the embodiment described above and shown in the drawings, and various modifications can be made without departing from the spirit of the invention.

Although the printed wiring board of the embodiment has been described for a case where the wiring pattern has four layers, the present invention can also be widely applied to a printed wiring board having a multi-layered wiring pattern having six layers and eight layers.

[0024]

As described above, according to the multilayer printed circuit board of the present invention, via holes for electrically connecting circuit patterns sandwiching an insulating layer, and preferably one or more dummy via holes are formed around the via holes. Thereby, the thermal expansion stress of the insulating layer applied to the via hole plating layer can be reduced. As a result, it is possible to prevent the via-hole plating layer from being broken or cracked, and it is also possible to prevent the joint portion between the via-hole plating layer and the upper first layer circuit pattern from being peeled off from the bottom, so that the bonding can be prevented. Reliability can be improved.

[0025]

[Brief description of the drawings]

FIG. 1 is an enlarged sectional view showing a conventional multilayer printed circuit board.

FIG. 2 is a partially enlarged cross-sectional view illustrating an example of a multilayer printed board according to the present invention.

FIG. 3 is a partial enlarged view from above showing an example of the multilayer printed board of the present invention.

FIG. 4 is an explanatory diagram for describing a method for manufacturing a multilayer printed circuit board.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Inner board 2 ... Circuit pattern 3 ... Dummy via hole land part 4 ... Insulation layer 5 ... Via hole for circuit pattern connection 6 ... Dummy via hole 7 ... Full-surface plating layer 8 ... Dummy via hole plating layer 9 ... Circuit pattern connection Via-hole plating layer 10: Circuit pattern

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E338 AA03 AA16 BB02 BB13 EE27 5E346 AA43 CC04 CC32 DD12 FF04 FF13 FF15 GG15 HH11 HH16

Claims (1)

[Claims] 1. A multi-layer printed circuit board in which a circuit pattern and an insulating layer are sequentially laminated on the surface of an inner layer board to electrically connect the desired circuit patterns via a via-hole plating layer. A multilayer printed circuit board having a via hole to be connected and a via hole not to be connected to a circuit pattern.