JP2000101237A - Build-up substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve adhesion of a solid pattern and an insulating layer. SOLUTION: Concerning a build-up substrate 10 with which wiring patterns 18, 26 and 29 of plural layers are formed through insulating layers 17, 24 and 28 onto a wiring pattern 12 of a core substrate 11, the solid pattern 18 among the wiring patterns 18, 26 and 29 is provided with a through hole 40 for bridging the resins of the insulating layers 17 and 24. Thus, the resins of insulating layers are bridged to the through hole 40, and adhesion between the solid pattern 18 and the insulating layers 17 and 24 is improved. Besides, the moisture made into steam in the core substrate 11 or insulating layers is discharged to the outside by this through hole 40 and inter-layer release can be canceled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a build-up substrate capable of eliminating delamination.

[0002]

2. Description of the Related Art In a printed circuit board, a glass epoxy material (bismatrazine material, polyimide material, etc.) is used as a core, and an insulating layer (mainly a photosensitive resin layer) and a wiring pattern layer (copper A build-up board in which wiring patterns (plating films) are alternately stacked via via conduction portions is becoming mainstream as a high-density board.

In general, this build-up substrate forms a wiring pattern by forming a plating film on an insulating layer in which a via hole is formed by a photolithography method, and etching the plating film to form a wiring pattern. And it is possible to form a fine wiring pattern.

[0004]

However, as compared with the case where a wiring pattern is formed using a copper foil having a rough surface on one side, the build-up substrate has an electroless plating film on the insulating layer. Since this is formed and a plating film is further stacked on the electroless plating film by electrolytic plating, there is a problem that adhesion between the insulating layer and the wiring pattern is poor.

In addition, moisture is contained in the insulating layer, and the moisture in the insulating layer is turned into steam in a heating test or the like. Therefore, especially in the case of a solid pattern, there is no escape place of the steam, and delamination tends to occur. There are issues such as.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a build-up substrate having excellent adhesion between an insulating layer and a wiring pattern. .

[0007]

The present invention has the following arrangement to achieve the above object. That is, in the build-up board according to the present invention, in a build-up board in which a wiring pattern of a plurality of layers is formed on a wiring pattern of a core substrate via an insulating layer, Characterized in that a through hole for bridging the resin is provided.

As described above, by providing the through holes in the solid pattern, the resin of the insulating layer bridges the through holes, thereby improving the adhesion between the solid pattern and the insulating layer. In addition, the through holes allow the water vaporized in the core substrate and the insulating layer to be discharged to the outside, thereby eliminating delamination.

In the build-up board according to the present invention,
In a build-up substrate in which a plurality of wiring patterns are formed on a wiring pattern of a core substrate via an insulating layer, a solid pattern of the wiring patterns is a dummy pattern formed in the insulating layer in contact with the solid pattern. It is characterized by being connected to a pattern of an adjacent layer by a through-hole plating film.

[0010] Since the solid pattern is connected to the pattern of the adjacent layer through the dummy through-hole plating film, the adhesion between the solid pattern and the insulating layer is improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view schematically showing the build-up substrate 10. Reference numeral 11 denotes a core substrate made of a glass epoxy material. First-layer wiring patterns 12 are formed on both surfaces of the core substrate 11 by etching a copper foil. The first layer wiring patterns 12, 12 are composed of power supply layers 13, 13 formed of a solid pattern in a required area, and conductive portions 14, 14.

The conductive portions 14 on the front and back are connected to the core substrate 11.
Through-hole plating film 1 formed in through hole
5 are electrically connected. Power supply layer 1 on both sides
3 and 13 are also electrically connected at appropriate places by through-hole plating films (not shown).

On the first layer wiring patterns 12, 12, insulating layers 17, 17 made of photosensitive resin are formed. On the insulating layers 17, 17, second layer wiring patterns 18, 18 are formed. I have. The wiring patterns 18 of the second layer are
A power supply layer 20, which is formed by etching a copper layer formed to a required thickness by electroless copper plating and electrolytic copper plating on the insulating layers 17, 17 and comprising conductive portions 19, 19 and a required area; Consists of twenty.

Each conductive portion 14 and conductive portion 19 are formed by insulating layer 1
7, a copper film (via conductive portion) 19a is formed by electroless copper plating and electrolytic copper plating when forming the copper layer, thereby forming the via conductive portion 19a. As a result, electrical conduction is achieved.

Similarly, insulating layers 24, 24 made of a photosensitive resin are formed on the wiring patterns 18, 18 of the second layer.
On the insulating layers 24, 24, a third-layer wiring pattern 26,
26 are formed. This third layer wiring pattern 2
Reference numerals 6 and 26 each include a signal layer 27 formed by etching a copper layer formed on the insulating layers 24 and 24 to a required thickness by electroless copper plating and electrolytic copper plating in the same manner as described above. The signal layer 27 and the conductive portion 19 are also electrically connected by a via conductive portion similar to that shown in FIG.

Similarly, insulating layers 28 and 28 made of a photosensitive resin are formed on the third-layer wiring patterns 26 and 26, respectively.
On the insulating layers 28, 28, a fourth layer wiring pattern 29,
29 are formed. This fourth layer wiring pattern 2
Reference numerals 9 and 29 denote signal layers 30 formed by etching a copper layer formed on the insulating layer 28 to a required thickness by electroless copper plating and electrolytic copper plating in the same manner as described above.
Consisting of The signal layer 30 and the signal layer 27 are also electrically connected by a via conduction portion similar to that shown in FIG.

As described above, a multilayer wiring pattern is formed on the core substrate 11. Solder resist layers 32, 32 are formed as appropriate to cover the outermost wiring patterns 30, 30 of the above-described embodiment, and the build-up substrate 10 is completed.

When the build-up substrate 10 is used as a package on which a semiconductor chip is mounted, a semiconductor chip (not shown) is mounted on the outermost layer, and the semiconductor chip and the pad of the wiring pattern 30 on the outermost layer are connected. Electrical connection is established by wires or the like, and a bump (not shown) such as a solder ball is attached to a pad of the wiring pattern 30 on the outermost layer on the opposite side, and the bump is mounted on a mounting board by the bump.

Either of the power supply layers 13 and 20 can be used as a ground layer. These power supply layers 13 and 20
It is needless to say that electrical connection is appropriately established between the semiconductor chip and the bump via the via conduction portion of each layer.

The feature of the present embodiment lies in that a plurality of through holes 40 are formed at appropriate positions on the power supply layers 13 and 20 formed of a solid pattern.
As shown in FIG. 3, it is preferable to provide a suitable number of through holes 40 in a matrix. Note that the solid pattern is not limited to the power supply layer, and may be a dummy solid pattern in the signal layer. In this case, the formation of the through hole is effective similarly to the power supply layer.

As described above, the solid pattern power supply layer 13,
By providing a through-hole in 20 (particularly, power supply layer 20 formed by plating), insulating layers 17 and 24 made of resin are bridged through this through-hole 40, whereby power supply layer 18 and insulating layers 17 and 24 are connected. The adhesion between them is extremely good.

Further, through holes 40,
With the provision of 40, water contained in the core substrate 11 and the insulating layers 17 and 17 and vaporized by a heating test or the like is released to the outside through the space between the through holes 40 and 40 and the upper wiring pattern. Therefore, no stress is generated inside, and delamination is suitably eliminated.

In the above description, a photosensitive resin is used for the insulating layers 17, 24, and 28. However, a resin having ordinary adhesiveness may be applied or laminated to form the insulating layers. In this case, the via hole 22 can be opened by laser light. Further, the number of power supply layers 13 and 20 and the interlayer positions are not limited to the above. Further, in the above description, the core substrate 1
Although the wiring pattern is formed in multiple layers on both surfaces of the core substrate 11, the wiring pattern may be formed in multiple layers on one side of the core substrate 11.

FIG. 4 shows another embodiment. In the present embodiment, when it is not preferable to form the through-hole 40 in the power supply layer, for example, when the power supply layer is disposed immediately below the semiconductor chip to exert a shielding effect, the power supply layer and the insulating layer This is a structure that improves the adhesiveness between them.

In FIG. 4, reference numeral 42 denotes a signal layer formed on the insulating layer 44, and reference numeral 46 denotes a power supply layer composed of a solid pattern formed on the insulating layer 48 formed so as to cover the signal layer 42.
An insulating layer 50 is formed on the power supply layer 46, and a chip mounting portion 52 is formed on the insulating layer 50.

Signal layer 42, power supply layer 46, chip mounting section 5
In the same manner as described above, an electrical connection is made by a via conduction portion (not shown) as necessary, and a plating film is formed on the insulating layer by electroless plating and electrolytic plating, as described above.
The plating film is formed by etching.

When the power supply layer 46 is used as a shield layer of a semiconductor chip, it is not preferable to form the through-hole 40 described above. Therefore, a plurality of through-holes 54 are appropriately formed in the insulating layer 50, and when forming the plating film on the insulating layer 50, a dummy through-hole plating film 56 is also formed on the through-hole 54, and the plating film is formed. 56
Thereby, the power supply layer 46 and the plating film on the insulating layer 50 are mechanically connected. Then, the plating film on the insulating layer 50 is etched to form the chip mounting portion 52.
And an electrically independent pattern 58 connected to the through-hole plating film 56 is formed.

As described above, the power supply layer 46 is mechanically connected to the upper layer pattern 58 via the dummy through-hole plating film 56, and the insulating layer 50 therebetween is sandwiched between the power supply layer 46 and the pattern 58. Therefore, the adhesion between the insulating layer 50 and the power supply layer 46 is improved.

The power supply layer 46 is mechanically formed by a through-hole plating film between an independent pattern (not shown, that is, an adjacent pattern) of the layer on which the lower signal layer 42 is formed in the same manner as described above. You may make it connect. Further, when the through hole 54 is formed by a laser beam, the connection target of the pattern 58 is not limited to the power supply layer 46, but may be a dummy pattern formed in the signal layer 42, for example.

Although the present invention has been described in detail with reference to the preferred embodiments, the present invention is not limited to the embodiments, and it is noted that many modifications can be made without departing from the spirit of the invention. Of course.

[0031]

According to the build-up substrate of the present invention, the adhesion between the solid pattern and the insulating layer can be improved,
It can eliminate delamination.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing a build-up substrate.

FIG. 2 is an explanatory view showing a via conduction portion;

FIG. 3 is an explanatory diagram showing an example of a solid pattern through-hole pattern;

FIG. 4 is an explanatory diagram showing another embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Build-up board 11 Core board 12 1st-layer wiring pattern 13 Power supply layer 14 Conducting part 15 Through-hole plating film 17 Insulating layer 18 Second-layer wiring pattern 19 Conducting part 20 Power supply layer 22 Via hole 24 Insulating layer 26 Third Layer wiring pattern 27 Signal layer 28 Insulating layer 29 Fourth layer wiring pattern 30 Signal layer 32 Solder resist layer 40 Through hole 42 Signal layer 44 Insulating layer 46 Power supply layer 48 Insulating layer 50 Insulating layer 52 Chip mounting part 54 Through hole 56 Through-hole plating film 58 patterns

Claims (2)

[Claims] 1. A build-up board in which a wiring pattern of a plurality of layers is formed on a wiring pattern of a core substrate via an insulating layer, wherein a through-hole that bridges a resin of the insulating layer to a solid pattern of the wiring patterns. A build-up board having holes. 2. A build-up substrate having a plurality of wiring patterns formed on a wiring pattern of a core substrate via an insulating layer, wherein a solid pattern of the wiring patterns is formed on the insulating layer in contact with the solid pattern. A build-up substrate connected to a pattern of an adjacent layer by a formed dummy through-hole plating film.