JPH03205878A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To obtain devices capable of increasing component density of memory cells by spreading a channel region with a tunnel oxide film and by incorporating a conductivity-I semiconductor region higher doped than a conductivity-I semiconductor substrate to surround a conductivity-II drain region built in the substrate. CONSTITUTION:A semiconductor nonvolatile memory having a memory transistor that is a laminate of a floating gate FG and control gate CG is so designed that a channel region is spread with a tunnel oxide film 2a and that a conductivity-I semiconductor substrate 1 incorporates a conductivity-I semiconductor region 6 higher doped than the substrate to surround a conductivity-II drain region 5 built in the substrate 1. For example, the above-mentioned semiconductor region 6 is formed by selective ion-implantation of an n-type impurity such as arsenic, and a p-type impurity such as boron into the semiconductor substrate 1, by diffusion of these impurities, and by the fact that the n-type impurity diffuses more rapid than the n-type impurity.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor nonvolatile memory, and is particularly suitable for application to an electrically writable/erasable floating gate type semiconductor nonvolatile memory. It is.

[Summary of the invention]

The present invention provides a semiconductor nonvolatile memory having a memory transistor having a structure in which a control gate is stacked on a floating gate, in which a tunnel oxide film is formed on a channel region and in a semiconductor substrate of a first conductivity type. A first conductivity type semiconductor region having a higher impurity concentration than the second conductivity type semiconductor substrate is formed to surround the second conductivity type drain region. Thereby, it is possible to achieve high integration density of memory cells.

[Conventional technology]

E E P R O M (E1 electrically
Erasable and programmable
e Read Only Memory) is an electrically writable/erasable semiconductor nonvolatile memory.

An example of a conventional floating gate type EEFROM is shown in FIG. In FIG. 3, reference numeral 101 indicates a p-type silicon (Si) substrate, 102 indicates a gate oxide film such as a SiOz film, FG'' indicates a floating gate, and G' indicates a gate electrode. A control gate CG' is formed via a film (coupling insulating film) 103. Reference numerals 104, 105.
Reference numeral 106 indicates, for example, an n-type semiconductor region. These control gates CG' and floating gates FG'
A memory transistor is formed by semiconductor regions 104 and 105. Here, the semiconductor region 104.10
5 constitute a source region and a drain region, respectively.

Further, a selection transistor is formed by the gate electrode G' and the semiconductor regions 105 and 106. This EEP
FIG. 4 shows an equivalent circuit of a ROM memory cell. on the other hand,
Reference numeral 107 indicates a glabellar insulating film formed to cover the control gate CG", the floating gate FG", and the gate electrode G'. A contact hole 107a is formed in a predetermined portion of this glabellar insulating film 107.
Through this contact hole 107a, the semiconductor region 10
A bit line 108 is connected to 6.

Figure 5 shows another conventional floating gate type EEPRO.
Indicates M. As shown in FIG. 5, this EEPROM is
Control gate C on floating gate FG'
EE shown in Figure 3 shows that G'' has a laminated structure.
It is similar to PROM, but in this case, select gate electrodes G+ are placed below both ends of the floating gate FG.
', G2', and has a tri-gate (3-gate) structure. FIG. 6 shows an equivalent circuit of a memory cell of this EEPROM.

Regarding EEPROM, for example, see Nikkei Electronics, October 21, 1985, pp. 127-
154.

[Problem to be solved by the invention]

The conventional EEFROM shown in FIG. 3 has a structure in which one selection transistor is added to one memory transistor, and two transistors are required for each memory cell. Therefore, the area per memory cell is large, which is disadvantageous in achieving high integration density of memory cells.

On the other hand, the conventional EEPROM shown in FIG.
It can be said that each transistor has one transistor, but the select gate electrode G. ``, G.'' forms a tri-gate structure, so it is difficult to shorten the actual gate length. Therefore, it is difficult to increase the integration density of memory cells as shown in Figure 3. The problem was similar to that of the EEPROM shown in .

Accordingly, an object of the present invention is to provide a semiconductor nonvolatile memory that can achieve high integration density of memory cells.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a semiconductor nonvolatile memory having a memory transistor having a structure in which a control gate (CC) is stacked on a floating gate (FG), and a tunnel oxide film ( 2a) and a first conductivity type semiconductor substrate (1
) A first conductivity type semiconductor region (6) having a higher impurity concentration than the first conductivity type semiconductor substrate (1) is formed to surround the second conductivity type drain region (5) formed in the first conductivity type semiconductor substrate (1). There is.

[Effect]

Control gate (CG) and floating game}
The first conductivity type semiconductor substrate (1
), a source region (4) and a drain region (5) of the second conductivity type are formed. A memory transistor is formed by the control gate (CG), floating gate (FG), source region (4), and drain region (5). In this case, writing is performed by injecting carriers into the floating gate (FC) through the tunnel oxide film (2a) formed on the channel region;
Erasing is performed by extracting carriers from (FG) toward the semiconductor substrate (1).

On the other hand, the portion of the first conductivity type semiconductor region (6) that is formed to surround the second conductivity type drain region (5) and has a higher impurity concentration than the first conductivity type semiconductor substrate (1). Since the threshold voltage becomes high, even if too many carriers are extracted from the floating gate (FC) during erasing, an inversion layer is prevented from being formed in the first conductivity type semiconductor region (6). Therefore, it is possible to prevent the memory transistor from being debrised. This allows the memory state to be correctly determined.

From the above, it can be seen that electrical writing/erasing is possible, but in this semiconductor nonvolatile memory, only one transistor is required per memory cell, and there is no need for a tri-gate structure. , the area per memory cell can be reduced. Thereby, it is possible to achieve high integration density of memory cells.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an EEPROM according to an embodiment of the present invention,
FIG. 2 shows an equivalent circuit of the EEPROM memory cell shown in FIG.

In FIG. 1, reference numeral 1 indicates a semiconductor substrate such as a p-type Si substrate, and reference numeral 2 indicates a semiconductor substrate such as a p-type Si substrate. The film-like gate oxide is shown. A portion of this gate oxide film 2 above the channel region is thinner than other portions, and this portion constitutes a tunnel oxide film 2a. A floating gate FC is formed on this gate oxide film 2. Here, the floating gate FG can be formed by a first layer of polycrystalline Si film doped with an impurity such as phosphorus (P), for example. On this floating gate FG, for example, Sin. A control gate CG is laminated with an insulating film (coupling insulating film) 3 interposed therebetween. Here, this control gate CG is made of a second layer of polycrystalline St film doped with an impurity such as P, or a high melting point metal silicide such as a tungsten silicide (WSiz) film on this polycrystalline Si film. It can be formed using a polycide film in which films are stacked.

On the other hand, in the semiconductor substrate 1, an n-type source region 4 and a drain region 5, for example, are formed in self-alignment with respect to the control gate CG and the floating gate FC. And these control gate CG,
A memory transistor is formed by the floating gate FC, the source region 4, and the drain region 5.

In this embodiment, the drain region 5 is a p++ type semiconductor region 6 having a higher impurity concentration than the semiconductor substrate 1, for example.
The precepts are written to surround the . In this case, these n”
type drain region 5 and p++ type semiconductor region 6 are so-called DSA (Diffusion Self A).
It has a ligated structure. This DSA structure is
After selectively ion-implanting n-type impurities such as arsenic (As) and p-type impurities such as boron (CB) into the semiconductor substrate l, these n-type impurities and p-type impurities are diffused, and at this time, It can be formed by taking advantage of the fact that p-type impurities diffuse faster than n-type impurities.

On the other hand, a portion of the semiconductor substrate 1 below the tunnel oxide film 2a
For example, an n-type semiconductor region 7 is formed therein.

This semiconductor region 7 is for facilitating the injection of electrons into the floating gate FG. Also, code 8
9 represents, for example, a p-type channel stopper region, and 9 represents, for example, a sin. Indicates a film-like insulating film. A contact hole 9a is formed in a predetermined portion of this insulating film 9,
Bit line 10 is connected to drain region 5 through contact hole 9a. Here, this bit line 1
0 is formed by, for example, aluminum (^l) wiring.

Next, the EEP according to this embodiment configured as described above
The operation of the ROM will be explained. First, writing is performed by setting the control gate CG at a high level and the bit line 10 at a low level, and injecting electrons from the n-type semiconductor region 7 into the floating gate 1-FC through the tunnel oxide film 2a. On the other hand, erasing is performed on the semiconductor substrate 1
This is done by setting the voltage to a high level and extracting electrons from the floating gate FG to the semiconductor substrate 1 side through the tunnel oxide film 2a. Further, reading is possible by setting the control gate CG and the bit line IO to an intermediate state between high level and low level.

According to this embodiment, since only one transistor is required for each memory cell, the area per memory cell can be reduced, and therefore, the integration density of the memory cells can be increased.

Furthermore, since the threshold voltage of the p + 4 type semiconductor region 6 formed to surround the drain region 5 of the memory transistor becomes high, even if too many electrons are extracted from the floating gate FG during erasing. , it is possible to prevent an inversion layer from being formed in this p' type semiconductor region 6, and therefore to prevent deblation of the memory transistor due to excessive extraction of electrons from the floating gate FC. I can do it. Accordingly, the memory state can be correctly determined.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the above embodiment, the p~ type semiconductor region 6 and the n'' type drain region 5 have a DSA structure, but they do not necessarily have to have a DSA structure, and other structures are also possible. In addition, in the above embodiment, a type 1 semiconductor region 7 is formed in the semiconductor substrate l below the tunnel oxide film 2a, but this semiconductor region 7 may be omitted if necessary. Is possible.

Further, in the above-described embodiment, the case where writing is performed using the tunnel oxide film 2a has been described, but writing can also be performed using channel injection using hot electrons. According to this channel injection, it is possible to write at high speed.

〔Effect of the invention〕

As described above, according to the present invention, the tunnel oxide film is formed on the channel region, and the first conductive film is formed so as to surround the drain region of the second conductive type formed in the semiconductor substrate of the first conductive type. The first semiconductor substrate has a higher impurity concentration than the semiconductor substrate of the mold type.
Since a conductive type semiconductor region is formed, only one transistor is required for each memory cell, and there is no need for a tri-gate structure. Thereby, it is possible to achieve high integration density of memory cells.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an EEFROM according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of a memory cell of the EEFROM shown in FIG. 1, FIG. 3 is a sectional view showing a conventional EEFROM, and FIG. is an equivalent circuit diagram of a memory cell of the EEFROM shown in FIG. 3, FIG. 5 is a sectional view showing another conventional EEPROM, and FIG. 6 is an equivalent circuit diagram of a memory cell of the EEPROM shown in FIG. Explanation of main symbols in the drawings 1: Semiconductor substrate, 2: Gate oxide film, 2a: Tunnel oxide film, 4: Source region, 5: Drain region, 7: Semiconductor region, IO: Bit line, FG: Floating gate, CG : Control gate.

Claims (1)

[Claims] In a semiconductor nonvolatile memory having a memory transistor having a structure in which a control gate is stacked on a floating gate, a tunnel oxide film is formed on a channel region, and a first
A first conductivity type semiconductor region having a higher impurity concentration than the first conductivity type semiconductor substrate is formed to surround a second conductivity type drain region formed in the conductivity type semiconductor substrate. Semiconductor non-volatile memory.