JPH03204231A - D/a conversion circuit - Google Patents

Abstract

PURPOSE:To decrease an offset voltage and an absolute error by providing a 2nd switch connected to other electrode of a 2nd capacitance element and switching a ground level and an output of a D/A converter section. CONSTITUTION:One electrode of 1st and 2nd capacitance element CA, CB is connected respectively to an inverting input terminal (-) of an operational amplifier circuit (A1)2 an the capacitances of them are respectively A, B. A 1st switch 3 whose switching destination is either an output of the operational amplifier circuit (A1)2 or a ground level is connected to the other electrode of the 1st capacitance element CA and a 2nd switch 4 whose switching destination is either an output of the D/A converter section 1, that is, a common connecting point VX of capacitance elements C1-C4 or a ground level is connected to the other electrode of the 2nd capacitance element CB. Moreover, a switch S8 is a switch provided to reset a charge stored in the 1st and 2nd capacitance elements CA, CB to zero. Thus, the offset voltage and the absolute error and reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D/A conversion circuit, and particularly to a D/A conversion circuit using a capacitive element.

[Conventional technology]

Conventionally, there are various types of D/A conversion circuits using such capacitive elements, one of which is known as a D/A conversion circuit using a capacitive array using capacitive elements.

FIG. 4 is a D/A conversion circuit diagram showing an example of such a conventional device.

As shown in FIG. 4, this conversion circuit consists of a D/A converter 1 that converts 3 bits, and an operational amplifier circuit 2 used as a buffer.
1 to S7 are switches corresponding to inputs, terminal 5 is connected to a positive reference potential (hereinafter referred to as λ1), terminal 6 is connected to a negative reference potential (hereinafter referred to as vR2), and terminal 7 is connected to a negative reference potential (hereinafter referred to as vR2). is the output terminal (VO) of the D/A conversion circuit. Also,
In the capacitive elements 01 to C4 in the D/A converter 1, C1=C, where C is the unit capacitance.

C2=C/2. C3=C4=C/4. Capacitive element 0
One electrode of 1 to C3 is commonly connected to the (+) input terminal of the operational amplifier circuit 2, and the other electrode is connected to either terminal 5 (VRI> or terminal 6 (■8□)). Switches 81 to S6 are provided for this purpose.Also, one of the capacitive elements C4 is commonly connected like C1 to C3, and the other electrode is connected to the terminal 6 (VB2).On the other hand,
The switches 81 to S7 of the D/A converter 1 are controlled to be turned on and off by digital input signals and control signals of the D/A conversion circuit, but the digital input signal lines and control lines are omitted here.

Next, the digital input signal of the D/A conversion circuit is “
101'' as an example, its operation will be explained with reference to FIG.

FIG. 5 is a timing chart of switches for explaining the operation of the conversion circuit shown in FIG. 4.

As shown in FIG. 5, the switches 81 to S7 are turned on when the logic is at a high level, and turned off when their logic is at a low level.

First, time t. ~t1, switch 52S4. S6.
S7 is turned on, and the charges stored in 01 to C4 are reset to zero by discharging.

This time t0 to t1 is necessary only once at the beginning of starting D/A conversion. Next, at time t, S7 is turned off, and M
The digital input of SB selects one switch to turn on from each set (Sl, S2), the digital input of 23B selects (S3.S4), and the digital input of LSB selects one switch from each set (S5.S6). When the input is "'1", the switches are turned on to connect to VRI, and when the input is "'0", they are connected to VB2.As shown in FIG. S5 is on.

Here, if the potential at the point where capacitive elements 01 to C4 are commonly connected is VX, the charge stored in 01 to C4 is zero, and according to the law of conservation of charge, C(VX VRI) + (V It will be done.

[Problem to be solved by the invention]

Since the above-described conventional D/A conversion circuit using a capacitor array uses an operational amplifier circuit connected to a voltage follower as a buffer, an offset voltage of the operational amplifier circuit is added to the conversion output.

That is, the offset voltage of the operational amplifier circuit (A1) is . If it is an FF, the output Vo of the D/A conversion circuit is not given by the above equation (1), but the voltage given by Vo = V x + V OFF - (2), and the output voltage as a D/A conversion circuit is The disadvantage is that the absolute error, including zero-scale offset and full-scale offset, is worse.

An object of the present invention is to provide a D/A conversion circuit that reduces such offset voltage and absolute error.

[Means to solve the problem]

The D/A conversion circuit of the present invention includes (number of bits + 1) capacitive elements whose one electrodes are commonly connected and whose capacitance values are weighted, and the capacitive elements corresponding to each bit are commonly connected. the other of the remaining one capacitive element; a charge distribution type D/A converter having an electrode connected to the second reference potential; an operational amplifier circuit having a non-inverting input terminal connected to a ground potential; and an inverting input terminal of the operational amplifier circuit. first and second capacitive elements each having one electrode connected thereto; a first switch connected to the other electrode of the first capacitive element and switching between a ground potential and the output of the operational amplifier circuit; The device is characterized in that it includes a second switch connected to the other electrode of the second capacitive element and configured to switch between the ground potential and the output of the D/A converter.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a D/A conversion circuit diagram showing one embodiment of the present invention.

As shown in FIG. 1, this embodiment represents the same 3-bit case as the conventional example shown in FIG. 4 described above.

That is, the terminal 5 is connected to the first reference potential ■R1, the terminal 6 is connected to the second reference potential vR2, and the terminal 7 is connected to the output VO of the D/A conversion circuit. The D/A converter 1 is composed of capacitive elements 01 to C4 and switches 81 to S7, as in the conventional example described above. Operational amplifier circuit (At) 2
One electrode of the first and second capacitive elements CA, CB is connected to the inverting input terminal (-> side of A first switch 3 whose switching destination is the output of the operational amplifier (Al) 2 or the ground potential is connected to the electrode,
Further, the other electrode of the second capacitive element CB is connected to the output of the D/A converter 1, that is, to the other electrode of the second capacitive element CB.
A second switch 4 is connected to the common connection point Vx of C4, which is at ground potential. Furthermore, the switch S8 is a switch provided to reset the charges stored in the first and second capacitive elements CA, cm to zero. still,
Switches S1 to S8 corresponding to digital inputs. The signal lines for controlling the first and second switches 3.4 are omitted as in the conventional example.

Next, taking as an example the case where the digital input signal is "101", the circuit operation will be explained with reference to FIG.

FIG. 2 is a timing diagram of switches for explaining the operation of the conversion circuit shown in FIG. 1.

As shown in FIG. 2, the switches 81 to S8 are turned on when the logic is at a high level, and turned off when the logic is at a low level. However, for the first switch 3, when the control signal is at a high level ■. It is assumed that the second switch 4 is conductive to the VX side when the control signal is at a high level, and conductive to the ground potential side when the control signal is at a low level.

In this embodiment, time t1 to time t corresponds to one D/A conversion, and the D/A converted output voltage is obtained from time t2 to t3.

First, time t. During the time period from t1 to t1, the switches S2, 54S6 and S7 of the D/A converter are turned on in the same way as in the conventional example described above, and the charges stored in the capacitive elements 01 to C4 are reset to zero by discharging. In addition, since the switch S8 is on and the lower switches of the first and second switches 3 and 4 are on, the electrodes of the first and second capacitive elements C^ and CB are connected to the ground potential, and due to discharge, Capacitive element CA.

The charge stored in CB is reset to zero.

This time 1. -1. is needed only once at the beginning to start D/A conversion. The operation of the D/A converter 1 is the same as that of the conventional example described above after time t1.

Next, from time t1 to t2, the switch S8 is turned off, and the second switch 4 switches the output V of the D/A converter 1 from the ground potential side.
The connection of the first switch 3 is connected to the −(
3).

Next, from time t2 to t3, the first switch 3 is switched from the ground potential side to the VO side, and the second switch 4 is switched from the 8 side to the ground potential side. Switch S8 remains off. At this time, the first and second capacitive elements CA,
The charge Q2 stored in the inverting input terminal of CB is: Q2 = A (Vopp Vo) + BVOFF
...(4).

Since the charge is conserved between times t1 and t2 and between t2 and t3, that is, Ql=Q2, the above (3) is satisfied.
From formula and formula (4), AVOFF + B (
VOFP VX )=A(Vopp
VO)+BVOPF ・−(5).

Therefore, equation (5) and digital input signal “°101
” by substituting it into VX, we get

However, in the conventional example described above, when the operational amplifier circuit 2 has an offset voltage V□pp, from the above equation (2), V □ = V
The offset voltage VOFF of the operational amplifier circuit 2 appeared in the output VO of the conversion circuit.

On the other hand, in the present embodiment described above, as can be seen from equation (6), the output V of the D/A conversion circuit. operational amplifier circuit 2
The offset voltage V□pp does not appear. However, the operations of the first and second switches 3 and 4 in the second and subsequent D/A conversions occur at time t.

Since it is a repetition between t3 and t3, it will be omitted.

FIG. 3 is a timing diagram of a conversion circuit switch for explaining a second embodiment of the present invention.

As shown in FIG. 3, this embodiment has the same circuit configuration as that shown in FIG. 1 described above, but the control of the first and second switches 3 and 4 is different. A
The output characteristics of the conversion circuit will differ greatly. Incidentally, the timing of the switches S1 to 88 of the D/A converter 1 in FIG. 3 is the same as the timing of the switches S1 to 88 shown in FIG. 2, so a description thereof will be omitted here. Also, in this embodiment, the period between t1 and t3 and the period between t3 and t2 each correspond to one D/A conversion, and the operation of the first and second switches 3°4 between times t1 and t3 is similar to that of the above-mentioned embodiment. Similarly, the voltage expressed by equation (6) is obtained as the D/A converted output.

First time t. ~1. During this period, the switch S8 is turned on, and the first and second switches 3 and 4 connected to the ground potential side are turned on, and the charges stored in the first and second capacitive elements CA and CB are reduced to zero. Reset. This time to
~t1 is required only once at the beginning of starting D/A conversion.

Next, the second D/A conversion between times t and t5 begins.

First, the connection of the first switch 3 between times t3 and t4 is switched to the ground potential side, and the switch S8 and the second switch 4 remain in their previous states.

At this time, the charge Q3 stored on the inverting input terminal side of the operational amplifier circuit 2 of the first and second capacitive elements CA and CB becomes QS=AVOFF+BVopp·=(7).

Also, between times t4 and t5, the first switch 3 changes from the ground potential to the VO side, and the second switch 4 changes from the ground potential to the VO side.
The connection is switched to the X side. At this time, the charge Q4 stored in the inverting input terminal of the negative and second capacitive elements C^+CB is Q4=A(VOFP VO)+B(VOF
PVX)...(8) However, as in the above embodiment, from time t3 to t
4 and between times t4 and t5 (QS-
Q4), so from equations (7) and (8), A V OFF + B V 0FF = A (Vopp VO) + B (VOFF Vx)・
...(9). If we rearrange this equation (9), the output potential V.

can be expressed as Vo = Vx - (10). Therefore, the output of the D/A conversion circuit is ■. The offset l-voltage of the operational amplifier circuit 2 is . FF doesn't appear. Furthermore, the output voltage Vo obtained between times t and t5 has the opposite polarity to the output voltage obtained between times t1 and t3.

In short, with one circuit configuration as in this embodiment, in addition to the digital input, the control signal of the D/A conversion circuit can be input at time t.
Between 1 and t3, or t.

By selecting whether to do it between .about.t5, a D/A conversion circuit having an output voltage vo of both positive and negative polarities can be realized.

〔Effect of the invention〕

As explained above, the D/A conversion circuit of the present invention is provided with two capacitive elements whose one electrode is connected to the inverting input terminal of the operational amplifier circuit, and which is charged with a charge proportional to the offset voltage of the operational amplifier circuit. By storing and canceling the offset voltage of the operational amplifier circuit applied to the output, there is an effect that the zero scale offset, full scale offset, and absolute error can be reduced.

[Brief explanation of drawings]

FIG. 1 is a D/A conversion circuit diagram showing a first embodiment of the present invention, FIG. 2 is a switch timing diagram for explaining the operation of the conversion circuit shown in FIG. 1, and FIG. 3 is a diagram of the present invention. A timing diagram of a conversion circuit switch for explaining a second embodiment of
FIG. 4 is a D/A conversion circuit diagram showing an example of the conventional art, and FIG. 5 is a switch timing diagram for explaining the operation of the conversion circuit shown in FIG. 4. ], . . . D/A conversion section, 2 . . . operational amplifier circuit, 3.
...First switch, 4...Second switch, 5, 6
...Reference voltage supply terminal, 7...Output terminal, 01-C
4° CA, CB... Capacitive element, S1 to S7. S8...
・Switch element.

Claims (1)

[Claims] Digital and a switch group that connects each electrode to either a first reference potential or a second reference potential according to an input signal, and connects the other electrode of the remaining one capacitive element to the second reference potential. a charge distribution type D/A converter, an operational amplifier circuit whose non-inverting input terminal is connected to a ground potential, and first and second electrodes each having one electrode connected to the inverting input terminal of the operational amplifier circuit. a first switch connected to the other electrode of the first capacitive element and switching between the ground potential and the output of the operational amplifier circuit; and a first switch connected to the other electrode of the second capacitive element. and a second switch for switching between a ground potential and an output of the D/A converter.